KR19990075990A - Data processing systems - Google Patents

Abstract

The present invention relates to a data processing system that supports a plurality of virtual FIFOs, and more particularly, a main memory having a plurality of virtual FIFOs, and a plurality of virtual FIFOs in the main memory, based on the stored data after the tasks are stored in the main memory. A DMA controller that reads data from the host CPU stored in the host CPU, the state and data length of each virtual FIFO read from the host CPU, and transfers the data from the virtual FIFO where data writing is completed to the actual data FIFO, and from the main memory. It consists of a real data FIFO that receives data through the DMA controller and transmits it to a peripheral device in a DMA manner and provides its working status to the DMA controller, so that the start address of the virtual FIFO and the start address of valid data are always available. Due to the coincidence, the control of the FIFO is only possible with the data length value. In order to use each virtual FIFO, there is a register for changing the signal between the host CPU and the DMA controller to facilitate the status check for the switching of tasks, which minimizes the latency when the switching of tasks occurs. It is possible to control FIFO with simple DMA controller.

Description

Data processing systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system that supports a plurality of first in first output memory (hereinafter referred to as FIFO). In particular, a host CPU transfers data in a direct memory access (DMA) manner. The present invention relates to a data processing system for processing data FIFOs used when controlling a plurality of peripheral devices.

1 is a block diagram of a conventional data processing system, in which a host CPU (or controller) 101 performing main operations is configured with contents of virtual FIFOs in the main memory 102 of the system and control signals of each virtual FIFO. And control signals to the DMA controller 103 and receive DMA status or interrupts from the DMA controller 103.

The DMA controller 103 controls the data FIFO, that is, the actual FIFO 104 by the control signal received from the host CPU 101 and the control signals of the virtual FIFO read from the system memory 102. The actual FIFO 104 reads the data transmitted from the system memory 102 to the peripheral device, and simultaneously outputs the transmission data to the DMA controller 103 to check the transmission data.

Here, each virtual FIFO of the system memory 102 is configured as shown in FIG. 2, where FIG. 2A is a virtual FIFO when no wrap occurs, and FIG. 2B is a configuration of a virtual FIFO when a wrap occurs. Start address and end address are reversed.

2, there are two address pointers 201 and 202 that contain valid data in a portion of system memory 102 that is used as a virtual FIFO and store addresses indicating the beginning and end of valid data.

That is, the system memory 102 has a number of queues called virtual FIFOs. As an example, three virtual FIFOs are used to describe the operation.

In this case, the virtual FIFO is used to drive the peripheral device, and the actual transmission occurs from the virtual FIFO of the main memory 102 via the actual FIFO 104.

Here, the DMA controller 103 may or may not have an internal processing function as part of the peripheral subsystem, which is controlled by a program (software or firmware) of the host CPU 101. The actual FIFO 104 is also implemented as part of the peripheral subsystem. And while using multiple virtual FIFOs, it is only one virtual FIFO at a time that the actual transmission takes place.

That is, when the virtual FIFO required in the system memory 102 is selected by the host CPU 101, and a control signal for this is output from the host CPU 10 to the DMA controller 103, the DMA controller 103 generates a host CPU ( After reading the control signal of the virtual FIFO in the system memory 102 using the control signal received from 101), the contents of the virtual FIFO are read from the start address and transmitted to the peripheral device via the actual FIFO 104.

At this time, the start address and the end address have the same value so that the peripheral device can be used for additional work to leave the FIFO empty when a task change occurs.

However, the conventional data processing system described above has the following problems.

First, when a switchover occurs, additional work is required to leave the actual FIFOs empty, resulting in significant delays in the switched tasks.

Second, the peripheral and system memory must keep the start and end addresses at the same value, which is very difficult to control.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use a data FIFO when the host CPU controls a plurality of peripheral devices supporting DMA data transmission. By providing a virtual FIFO existing in the memory, to provide a data processing system that makes the transfer of data simple and efficient.

1 is a block diagram of a conventional data processing system

FIG. 2A is a detailed block diagram of the virtual FIFO when no wrap occurs in FIG.

FIG. 2B is a detailed block diagram of a virtual FIFO when a wrap occurs in FIG. 1. FIG.

3 is a block diagram of a data processing system according to the present invention;

4 is a detailed block diagram of the virtual FIFO of FIG.

5 is a detailed block diagram of the DMA controller of FIG.

6 is a block diagram showing another embodiment of a data processing system according to the present invention;

Explanation of symbols for main parts of the drawings

301: host CPU (or controller) 302: DMA controller

303: real FIFO 304: system memory

313: Virtual FIFO in System Memory

401: status register 402: data length register

403: current address pointer 501: control unit

502: start address register 503: DMA control register

504: DMA status register 505: V-FIFO status register

506 data length register 507 current address register

A feature of the data processing system according to the present invention for achieving the above object is, the main memory having a plurality of virtual FIFO, and after storing the respective tasks in the main memory based on the processed data based on the main The host FIFO stored in the virtual FIFO in the memory and the state and data length of each virtual FIFO read from the host CPU under the control of the host CPU are read, and data is read from the virtual FIFO where data writing is completed to the actual data FIFO. The DMA controller transmits data received from the main memory through the DMA controller, transfers the data to the peripheral device in a DMA manner, and provides its working status to the DMA controller.

Another feature of the data processing system according to the present invention is a main memory having a plurality of virtual FIFOs, a host CPU which manages the contents of the virtual FIFOs in the main memory and control signals of each virtual FIFO, and under the control of the host CPU. It checks the status and data length of the virtual FIFO read from the host CPU and controls the actual data FIFO according to the result, and saves the transmission data received from the peripheral device in the virtual FIFO in the main memory and at the same time performs its own work. It consists of an actual data FIFO that provides status to the DMA controller.

This data processing method facilitates status checking for job switching, minimizing latency when job switching occurs, and enables FIFO control with a simple DMA controller.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a data processing system according to the present invention, which is composed of a host CPU (or controller) 301, a DMA controller 302, an actual FIFO 303, and a system memory 304.

The host CPU 301 manages the contents of the virtual FIFOs 313 and the control signals 312 of each virtual FIFO present in the main memory 304 of the system via a host data bus, and also controls the DMA controller ( The control signal Ctrl is sent to the 302, and the main operation such as receiving a status Stat or an interrupt Int. From the DMA controller 302 is performed. The DMA controller 302 reads the control signal received from the host CPU 301, the status signal of the virtual FIFO and the length of data from the system memory 304 through the DMA data bus, and controls the actual FIFO 303. In addition, the actual FIFO 303 transmits the transmission data read from the system memory 304 to the peripheral device and transmits its operation status to the DMA controller 302. At this time, the write data of the host CPU 301 is input to the main memory 304 through the host data bus.

Here, the configuration of each virtual FIFO of the system memory 304 is as shown in FIG.

4, part of the system memory 304 used as the virtual FIFO 313 contains valid data and the beginning of the valid data always coincides with the beginning of the virtual FIFO 313 and stores an address indicating the end. There is a data length register 402 and an address pointer 403 indicating the current data address, and is composed of a status register 401 for storing information such as read / write, access function, and halt.

FIG. 5 is a block diagram illustrating the configuration of the DMA controller 302. The state register 504, which stores its state and outputs an interrupt signal according to its state and the state thereof, is identified. Read from the V-FIFO status register 505, the DMA control register 503 for storing the control signal provided from the host CPU 301 and the start pointer of the data, the start address 502, and the virtual FIFO 313, respectively. A data length register 506 which stores the length of the data, a current address register 507 which stores the read address created in the DMA controller 302, and a controller 501 which collectively controls these registers and controls the actual FIFO 303. It consists of.

In the present invention configured as described above, the host CPU (or controller) 301 performing the main task stores the respective tasks in the system memory 304.

This includes the starting pointer information of the data to be sent (that is, it can be a real address or other information that can calculate a real address), the length of the data (which covers the entire task to be performed), peripheral information, current status, etc. Is stored. Based on this, the host CPU 301 stores the processed data in the virtual FIFO 313 of the system memory 304.

How to save is as follows.

That is, the status register 401 of the virtual FIFO 313 is read and analyzed, and its status is divided as follows.

1. FIFO write enabled: FIFO empty, not used by DMA controller 302.

2. FIFO Readable: The FIFO is not empty and is not used by the host CPU 301.

3. Writing FIFO: The host CPU 301 is using the FIFO.

4. Reading FIFO: The FIFO is being used by the DMA controller 302.

Then, it is checked whether all previous output data by the task has been transmitted. This means that if the status register is set by checking the writeable mode, all previous data has been transferred. If all of the previous output data has been transmitted, the virtual FIFO becomes empty and if it is determined that the virtual FIFO is empty, the host CPU 301 generates the readable bit of the status register 401 and resets the writeable bit. Write new data to the area. In this case, the start address always matches the start address of the virtual FIFO. After the data has been written out, the data length register 402 stores the length of the written data and the status register 401 is in a readable mode.

At this time, the DMA controller 302 reads each virtual FIFO in a predefined order. First, the DMA controller 302 checks the status register 401 of the virtual FIFO to find out whether it is in a readable mode. If this bit is in the reset state, the next virtual FIFO is read in the predefined order. If this bit is set, this indicates that data write is completed to the FIFO. At this time, the DMA controller 302 reads data from the virtual FIFO and then transmits the data to the peripheral device via the actual FIFO 303.

To do this, first, the writeable bit of the status register 401 is reset, the writeable bit is set, and then the data length register 402 is read to move data of the data length from the start address of the virtual FIFO to the actual FIFO 303. Let's do it.

After the data has been read, the data length register 402 is cleared and the status register 401 is in the writeable mode.

The actual FIFO 303 transfers the data read from the system memory 304 to the peripheral device in a DMA manner, and transmits a status of whether the operation is completed or completed to the DMA controller 302.

6 shows that another embodiment of the present invention can be applied to a bidirectional DMA communication. That is, the actual FIFO 303 may write and read data input from the peripheral device to the virtual FIFO in the system memory 304 by the host CPU 301 and the DMA controller 302.

As such, when the host CPU controls a plurality of peripheral devices that support DMA data transfer, only one actual data FIFO is used and the remaining operations use virtual FIFOs existing in memory. Suitable for controllers that run in parallel.

As described above, according to the data processing system of the present invention, since the start address of the virtual FIFO and the start address of the valid data are always matched, the FIFO can be controlled only by the data length value. In addition, in using each virtual FIFO, a register for handling handshaking between the host CPU and the DMA controller facilitates the status check for the switching of tasks. The advantage is that it can be minimized and FIFO control is possible with a simple DMA controller.

Claims (5)

A data processing system comprising a host CPU performing main operations, an actual data FIFO transmitting data to peripheral devices, a DMA controller controlling the actual FIFO under control of the host CPU, and a main memory having a plurality of virtual FIFOs. In The host CPU stores the respective tasks in the main memory and stores the processed data in the virtual FIFO in the main memory based on the tasks. The DMA controller checks the state and data length of each virtual FIFO read from the host CPU under the control of the host CPU, reads data from the virtual FIFO where data writing is completed, and transmits the data to the actual data FIFO. And the actual data FIFO receives data read from the main memory through the DMA controller and transmits the data to the peripheral device in a DMA manner and provides its working status to the DMA controller. The method of claim 1, And a portion of main memory used as the virtual FIFO contains valid data, and the start address of the valid data always matches the start address of the virtual FIFO. The method of claim 1 wherein the virtual FIFO is A data length register for storing an address indicating the end of valid data; An address pointer indicating the current data address, A data processing system comprising a status register for storing information such as read / write, access function, and holt. The method of claim 1, wherein the DMA controller, A state register that stores its state, A V-FIFO status register to determine the status of the virtual FIFO, A control register for storing a control signal provided from the host CPU; A start address register for storing a start pointer of data received from the host CPU; A data length register for storing a length of data read from the virtual FIFO; A current address register for storing a read address created in the DMA controller; And a control unit for controlling the registers and the actual data FIFO. A data processing system comprising a host CPU performing main operations, an actual data FIFO transmitting data to peripheral devices, a DMA controller controlling the actual FIFO under control of the host CPU, and a main memory having a plurality of virtual FIFOs. In The host CPU manages the contents of the virtual FIFOs in the main memory and the control signals of each virtual FIFO, The DMA controller checks the state and data length of the virtual FIFO read from the host CPU under the control of the host CPU, and controls the actual data FIFO according to the result. And the actual data FIFO stores its transmission data received from a peripheral device in a virtual FIFO in main memory and provides its working status to the DMA controller.