JP2000132527A - Inter-processor communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the change of a system constitution and also to make significantly improvable the flexibility of an inter-processor communication controller by providing a buffer which receives the inter-processor communication requests and stores them and a communication destination port number generation circuit which generates the communication destination port numbers based on each communication destination device number. SOLUTION: The inter-processor communication controller 40 receives the inter-processor communication requests from a crossbar switch 20 and stores these requests in a buffer 50 in the receiving order of them. A buffer control circuit 60 reads an inter-processor communication requests out of the buffer 50. The communication destination device type and number included in the read communication request are sent to a communication destination port number generation circuit 70 where a communication destination port number is generated. This port number is added to the inter-processor communication request and sent to the switch 20. Thus, it is possible to deal with the change of the positions or the number of processors just by changing the contents of a port number rereading register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-processor communication control device, and more particularly to an inter-processor communication control device in a system having a plurality of processors.

[0002]

2. Description of the Related Art A multiprocessor system using a plurality of processors to increase the operation and processing speed is well known. It is anticipated that the need for multiprocessor systems will also increase as processor costs become relatively inexpensive and the need for faster arithmetic / processing speeds increases.

In such a multiprocessor system,
Communication between the processors is required to operate a plurality of processors efficiently, and an inter-processor communication control device is inevitably used. An example of a conventional inter-processor communication control device is disclosed in, for example, an inter-processor communication system disclosed in Japanese Patent Application Laid-Open No. 3-58162. Such a conventional interprocessor communication control device will be briefly described with reference to FIG.

[0004] A plurality of processors 11, 12, ..., 1m
, A system bus 2 used for communication between the processors, and a plurality of processor interface circuits 31 for performing one-to-one communication with the processors 11, 12,.
3m, and a memory access control circuit 4 for controlling read access and write access to the memory circuit 5 in response to requests from the processor interface circuit and the inter-processor communication access control circuit 6.

Further, a memory circuit 5 for storing common information of the multiprocessor system and for temporarily storing communication data between the processors 11, 12,..., 1m.
, Processor interface circuits 31, 32,.
and a communication control memory circuit 7 that is connected to the inter-processor communication access control circuit 6 in response to a request from the processor m and stores communication control information between the processors 11, 12,..., 1m.

[0006] For example, from processor 11 to processor 1
When performing data transfer to 2, the processor 11 first writes transfer data to a free area of the memory circuit 5 via the processor interface circuit 31 and the memory access control circuit 4.

Next, the processor 11 determines the processor number of the communication source processor 11 and the processor 12 of the communication destination.
The communication control information such as the processor number and the storage address of the transfer data in the memory circuit 5 is written to the free space of the communication control memory circuit 7 via the processor interface circuit 31 and the inter-processor communication access control circuit 6.

When the communication control information is written in the communication control memory circuit 7, the inter-processor communication access control circuit 6 extracts the communication control information from the communication control memory circuit 7. The read access to the memory circuit 5 is made to the communication destination processor 12 via the processor interface circuit 32 in accordance with the extracted communication control information.
Together with the storage address of the transfer data in.

Thereafter, the inter-processor communication access control circuit 6 monitors the memory access control circuit 4 to determine whether or not a read access to the storage address of the transfer data of the memory circuit 5 has been performed from the communication destination processor 12. To check.

If the processor 12 of the communication destination has made a read access to the storage address of the transfer data in the memory circuit 5, the inter-processor communication access control circuit 6 considers that the data transfer has been completed, and It notifies the processor 11 of the end of the data transfer.

According to the above-described conventional inter-processor communication control device, since the processors and their corresponding processor numbers are fixedly determined, the physical positions of the processors are changed or the number of processors is increased or decreased. In such a case, there is a problem that it is not easy to change the system configuration because it is necessary to change software for performing inter-processor communication.

According to the conventional device, the transfer data is stored in a memory circuit separate from the communication control information.
Since the operations of writing and reading to and from the memory are useless, there is a problem that the processing time of the communication between the processors is long.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inter-processor communication control device capable of easily changing the system configuration, that is, changing the physical position of a processor or changing the number of processors.

It is another object of the present invention to provide an inter-processor communication control device capable of reducing the processing time of inter-processor communication.

[0015]

In order to solve the above-mentioned problem, an inter-processor communication control device according to the present invention employs the following characteristic configuration.

(1) An inter-processor communication control device including a plurality of processors and controlling communication performed between the plurality of processors, a buffer for receiving and storing an inter-processor communication request issued from the processor; A communication destination port number generating circuit for generating a communication destination port number based on a destination device number.

(2) The communication destination port number generation circuit includes:
The inter-processor communication control device according to (1), further including a port number rewriting register for changing configuration information according to the configuration of the processor.

(3) The destination port number generation circuit includes:
The inter-processor communication control device according to the above (2), further comprising a multiplexer connected to an output side of the port number rewriting register.

(4) An inter-processor communication control device that includes a plurality of processors and arbitrates an inter-processor communication request between the plurality of processors, based on a communication destination device type and a device number included in the inter-processor communication request. An inter-processor communication control device including a communication destination port number generation circuit for generating a communication destination port number.

(5) A buffer for storing an inter-processor communication request from a processor, a buffer control circuit for controlling the buffer, and a communication destination port for generating a communication destination port number based on communication destination information of the inter-processor communication request An inter-processor communication control device including a number generation circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of an inter-processor communication control device according to the present invention will be described below in detail with reference to the accompanying drawings, particularly FIGS.

FIG. 1 is a block diagram showing the configuration of an interprocessor communication control device of the present invention and a multiprocessor system using the same. This multiprocessor system includes a plurality of processors 10 to 16, a crossbar switch 20 connected to the processors 10 to 16, a main storage device 30, and an inter-processor communication control device 40. The plurality of processors 10 to 16 are
Issue a request to 0. The crossbar switch 20 performs switching by arbitrating such a request and an inter-processor communication request. The interprocessor communication control device 40 controls interprocessor communication between the processors 10 to 16.

Here, the processors 10 to 13 are the central processing units CPU0, 1, 2, and 3, respectively.
Reference numeral 15 denotes input / output devices IOP0 and IOP1, and a processor 16
.. Means an inter-note connection device RCU, which are connected to ports 0, 1,..., 6 of the crossbar switch 20, respectively.

The inter-processor communication control device 40 includes:
Processor 1 sent from crossbar switch 20
, 16, a first-in first-out (FIFO) buffer 50 for temporarily storing inter-processor communication requests, a buffer control circuit 60 for controlling the buffers 50, and communication included in the inter-processor communication requests. A destination port number generation circuit 70 for generating a destination port number from the destination device type and the destination device number.

The communication destination port number generation circuit 70 of the inter-processor communication control device 40 shown in FIG.
The following configuration is acceptable. That is, in the example of FIG. 2, the communication destination port number generation circuit 70 includes a port number reading register 71 and multiplexers 72, 73, and 74. On the other hand, the communication destination port number generation circuit 70 of FIG. 4 includes a port number rewriting register 71 and a multiplexer 75. The port number rewriting register 71 stores the port number of the crossbar switch 20 to which the processors 10 to 16 corresponding to the communication destination device type and the communication destination device number are connected.

Next, the operation of the multiprocessor system shown in FIG. 1 will be described. When reading / writing (reading / writing) to / from the main storage device 30, the processors 10 to 16 issue a command 31 indicating that the request is to the main storage device 30, as shown in FIG. ,
The address 32 and the data 33 (valid at the time of writing) in the main storage device 30 are set and transmitted to the crossbar switch 20.

In the crossbar switch 20, a request from each of the processors 10 to 16 is arbitrated between the ports 0 to 6, and a command in the request is transmitted to the main storage device 3.
If the request is for 0, the request is sent to the main storage device 30. The main storage device 30 that has received the request performs an operation corresponding to the command 31 in the request, and returns a reply (response) to the crossbar switch 20. Crossbar switch 2
0 returns the reply from the main storage device 30 to the communication source processors 10 to 16.

Next, the case where the processors 10 to 16 perform inter-processor communication will be described. As shown in FIG. 3B, a command 34 indicating that the request is inter-processor communication, a communication destination device type 35 indicating the type of a communication destination processor such as CPU, IOP, or RCU, a CP
The communication destination device number 36, the communication source device type 37, the communication source device number 38, and the data 3 to be transmitted to the communication destination device added to each device having the same device type such as U0, 1, and 2.
9 is transmitted to the crossbar switch 20.

Therefore, in the crossbar switch 20, requests from the processors 10 to 16 are transmitted to the ports 0 to 6 respectively.
If the command 34 in the request is inter-processor communication, the request is sent to the inter-processor communication control device 40.

Here, actually, the crossbar switch 2
At 0, the request for the main storage device 30 and the inter-processor communication request are arbitrated and switched at the same time.

Next, the inter-processor communication control device 40 stores the inter-processor communication requests received from the crossbar switch 20 in the buffer 50 in the order of reception. If the crossbar switch 20 can receive data from the inter-processor communication control device 40, the buffer control circuit 60 reads the stored inter-processor communication request from the buffer 50.

The destination device type 35 and the destination device number 36 in the read request are sent to the destination port number generation circuit 70, and the destination port number is generated. The generated communication destination port number is added to the inter-processor communication request received from the crossbar switch 20 and sent to the crossbar switch 20.
The crossbar switch 20 that has received it sends the inter-processor communication request to the port indicated by the communication destination port number.

Further detailed operation of the inter-processor communication control device 40 will be described below with reference to FIG. 2 which shows a detailed block diagram of the communication destination port number generation circuit 70.

The (A), (B), (C), (D), and (E) of the port number rewriting register 71 are connected to CPUs 10 to 13 in FIG.
(F), (G), and (H) are in the IOP, and (I) is in the RCU.
16 is stored in the port number of the crossbar switch 20 connected to the switch 16. Here, a case where the number of CPUs is a maximum of five, the number of IOPs is a maximum of three, and the number of RCUs is one is shown.

Next, the port number rewriting register 71
Is set when the system is started up in accordance with the system configuration. In the example of FIG. 1, the processor 1 connected to the ports 0, 1, 2, and 3 of the crossbar switch 20
Since 0, 11, 12, and 13 are CPUs 0, 1, 2, and 3, (A), (A),
(B), (C), and (D) store 0, 1, 2, and 3, respectively.

Since the processors 14 and 15 connected to the ports 4 and 5 are IOP0 and IOP1, respectively, (F) and (G) of the port number rewriting register 71 have 4,
5 is stored and the processor 1 connected to the port 6
Since 6 is an RCU, 6 is stored in (I) of the port number rewriting register 71. Then, (E) of the port number rewriting register 71 which is not connected at all.
And (H) are unused.

Here, for example, when the communication destination device type SL1 is CPU and the communication destination device number SL2 is 2, the communication destination device type SL1 acts on the multiplexer 74 and the communication destination device number SL2 acts on the multiplexer 72. . Therefore, 2 is output as the communication destination port number PN.

The port 5 of the crossbar switch 20
Consider a system configuration in which the IOP1 connected to the CPU is replaced with the CPU3. In this case, 5 is stored in (E) of the port number rewriting register 71,
(G) is unused.

The case where the communication destination port number generation circuit 70 is configured as shown in FIG. 4 will be briefly described. In this case,
Separate device numbers are set for all processors connected to the crossbar switch 20 irrespective of the type of device. When reading the port number from the port number rewriting register, only the device number is used. This eliminates the need for the device type of the inter-processor communication request, so that the hardware can be simplified as compared with the case of FIG.

The configuration and operation of the preferred embodiment of the interprocessor communication control device according to the present invention have been described above in detail. However, the present invention should not be limited to only such specific examples, and those skilled in the art can easily understand that various modifications can be made according to specific applications.

[0041]

As will be understood from the above description, according to the interprocessor communication control device of the present invention, when the physical position or the number of processors is changed, only the contents of the port number replacement register are changed. Therefore, it is easy to change the system configuration, and the flexibility can be greatly improved.

Further, according to the interprocessor communication control device of the present invention, the interprocessor communication can be processed only by the interprocessor communication control device, so that the interprocessor communication can be performed at a high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of an interprocessor communication control device of the present invention and a multiprocessor system using the same.

FIG. 2 is a detailed block diagram of an example of a communication destination port number generation circuit of the inter-processor communication control device of FIG. 1;

FIG. 3 is a diagram illustrating an example of a read / write request to the processor of FIG. 1;

FIG. 4 is a block diagram of a modification of the communication destination port number generation circuit.

FIG. 5 is a block diagram of a conventional interprocessor communication control device.

[Explanation of symbols]

10 to 16 processor 40 inter-processor communication control device 50 buffer 60 buffer control circuit 70 destination port number generation circuit 71 port number read register 72 to multiplexer SL1 destination device type SL2 destination device number PN destination port number

Claims (5)

[Claims] 1. An inter-processor communication control device including a plurality of processors and controlling communication performed between the plurality of processors, a buffer for receiving and storing an inter-processor communication request issued from the processor, and a communication destination A communication destination port number generation circuit that generates a communication destination port number based on the device number. 2. The inter-processor communication control device according to claim 1, wherein the communication destination port number generation circuit includes a port number replacement register that changes configuration information according to a configuration of the processor. 3. The inter-processor communication control device according to claim 2, wherein the communication destination port number generation circuit has a multiplexer connected to an output side of the port number rewriting register. 4. An inter-processor communication control device that includes a plurality of processors and arbitrates inter-processor communication requests between the plurality of processors, the communication destination based on a communication destination device type and a device number included in the inter-processor communication request. An inter-processor communication control device comprising a communication port number generation circuit for generating a port number. 5. A buffer for storing an inter-processor communication request from a processor, a buffer control circuit for controlling the buffer, and a destination port number for generating a destination port number based on destination information of the inter-processor communication request. An inter-processor communication control device comprising: a generation circuit.