KR0145932B1 - Dma controller in high speed computer system - Google Patents

Abstract

This DMA controller is suitable for high speed data transfer rate in high speed medium computer system, and transfers the first address data of main memory provided to main memory address register / counter by using the upper address line of processor. / Counter and buffer memory address register / counter to configure the processor to be accessed at the same time, the size register and the control / status register in a single register structure to be selected using a single select signal, and data transfer with the processor In the case of the size register, the upper data line is used and in the control / status register, the lower data line can be configured so that the processor can reduce the number of accesses for DMA control.

Description

DM controller in high speed medium computer system

1 is a block diagram of a high speed medium computer system having a conventional DM controller,

2 is a relationship diagram between a DM controller and a processor on the input / output processing board side according to the present invention.

* Explanation of symbols for main parts of the drawings

200: processor 210: DMA controller

211: Main memory address register and counter

212: Buffer memory address registers and counters

213: Size register 214: Control and status register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access (DMA) controller in a high speed medium computer system having a multiprocessor structure, and more particularly to a DMA controller configured for high speed data transfer.

In general, the DMA controller exists between the memory and the input / output processing unit, and is used to directly input / output data to the memory at high speed without passing through a processor (also called a central processing unit (CPU)). The conventional DMA controller was configured to access each of the registers configured therein from the processor on the I / O side using the same data line.

Referring to the DMA controller in the high speed medium computer system shown in FIG. 1, the control relationship between the above-described DMA controller and the processor on the input / output processing side will be described in more detail as follows.

As shown, the DMA controller 110 includes a main memory address register / counter 111 and an input / output processing unit board for providing a read / write address for the main memory board 160 which is a system memory of a high-speed medium computer system. A buffer memory address register / counter 112 for providing a read / write address of the buffer memory 120 on the side 140, a size register 113 having data for the data transfer amount, and a control register for controlling the DMA operation. (114), a state register (115) having data on the progress of the DMA, and if a DMA transfer is requested from the processor (100) on the I / O processing board side, it is transmitted through a low address line (Low Address Line). The main memory address register / counter 111 writes the data value transmitted through the all data line according to the register select signal. It becomes. At this time, the first address value of the read mode (or write mode) of the main memory board 160 is written in the data transmitted from the processor 100. The address value is multiplied by counting up or down during data transfer.

The processor 100 transmits a register select signal so that the buffer memory address register / counter 112 is selected through the lower address line, and the first address of the write mode (or read mode) of the buffer memory 120 through all the data lines. Is transferred to the buffer memory address register / counter 112. At this time, the address value is also counted up or down at each data transfer as in the main memory address register / counter 111.

The processor 100 then transmits a register select signal through the lower address line so that the size register 113 can write data transmitted over the data line. Accordingly, the size register 113 stores data on the amount of transmission provided from the processor 100, and the buffer memory 120 to the main memory board 160 through the system bus connection unit 130 and the system bus 150. It controls the amount of data to be transmitted or the amount of data to be transferred in the above-described process and the reverse process. When data is transferred by the amount of data stored in the size register 113, the main memory address register / counter 111 and the buffer memory are described. The count value of the address register / counter 112 is up or down to change the claimed address value.

The processor 100 then transmits a register select signal to select the control register 114 through the lower address line and a DMA GO command to actually perform a DMA transfer command using the data line.

Accordingly, the control register 114 performs DMA transfer. When the DMA transfer is completed, the control register 114 transmits an interrupt signal to the processor 100, and the interrupted processor 100 sets the state register 115 to check whether there is an error in the DMA transfer and transfer completion. The register select signal is transmitted through the lower address line for access, and the data stored in the state register 115 is read through the data line. If it is determined that the transmission is completed by analyzing the value of the read state register 115, the DMA request is withdrawn.

As described above, the conventional DMA controller 110 selects a register to process data transmitted through the data line by the register select signal transmitted through the processor 100 and the lower address line, and selects the register selected using all the data lines. Since the processor 100 transfers data between the processor and the processor 100, the processor 100 performs access control several times until the DMA command is executed, thereby delaying the data processing speed and increasing the processing burden of the processor.

In addition, the amount of data transmitted between the size register 113, the control, and the state registers 114 and 115 and the processor 100 has a problem of inefficient operation due to the presence of unused data lines because all data lines are not used.

This may cause a decrease in the efficiency of the system bus in the case where the high speed medium computer system has a symmetrical structure and requires DMA on the side of the main processor board not shown through the system bus 150.

Accordingly, an object of the present invention is to provide a DMA controller suitable for a high data rate in a high speed medium computer system.

In order to achieve the above object, an apparatus according to the present invention is a DMA controller of a high speed medium-size computer system having a DMA controller between an input / output processing board and a main memory board: a lower address of a processor in the input / output processing board. When selected by the register select signal transmitted through the line, the main memory address register stores the first address data for the main memory board transmitted through the upper address line of the processor, and changes the address data to the next address every time data is transferred. /counter; When selected by the register select signal transmitted through the lower address line of the processor, the first address data of the buffer memory on the I / O processing board side transmitted through the entire data line of the processor is stored, and the address data is transferred after each data transfer. A buffer memory address register / counter that changes to an address; A size register for controlling the amount of data transmission amount (or transmission size) transmitted from the processor by using the upper data line of the processor when selected by the register select signal of the processor; When selected by the register select signal of the processor, the DMA operation control signal (DMA GO signal) provided from the processor is stored using the lower data line of the processor to control the DMA operation, and the DMA operation state data at the request of the processor. It is characterized by consisting of a control / status register for transmitting to the processor.

Next, another embodiment of the present invention will be described in detail with reference to FIG. 2.

FIG. 2 shows a detailed diagram of the DMA controller and the processor on the input / output processing board side according to the present invention. The DMA controller 210 performs a main memory address register / counter performing the same function as in FIG. 211, a buffer memory address register / counter 212, a size register 213, and a control and status register 214. In particular, the size register 213 and the control and status register 214 consist of one register. The processor 200 transmits data to be transmitted to the main memory address register / counter 211 using a high address line, and uses a low address line of the DMA controller 210. Transmit register select signal, transfer data to buffer memory address register / counter 212 using all data lines, and all data lines to size register 213 consisting of one register and control / status register 214 The upper data line is configured for the size register 213 and the lower data line is used for the control / status register 214.

The DMA controller 210 and the processor 200 of FIG. 2 configured as described above are operated as follows.

First, since the data to be transmitted to the main memory address register / counter 211 and the buffer memory address register / counter 212 use different data lines, the processor 200 may register the above-described registers 211 and 212 through lower address lines. The register select signal is transmitted to be selected at the same time, the first address signal for the write (or read) mode of the main memory board is transmitted through the upper address line, and the first address signal of the buffer memory 120 is transmitted through all the data lines. The first address signal is stored in each register 211, 212.

Since the size register 213 and the control / status register 214 are constituted by one register, when the size register 213 and the control / status register 214 are selected by the register select signal applied through the lower address line, the data transferred through the entire data line is the size register 213. And control / status register 214. At this time, the data for the transmission size of the data to be transmitted is transmitted through the upper data line, and the data for the DMA GO command is transmitted through the lower data line. In this case, since the size register 213 and the control / status register 214 are configured as one register as described above, the size register 213 and the control / status register 214 may be simultaneously selected by the processor 200, but data transmission is controlled by the processor 200. It may not be done at the same time.

When the data transfer operation for the DMA operation of the processor 200 is completed as described above, the DMA controller 210 performs the DMA operation under the control of the control / status register 214.

When data transfer between the main memory board 160 and the buffer memory 120 is completed by the DMA operation, the control / status register 214 of the DMA controller 210 transmits an interrupt signal to the processor 200 and sends an interrupt signal. The received processor 200 accesses the control / status register 214 to confirm whether there is an error in the DMA transfer and the completion of the transfer. After analyzing the accessed data and determining that the transmission is completed, the processor 200 withdraws the DMA request.

As described above, the present invention has the advantage of improving the DMA transfer rate by reducing the number of register accesses in the DMA controller by efficiently using an upper address line which is not used when the processor requests the DMA to the DMA controller, and also controlling / Improve the system efficiency by using the status register and size register as one register so that the upper data line is used for the size register and the lower data line is used for the control / status register so that the data transmission line can also be used as a pool. There is.

Claims (2)

In the DMA controller of the multi-processor high speed medium computer system having a DMA controller between the I / O processing board and the main memory board, the DMA controller is selected by a register select signal transmitted through a lower address line of the processor in the I / O processing board. A main memory address register / counter for storing the first address data for the main memory board transmitted through the upper address line of the processor, and for changing the address data to the next address every time data is transmitted; When selected by the register select signal transmitted through the lower address line of the processor, the first address data of the buffer memory on the I / O processing board side transmitted through all the data lines of the processor is stored, and every data transfer. A buffer memory address register / counter for changing the address data to the next address; A size register configured to control an amount of data transmission amount (or transmission size) transmitted from the processor by using an upper data line of the processor when selected by the register select signal of the processor; When selected by the register select signal of the processor, a DMA performance control signal (DMA GO signal) provided from the processor is stored using a lower data line of the processor to control the DMA operation, and to the request of the processor. And a control / status register for transmitting DMA operation status data to the processor. The method of claim 1, wherein the size register and the control / status register are configured as one register so that the processor selects the size register and the control / status register at the same time by providing one register select signal. DMA controller in high speed medium computer system.