JPH0644193A - I/o register access system - Google Patents

Abstract

PURPOSE:To shorten the access time of a register by means of a main processor. CONSTITUTION:A two-port register 12 which can be accessed from both main processor 20 and CPU 11 is prepaired and a writing end status is prepaired inside the two-port register 12. The writing end status is set by CPU 11 when writing ends. Then, it is cleared when the main processor 20 writes data in the two-port register 12. When the main processor 20 performs writing access to the two-port register 12, arrangement is executed by an interrupting signal so as to inform CPU 11 of it. CPU 11 can judge to which address access is performed by detecting the writing end status by an interruption processing. At the time of reading access from the main processor 20 to the two-port register 12, no information is given to CPU 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to I / O in an I / O device controlled by firmware of an information processing system.
The present invention relates to an O register access method.

[0002]

2. Description of the Related Art Conventionally, as an I / O device of an information processing system, there are various devices such as a DMA controller, a magnetic disk device and a printer. Such an I / O device is controlled by built-in firmware. Data is exchanged between the firmware and the main processor via a built-in register. In this case, with respect to the access to the register of the I / O device by the main processor, the response is kept waiting until the processing by the firmware is completed.

[0003]

However, the above-mentioned conventional technique has the following problems. That is, in the above-described method, the main processor has to wait for the processing of the firmware each time the register of the I / O device is accessed, which causes a problem that the processing time increases. The present invention has been made in view of the above points, and it is an object of the present invention to provide an I / O register access method that shortens register access time and is excellent in cost performance.

[0004]

According to the I / O register access method of the present invention, when an I / O device is controlled by register access by a main processor, the main processor and the control device of the I / O device are connected to each other. A two-port register accessible from both sides is prepared, data is read from the register without reporting to the control unit at the time of read access to the register, and data is read from the register at the time of write access to the register. The write access is ended at the end of this writing, and the write access is reported to the control device by an interrupt signal, while a write end status is prepared in the register and when the write is completed by the control device. The write end status is set, and the main process Makes it possible to determine which address of the I / O device has been accessed by clearing the write end status when writing to the register and detecting the write end status by the interrupt processing of the control device. It is characterized by that.

[0005]

In the I / O register access method of the present invention, data is exchanged between the main processor and the firmware by the 2-port register which can be accessed by both the main processor and the firmware.
No report is made to the firmware when a read access is made from the main processor to the 2-port register. On the other hand, at the time of write access from the main processor to the 2-port memory, the interrupt signal of 1 level is collected and reported to the firmware. At this time, the write end status is prepared in the 2-port register, and the write end status is set by the firmware at the end of the write. Then, when the main processor writes to the register, the write end status is cleared. As described above, by detecting the write end status in the interrupt processing of the firmware, it is possible to determine which address has been accessed.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the I / O register access system of the present invention. The illustrated I / O device 10 is connected to the main processor 20 via a system bus. The I / O device 10 includes a CPU 11, a 2-port register 12, an interrupt control circuit 13, and an address decoder 14. The CPU 11 executes the firmware. The 2-port register 12 can be accessed by both the main processor 20 and the CPU 11 that executes firmware.

The interrupt control circuit 13 outputs an interrupt signal to the CPU 11 in response to an interrupt request from the address decoder 14. The address decoder 14 decodes the address of access from the main processor 20 to the 2-port register 12, and outputs an interrupt request to the interrupt control circuit 13. Next, the operation of the above system will be described. First, when a register is read from the main processor 20, data is returned from the corresponding area of the 2-port register 12 corresponding to the address requested by the main processor 20, and no interrupt is generated. When writing to a register area of the I / O device 10 that does not require firmware processing, the 2-port register 1 corresponding to the requested address is written.
Write to area 2 and do not generate an interrupt.

When writing to the register of the I / O device 10 which requires firmware processing, write to the register of the 2-port register 12 corresponding to the requested address,
Further, the address decoder 14 reports an interrupt request to the interrupt control circuit 13. As a result, the interrupt control circuit 1
3 reports an interrupt to the CPU 11. FIG. 2 is a flowchart for explaining the interrupt processing of the firmware. The CPU 11 first reads which interrupt has occurred by judging the type of interrupt (step S1). Then, the register in the area corresponding to the interrupt of the 2-port register 12 is read (step S2), and the register for which the end status is not set is searched (step S).
3). Then, the processing of the designated function of the register is accepted (step S4), and the end status is set (step S5). At this time, the main processor 20
When it is necessary to confirm the end of processing, it can be confirmed by determining whether or not the end status is set.

FIG. 3 is a diagram showing an example of register allocation of an I / O device for performing DMA transfer. As shown, D
Writing to a register used as data such as MA address / transfer count / transfer mode does not generate a firmware interrupt. When writing to a register that requests firmware processing such as DMA activation / buffer clear / interrupt clear, interrupt levels are grouped for each function type and an interrupt to the firmware is generated. FIG. 4 is a diagram showing an example of a bit field of a register for generating an interrupt. In the illustrated example, the end flag is placed in the MSB. Then, the flag can be used to confirm the start-up of the firmware and the end of processing, and the type of processing can be specified by the control field.

In the above-described embodiment, the case of the DMA control device has been described, but the present invention is applicable to various I / O devices 10 such as an input / output device such as a magnetic disk device and an output device such as a printer. Applicable. That is, this is a case where the main processor 20 itself controls input / output by program control without using DMA.

[0011]

As described above, according to the I / O register access method of the present invention, a 2-port register having a write end status is prepared, and write access from the main processor is performed using the write end status. Since the read access is performed unconditionally, the access to the register of the I / O device can be completed within the access cycle time of the RAM with a small amount of hardware, and the main processor can be processed during the firmware processing. Can perform other processing in parallel.
Therefore, the processing performance of the system can be improved at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an I / O register access system according to the present invention.

FIG. 2 is a flowchart illustrating firmware interrupt processing.

FIG. 3 is a diagram showing an example of register allocation of an I / O device.

FIG. 4 is a diagram showing an example of a bit field of a register.

[Explanation of symbols]

 10 I / O device 11 CPU 12 2 port register 13 interrupt control circuit 14 address decoder 20 main processor

Claims (3)

[Claims] 1. When a main processor controls an I / O device by register access, a two-port register accessible by both the main processor and the control device of the I / O device is prepared, and the register is accessed. At the time of the read access, the data is read from the register without reporting to the control device, at the time of the write access to the register, the data is written to the register, and the write access is ended at the end of the writing. While the write access is reported to the control device by an interrupt signal, a write end status is prepared in the register, and the write end status is set by the control device at the end of writing, and the main processor sets the register in the register. When writing, end the writing It is possible to determine which address of the I / O device has been accessed by clearing the status and detecting the write end status in the interrupt process of the control device.
/ O register access method. 2. The access to a plurality of addresses for each address area of the register is collectively reported to the control device as one interrupt level, and the access level of the register is assigned to the access of the register. 2. The I / O register access method according to claim 1, wherein 3. The access to an address other than a specific address area of the register does not report to the control device, and the access to the specific address area reports to the control device by an interrupt signal. 3. The I / O register access method according to claim 1, wherein