JP3036590B2 - External device control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external agent connected to a processor, and more particularly to a method for efficiently accessing an external device in an information processing apparatus using an LSI as the external agent at the time of logic simulation and test pattern creation. And an external device control circuit.

[0002]

2. Description of the Related Art EP storing an initialization program and the like
The access time of an external device such as a ROM needs to be compensated for by an external agent, but the access time of the external device is 100 ns to 300 ns.
c, which is much longer than the period of the operation clock of the processor and the external agent,
When performing the logic simulation and the test pattern creation, the external device is accessed for 100 nsec to 300 nsec, and the logic simulation execution time, the verification time of the logic simulation result, and the number of test pattern patterns become enormous.

For this reason, Japanese Unexamined Utility Model Publication No. 1-169827 discloses that at least a counter circuit composed of a first counter and a second counter includes a carry signal indicating an overflow of the first counter and a counter enable signal of the second counter. A counter circuit having an OR circuit for inputting a carry signal and a test signal of the first counter of the second counter and outputting a signal as an enable signal; A technique for solving the problem is disclosed.

[0004]

However, in the case where the LSI is used for compensating the access time to an external device in the LSI as described above, the count value of the counter itself has no meaning, and Since only the carry signal of the upper bit has a meaning, the conventional counter circuit described above cannot functionally detect a failure even if the first counter has a failure. Therefore, the output of the OR circuit which inputs the carry signal and the test signal of the first counter becomes valid when the test signal becomes valid, and the enable signal of the second counter becomes valid regardless of the result of the carry signal of the first counter. It is.

SUMMARY OF THE INVENTION The present invention speeds up access to an external device during logic simulation and test pattern creation, shortens logic simulation execution time and verification time of logic simulation results, and reduces the number of patterns in test patterns. An object of the present invention is to enable detection of a failure of a counter.

[0006]

According to the present invention, in an information processing apparatus for performing timing compensation of an external device by an LSI connected to a processor, the information processing apparatus is cascaded to secure the timing of the access time of the external device. A plurality of counters, a test signal that is valid only at the time of logic simulation and test pattern creation, a processor interface control unit that controls a request from the processor, an access request to the external device from the processor, and A counter enable control unit for controlling an enable signal of the counter according to a state of a test signal; and an external device control unit for controlling a signal to the external device by a carry signal of the counter. Connection Which gave an enable signal to the subsequent counter evening to count Bok up simultaneously with the previous stage of the counter, the external device control and controls access to the external device at the subsequent stage of the counter carry signal A circuit is obtained.

Further, according to the present invention, in an information processing apparatus for compensating timing of an external device by an LSI connected to a processor, a plurality of cascade-connected information processing devices for ensuring timing of access time of the external device are provided. A counter, a test signal that is valid only at the time of logic simulation and test pattern creation, a processor interface control unit that controls a request from the processor, and an access request to the external device from the processor and a state of the test signal A counter enable control unit that controls an enable signal of the counter, and an external device control unit that controls a signal to the external device by a carry signal of the counter. test The counter enable control unit outputs an enable signal to all the cascade-connected counters, and the external device control unit outputs the carry signals of all the cascade-connected counters. An external device control circuit for detecting and notifying the external device of a signal to speed up logic simulation and reducing the number of test patterns without impairing the failure detection rate of the counter. Can be

[0008]

[Action] When it is recognized from the test signal that the logic simulation and the test pattern are being created, the counter
The enable control unit outputs an enable signal to each counter, each counter counts up, and the external device control unit notifies the external device of the end of the access when the carry signal of each counter is input. For this reason, at the time of logic simulation and test pattern creation, the counter operates at a high speed, so that the time required for accessing an external device can be reduced, and the failure of each counter can be detected.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an external device control circuit according to an embodiment of the present invention. FIGS. 2, 3, 4 and 5 show operations of the external device control circuit according to an embodiment of the present invention. FIG.

FIG. 1 shows a processor 100 and an external agent 101. External agent 1
01, the processor interface controller 10
6 receives the processor interface signal 107 output from the processor 100 and
If it is determined that the data is to be read from the external device 119, a processor read instruction signal 117 is output.

The counter enable control unit 105 includes a test signal 108, a processor read instruction signal 117, a processor write instruction signal 118, which is valid only at the time of logic simulation and test pattern creation.
The carry signal 111 is input, and the access time securing counter 103 and the access time securing counter 104 are input.
A counter enable signal (hereinafter, referred to as an enable signal 109) 109 and a counter enable signal (hereinafter, referred to as an enable signal 110) 110 are output.

The access time securing counter 103 counts up by an enable signal 109 from the counter enable control unit 105, and outputs a carry signal 111 when overflow occurs. The access time securing counter 104 counts up by an enable signal 110 from the counter enable control unit 105, and outputs a carry signal 112 when overflow occurs.

The external device control unit 102 includes a processor read instruction signal 117, a processor write instruction signal 118, a carry signal 111, and a carry signal 11.
2 is input, and the processor read instruction signal 117 is input.
Indicates that the reading is being performed, the external device 119 outputs the external device read instruction signal 113 and the address 115 to the external device 119 to output the external device 1.
19, the data 116 is received from the external device 119, and the processor write instruction signal 118
Indicates that writing is being performed, an external device write instruction signal 114, an address 115, and data 116 are output to the external device 119 to notify the external device 119 of writing to the external device 119. The data 116 is written to 119.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. 1, 2, 3, 4 and 5. FIG. 2 shows the state of FIG.
4 is a timing chart showing the operation of each unit when the test signal is in a valid state. FIG. 3 is a timing chart showing the operation of each unit in FIG. 1 when executing an external device read, when the test signal is in an invalid state. FIG. 4 is a timing chart showing an operation of each unit in FIG. 1 when an external device write is executed, when a test signal is in a valid state. FIG. 5 is a timing chart showing the operation of each unit in FIG. 1 when executing an external device write, when the test signal is in an invalid state.

An external device read when the external agent 101 is notified by the test signal 108 at the time of logic simulation and at the time of test pattern creation will be described below. When it is notified by the test signal that the logic simulation is being performed and the test pattern is being created (A in FIG. 2), and the processor read instruction signal 117 is asserted (B in FIG. 2), the external device control unit 102 Asserts the external device read instruction signal 113 and the address 115 (C and D in FIG. 2), and the counter enable control unit 105 enables the enable signal 109 of the access time reservation counter 103 and the enable signal 109 of the access time reservation counter 104. Enable signal 1
10 is asserted (E, F in FIG. 2). With the enable signal 109 and the enable signal 110, the access time reservation counter 103 and the access time reservation counter 104 count up simultaneously (G in FIG. 2,
H).

Thereafter, the access time securing counter 10
3 overflows, and carry signal 112 instructing access time securing counter 104 when overflow occurs.
Are simultaneously asserted (I and J in FIG. 2). The external device control unit 102 receives the carry signal 111 and the carry signal 112, sets the data 116 output from the external device 119 by the logical product of the carry signal 111 and the carry signal 112 (K in FIG. 2), The device read instruction signal 113 and the address 115 are negated.

Next, when the external agent 101 is notified by the test 108 signal that it is not during the logic simulation or the test pattern creation,
The lead will be described. When it is notified by the test signal 108 that it is not the time of the logic simulation or the test pattern creation (A in FIG. 3) and the processor read instruction signal 117 is asserted (B in FIG. 3), the external device control unit 102 , The external device read instruction signal 113 and the address 115 are asserted (C and D in FIG. 3), and the counter enable control unit 105 asserts the enable signal 109 of the access time reservation counter 103 (E in FIG. 3). ). The access time securing counter 103 counts up by the enable signal 109 (G in FIG. 3).

Thereafter, the access time securing counter 10
When 3 overflows, carry signal 111 is simultaneously asserted (I in FIG. 3). When the carry signal 111 is input to the counter enable control unit 105, an enable signal 110 is output (F in FIG. 3), and the access signal securing counter 104 is counted up by the enable signal 110 (H in FIG. 3). Thereafter, when the access time reservation counter 104 overflows, the carry signal 112 is asserted (J in FIG. 3). In the external device control unit 102, the carry signal 111 and the carry signal 112 are input, and the data 116 output from the external device 117 is set by the logical product of the carry signal 111 and the carry signal 112 (K in FIG. 3). The external device read instruction signal 113 and the address 115 are negated.

Next, when the external agent 101 is notified by the test signal 108 that it is at the time of logic simulation and at the time of test pattern creation,
The light will be described. When the logic simulation and the creation of the test pattern are notified by the test signal 108 (A in FIG. 4) and the processor write instruction signal 118 is asserted (B in FIG. 4), the external device control unit 102 Asserts an external device write instruction signal 114, an address 115, and data 116 (C, D, and K in FIG. 4). Access time securing counter 104
4 is asserted (see FIG. 4).
E, F). In response to the enable signal 109 and the enable 1 signal 110, the access time reservation counter 103 and the access time reservation counter 104 simultaneously count up (G and H in FIG. 4).

Thereafter, the access time securing counter 10
3 overflows, and carry signal 112 instructing access time securing counter 104 when overflow occurs.
Are simultaneously asserted (I and J in FIG. 4). The external device control unit 102 receives the carry signal 111 and the carry signal 112, and negates the external device write instruction signal 114, the address 115, and the data 116 by the logical product of the carry signal 111 and the carry signal 112.

Next, when the external agent 101 is notified by the test signal 108 that it is not at the time of logic simulation or at the time of test pattern creation,
The light will be described. When it is notified by the test signal that the logic simulation is not being performed and the test pattern is not being created (A in FIG. 5), and the processor write instruction signal 118 is asserted (B in FIG. 5), the external device control unit 102 , The external device write instruction signal 114, the address 115, and the data 116 are asserted (C, D, and K in FIG. 5), and the counter enable control unit 105 asserts the enable signal 109 of the access time securing counter 103. (E in FIG. 5). In response to the enable signal 109, the access time securing counter 1
03 counts up (G in FIG. 5). Thereafter, when the access time counter 103 overflows, the carry signal 111 is asserted (I in FIG. 5).

When carry signal 111 is input to counter / enable control section 105, enable signal 110 is output (F in FIG. 5), and access time securing counter 104 is counted up by enable signal 110 (H in FIG. 5). ). Then, access time securing counter 1
When 04 overflows, carry signal 112 is asserted (J in FIG. 5). The external device control unit 102 receives the carry signal 111 and the carry signal 112, and negates the external device write instruction signal 114, the address 115, and the data 116 by the logical product of the carry signal 111 and the carry signal 112. .

[0023]

According to the present invention, by cascading counters inside an external agent for securing access time of an external device, it is possible to add a signal which is valid only when a logic simulation mode and a test pattern are created. In the logic simulation mode and test pattern creation, an enable signal is given to each cascade-connected counter, and access to an external device is terminated based on the result of a signal obtained by ANDing the carry signals of the counters. In addition, access to an external device at the time of test pattern creation can be speeded up. As a result, it is possible to reduce the number of test patterns without reducing the execution time of the logic simulation and the verification time of the result of the logic simulation, and without impairing the failure detection rate of the counter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an external device control circuit of the present invention.

FIG. 2 is a timing chart showing the operation of each unit in FIG. 1 when executing an external device read.

FIG. 3 is a timing chart showing an operation of each unit in FIG. 1 when executing an external device read.

FIG. 4 is a timing chart showing the operation of each unit in FIG. 1 when executing an external device write.

FIG. 5 is a timing chart showing the operation of each unit in FIG. 1 when executing an external device write.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 processor 101 external agent 102 external device control unit 103 access time reservation counter 104 access time reservation counter 105 counter enable control unit 106 processor interface control unit 107 processor interface signal 108 test signal 109 enable signal 110 enable signal 111 carry signal 112 Carry signal 113 external device read instruction signal 114 external device write instruction signal 115 address 116 data 117 processor read instruction signal 118 processor write instruction signal 119 external device

Claims (2)

(57) [Claims] 1. An information processing apparatus for performing timing compensation of an external device by an LSI connected to a processor, comprising: a plurality of counters connected in cascade to ensure timing of access time of the external device; A test signal that is valid only when a test pattern is generated, a processor interface control unit that controls a request from the processor, and an enable signal for the counter based on an access request to the external device from the processor and a state of the test signal. A counter enable control unit that controls the external device control unit that controls a signal to the external device by a carry signal of the counter,
At the time of logic simulation, an enable signal is provided so that the cascade-connected counter at the subsequent stage counts up at the same time as the counter at the previous stage, and access to the external device is controlled by the carry signal of the counter at the subsequent stage. An external device control circuit, comprising: 2. An information processing apparatus for performing timing compensation of an external device by an LSI connected to a processor, comprising: a plurality of counters connected in cascade to ensure timing of access time of the external device; A test signal that is valid only when a test pattern is generated, a processor interface control unit that controls a request from the processor, and an enable signal for the counter based on an access request to the external device from the processor and a state of the test signal. A counter enable control unit that controls the external device control unit that controls a signal to the external device by a carry signal of the counter,
When instructed by the test signal to be at the time of logic simulation and at the time of test pattern creation, the counter enable control unit outputs an enable signal to all cascaded counters, and the external device control unit Detecting carry signals of all connected counters and notifying the external device of the signals to speed up logic simulation and reduce the number of test patterns without impairing the failure detection rate of the counters. Characteristic external device control circuit.