JPS581451B2 - Data transfer method - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a data transfer system, specifically, connecting each board such as a central processing unit, memory, input/output control unit, etc. to a common bus,
The present invention relates to a data processing system configured to allow each board to have a different data transfer width.

Generally, in an integrated data processing system, a central processing unit board (chip) is connected to the data bus line.
It is constructed by connecting one or more input/output control device boards (hereinafter referred to as IOC chips) to a center (hereinafter referred to as a CPU chip).

Input/output devices are not connected to the IOC chip, and particularly those to which high-speed input/output devices are connected have a function (DMA: Direct Hemo-ry Access) to directly access memory or other IOCs without going through the CPU.
Some have s).

Input/output control in a data processing system refers to data transfer control between the CPU or main memory (memory) and input/output devices, and is performed while executing input/output commands under program control. There are DMAs that transfer data between main memories and DMAs that directly transfer data between input/output devices and main memories regardless of program control.

The former runs a program every time one word is transferred, so the data transfer speed is slower than that of DMA, so it is connected for low-speed input/output devices, while DMA is used for high-speed input/output devices.

In recent years, DMA has been required to transfer data at increasingly high speeds.

One effective method for increasing the speed of DMA data transfer is to increase the amount of information transferred to and from memory at one time (data transfer width of the bus).

However, this method cannot connect conventional input/output devices with a narrow data transfer width to a computer equipped with a new high-speed DMA bus, so if you are trying to improve the processing speed of an existing computer system, for example, all The drawback was that the input/output devices had to be all new to connect to the new bus.

The present invention has been made in view of the above-mentioned drawbacks, and the data transfer width can be changed in units of 32 bits by switching the data transfer width (for example, 1 6/3 2 bits) in response to an instruction from a device that is allowed to occupy the bus via the control line. Enables high-speed transfer with
and DMA with different data transfer widths (16 bits)
The purpose is to provide a data transfer method that allows connection with devices.

Hereinafter, the present invention will be explained in detail using the drawings.

Figure 1 shows a board connection diagram around the DMA bus line. As an example, when a system based on a 16-bit data line is expanded to a 32-bit data line, the conventional DMA channel can be used as an expansion model. It is designed to be insertable.

In the figure, 1 is a 1 6/3 2-bit data line,
2 is a memory board MM that stores programs or data;
U1 3 is a CPU board that processes data according to instructions from a program in the memory board MMU; 4 is a memory control board that controls the memory 2 in conjunction with the CPU board 3; 5, 6, and 7 are DMA channels. This is a high-speed input/output control board IOC.

Further, the IOCs 5 and 6.7 having DMA channels are both 16-bit and 32-bit, and a mode control line 8 is provided to distinguish between the two.

When the 32-bit DMA channel reads/writes the memory 2, the mode control line 8 is set to "0" level.

Since the 16-bit DMA channel does not have this mode control line, there is no change in the control line when the 16-bit DMA channel reads/writes the memory 2.

This control line has a wired OR configuration using a so-called pull-up resistor, and is normally set to "1".

For this reason, the information processing device to which the present invention is applied has a 16-bit DM.
When connecting the A channel, the bus according to the invention operates in 16-bit mode without requiring any changes to the 16-bit DMA channel.

When accessing the memory in this way, if the mode control line is "1", reading/writing is performed as 16-bit data, and if it is "0", the data bus line is distinguished as 32-bit data.

Note that the memory address/control line 9 is similar to a conventional bus line, so a description thereof will be omitted.

FIG. 2 is a detailed description of the periphery of the memory board 2 (memory board) in FIG.
・22, 23), read data line 13 (gate 31
・32, 33) and a memory 14 consisting of 32 bits per word, said memory 14 having a memory address assigned to each half word (16 bits each).

When operating in 16-bit mode, bits 0-15 of data bus line 11 are used.

In other words, the data bus line 11 is designed such that bits 16 to 31 of the data bus line 11 are newly added to the conventional 16-bit mode bus.

(This is also taken into account when designing the mounting surface, such as the allocation of back panel pins, etc.) Furthermore, the gates 21 and 2
The enable conditions for 2, 23, 31, 32, and 33 are as follows.

21 Bits 0 to 15...Mode control line/even address or mode control line 22 Bits 16 to 31...Mode leg line 23
Bits 0 to 15...Mode control line/Odd number address 31 Bits 0 to 15...Mode control line/Even numbered address or mode control line 32 Bits 16 to 31...Mode leg line/Odd number address 33 Bit 1 6=3 1...Mode control line Therefore, in the 32-bit mode (mode control line is "0"), use the data line of bits 0 to 31, open gates 21 and 22 to write, and write to gate 31, 33 and read odd and even addresses at the same time.

Furthermore, in the 16-bit mode (mode control line is "1"), only the data lines for bits 0 to 15 are used, so it is necessary to switch the memory bus lines when reading/writing odd addresses.

This is done by address bit “14” and “0”
When it is "1", it is an even number, and when it is "1", it is an odd number.

That is, data buses are switched by address bit "14".

In the 16-bit mode, writing to memory is performed only on 16 bits, not 32 bits.

The DMA operation will be described here, but since it is not directly related to the present invention, it will be briefly described.

In the case of DMA, unlike in the case of program control, it consists of an IO channel, and this channel includes an address register, a data counter, a data transfer end detection circuit, and a DMA
Consists of a control circuit.

The contents of the address register are placed on the address bus of the input/output interface, and the main memory address is specified during data transfer.

Furthermore, compared to the case of program control, the input/output control device has an additional transfer request flip-flop.

The DMA transfer procedure consists of three phases: initial processing, data transfer processing, and termination processing.

Initial processing uses a channel word setting command of an input/output instruction to set the start address of the main memory for data transfer in the address register and the number of transfer words in the data counter.

After that, execute the input/output control command and set the control register.

The DMA is processed up to this point by a program, and thereafter, all data transfer processing is performed by hardware until the transfer of a predetermined number of data words is completed.

That is, when data is fetched from an input/output device, when data is set in the data register, a transfer request flip-flop is turned on, a DMA transfer request signal is sent to the CPU, and the data is fetched into the main memory.

At this time, the address of the main memory is the address signal of the address bus, which is output from the address register.

At this time, the address of the main memory is the address signal of the address bus, which is output from the address register.

Each time a half word or one word of data is transferred to and from the main memory, the contents of the address register are incremented by 1 and the contents of the data counter are incremented by -1.

(In 32-bit mode, instead of +1, -1, +2,
-2) When the above operations are repeated, the content of the data counter finally becomes "0", and at this time, the end detection circuit operates and sends out an end signal to the input/output control device.

The input/output device sets the termination interrupt flipflop,
A termination interrupt request signal is sent to the CPU to perform termination processing.

When writing data to the input/output device, a DMA transfer request signal is sent every time a half word or one word is written, and similar processing is performed.

As explained above, according to the present invention, in order to improve the processing speed of an existing computer system, only devices with particularly high data transfer rates, such as CPU memory and disks, are replaced with new devices, and all other input/output devices are replaced with existing ones. This makes it possible to improve system performance at low cost.

In other words, 16/32-bit mode switching is performed every bus occupancy period according to instructions from the device that is allowed to occupy the bus via the mode control line, so it is possible to switch between devices that use 16-bit mode and devices that use 32-bit mode. It becomes possible to connect to a DMA bus, increasing transfer efficiency using the bus.

[Brief explanation of the drawing]

FIG. 1 shows a board connection diagram around the DMA bus line, and FIG. 2 shows an embodiment in which the periphery of the memory board in FIG. 1 is detailed. 1, 11...1 6/3 2-bit data bus line, 2...Memory board, 3...
CPU board, 4... Memory controller board, 5, 6, 7... DMA controller board, 8... Mode control line, 12...
Write bus line, 13... Read bus line, 14... Memory.

Claims (1)

[Claims] 1 Devices that perform data input/output with either one word length or half word length data width are commonly connected to the memory, and one word length and half word length data transfer can be performed using a common bus. In an information processing system that performs input/output of one word length, only the transfer data width specification line from the device that performs input/output of one word length is output coupled, and in a steady state, the mode control line is set to a state that instructs data transfer of half word length width. A data transfer method, characterized in that the connection relationship between the common bus and the memory is controlled according to the state of the mode control line.