JPS62217483A - Memory device - Google Patents

Abstract

PURPOSE:To input and output and also process data in bit units at high speed by specifying an address with a signal for word-by-word specification and specifying a bit position in data in word units with an address signal consisting of a specific number of bits. CONSTITUTION:When an address multiplexer 101 switches outputs according to whether input address signals are in bit mode or word mode and then attain bit-by-bit access, word positions in an image memory 103 are selected with address signals Ai-AN+i-1 which are shifted by (i) bits and bit positions in data in word units are selected with (i)-bit address signals A0-Ai. When data are written in word units, a write signal is sent for all bits through the AND and OR gates 202 and 203 of a transfer control circuit 104 and when data are written in bit units, a signal is sent to only selected bits in data in word units, a demultiplexer 105 controls data input to a memory 103, and a multiplexer 106 selects bits outputted from the memory 103.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device that performs image processing.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional image memory device.

In FIG. 3, 3o1 is an address register, 302 is a data register, 3o3 is an image memory, 304 is an address l/jimeta, 305 is a data register, A0 to A N
-1 is an address signal that specifies addressing in word units;
D OD-D is data. Next, the operation will be explained.

An address signal A is output from a CPU (not shown) through an address register 301. -AN+.

Image memo! It is input to the address input of J303.

Further, input/output operations of the image memory 303 are executed via the data register 302 by the WRITE signal and the REΔD signal input to the image memory 303 . The above explanation is the operation of a normal computer memory itself.

Image memory devices generally have a dedicated CPU or controller for image processing in addition to the CPU, and address signals from these are sent to the address register 3.
04, input/output operations are sent to the image memory 303 via the data register 305, and operations are executed in parallel with the main CPU.

[Problem that the invention seeks to solve]

In conventional image memory devices such as those mentioned above, access from the CPU is performed only in word units (or byte units), so the problem is that it takes a long time to operate the image memory in units of pins. There was a point.

The present invention was made to solve these problems, and an object of the present invention is to provide a memory device capable of inputting/outputting data in bits from a CPU and executing the processing at high speed.

[Failure to solve the problem]

The memory device according to the invention of Party B is a memory device that writes and reads data in word units by specifying addresses in units of words, and inputs an address signal specifying addresses in units of words, and changes the input bit mode/word mode. An address multiplexer that outputs an address signal to the memory to specify an address in word units in response to a selection signal, an address signal of a predetermined number of bits that specifies the pit position in data in word units, and a bit mode/word. A transfer control circuit to which a mode selection signal and a write/read selection signal are input;
A demultiplexer controls the data input to the pit position in the memory corresponding to the pit position in the word unit data when writing the mode, and controls which bit in the memory is output when reading the bit mode. and a multiplexer for selection.

[Effect]

In this invention, when bit mode is selected, addressing is performed in word units using an address signal that specifies addressing in word units, and a pit position within data in word units is specified by an address signal having a predetermined number of bits.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a memory device of the present invention. In FIG. 1, 101 is an address multiplexer whose output is switched depending on whether the input address signal is a bit mode address signal or a word mode address signal. Reference numeral 102 denotes a data register, which is used during conventional word mode execution. A transfer control circuit 104 executes transfer control to the image memory 103. 105 is a demultiplexer, and an image memo corresponding to the pit position in the word unit data! Data input to the pit position in 1103 is controlled. A multiplexer 106 selects which bit in the image memory 103 is to be output.

Further, 107 is an address register of a CPU or controller dedicated to image processing, 108 is a data register dedicated to image processing, and 109 is a transfer control circuit dedicated to image processing, which operate in parallel with the main CPU in a time-sharing manner.

Next, the operation will be explained.

When accessing bit by bit, address signal A0
~A p4-4 is 1 bit (bit length in word = 2'
) The word position of the image memory 103 is selected by the shifted address signals A1 to AN+1-1, and furthermore, the address signal A of 1 bit]. -A1 selects a pit position within word unit data.

FIG. 2 is a diagram showing the configuration of the transfer control circuit 104. In Figure 2, the same symbols as in Figure 1 indicate the same parts, and 2
01 is a decoder, 202 is an ant game-1-1203 is an OR gate.

When writing a word, a write signal is sent to all bits in the word through the ant game 1/202 and the orday 1/203, and when writing a bit, the decoder 201 determines the pit position in the word unit data. A write signal is sent to only the selected pin 1-203 through the ORD 1-203.

When configured with bit mode addresses, data pit positions in the CPU use specific bit positions (for example, bits 1-0), but address registers 1o7. By adding a switch circuit to select one of the data D0 to D as the signal connected to the data register 108, assignment to any pit position becomes possible. Note that the correspondence between the claims and the names in the examples is shown below.

Further, although the configuration of the image memory device is shown in FIG. 1, it goes without saying that the present invention is not limited to this.

〔Effect of the invention〕

As described above, the present invention provides a memory device that writes and reads data in units of words by specifying addresses in units of words. An address multiplexer that outputs an address signal to the memory that specifies addressing in word units in response to a signal, an address signal with a predetermined number of bits that specifies the pit position in data in word units, and bit mode/word mode selection. a transfer control circuit to which the signal and write/read selection signal are input, and a device that controls data input to a pit position in the memory corresponding to a pit position in word unit data during bit mode writing. Equipped with a multiplexer and a multiplexer that selects which bit in the memory is output when reading the bit mode, it is possible to input/output data (lQ) in units of pins and execute its processing at high speed. Moreover, it becomes possible to reduce the load on the CPU or controller, which has the effect of increasing the cost performance of the entire system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the memory device of the present invention, FIG. 2 is a diagram showing the configuration of a transfer control circuit, and FIG. 3 is a diagram showing an example of a conventional image memory device. In the figure, 101 is an address multiplexer, 102
．． 108 is a data register, 103 is an image memory, 10
4, 109 is a transfer control circuit, 105 is a demultiplexer, 106 is a multiplexer, and 1107 is an address register. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) (O) Figure 1 106° multiplexer

Claims (1)

[Claims] In a memory device that writes and reads data in word units by addressing in word units,
an address multiplexer which inputs the address signal for specifying the address in word units and outputs the address signal for specifying the address in the word unit to the memory in response to the input bit mode/word mode selection signal; A transfer control circuit receives an address signal of a predetermined number of bits for specifying a bit position in data, the bit mode/word mode selection signal, and a write/read selection signal; a demultiplexer for controlling data input to a bit position in the memory corresponding to a bit position in the data of a unit; and a multiplexer for selecting which bit in the memory to output when reading a bit mode. A memory device comprising: