JPH05197612A - Data access circuit - Google Patents

Abstract

PURPOSE:To efficiently perform access to data where data length exceeds the width of a data bus, and to shorten access time by executing control by inputting an access control signal outputted from a CPU to an address generating/ switching circuit and a storage device. CONSTITUTION:When an access control signal 7 is made active, first of all, the address signal of access start is outputted to an address bus 2 by a CPU 1 and inputted to an address generating/switching circuit 6. At the address generating/switching circuit 6, the access start address signal is set to a counter 8, set data are inputted to a multiplexer 9 as a counter output as they are, and the multiplexer 9 inputs the output of the counter 8 to an address decoder 5 as address information according to the access control signal 7. The prescribed stored data area of a storage device 4 is designated by the output of the address decoder 5, and the read/write of data is executed to a data bus 3 and the address bus 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access circuit, and more particularly to a data access circuit using a bus such as a microcomputer.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a microcomputer as an example of a conventional data access circuit.

In FIG. 5, a CPU (Central)
The processing unit 1 accesses the storage device 4 via the address bus 2 and the data bus 3. The address bus 2 transfers address information when the CPU 1 accesses the storage device 4. The data bus 3 is
Data information is transferred when the CPU 1 accesses the storage device 4.

The address decoder 5 inputs the address information from the address bus 2 and designates the address of the storage device 4. Both the address bus 2 and the data bus 3 are 32 bits wide.

Next, the operation will be described. When the storage device 4 is accessed, the CPU 1 causes the address bus 21
Address data is output to. The address decoder 5 fetches the address data from the address bus 2 at a predetermined timing, and the decode output selects a predetermined storage data area of the storage device 4 to read / write data from the data bus 3. Read / write to the data bus 3 is also performed at a predetermined timing, data is written to a register of the CPU 1 or a predetermined storage data area of the storage device 4, one data access ends, and the same at the next access. Success is achieved by repeating these steps.

[0006]

In the data access circuit shown in this conventional example, the access destination is always specified by the address bus, and the data read / write is performed on the data bus there. For example, the data has a data length of 32.
When accessing data with a bit length of more than 1 bit (double precision floating point = 64 bits, etc.), despite the fact that the access area of the data is indicated by consecutive addresses,
Since it is necessary to perform addressing every time the CPU 1 accesses, and only 32-bit data can be accessed at one time, a read / write cycle is required when accessing 64-bit data such as double-precision floating point data. There was a drawback that it took two times and it took time.

Therefore, an object of the present invention is to solve the above-mentioned drawbacks and to provide a data address circuit capable of efficiently executing the access of data whose data length exceeds the data bus width and shortening the access time. It is in.

[0008]

A data access circuit according to the present invention has an address bus, a data bus, at least one storage device, and an address for generating an address signal of an arbitrary continuous data area. In a data access circuit including a forming circuit, a signal designating an arbitrary data area of the storage device and a signal output from the address generation circuit are switched via the address bus when accessing the storage device. Switching means and access means for reading / writing data to / from the address bus when accessing the memory device by the address signal of the address generating circuit are provided.

[0009]

The present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of a data access circuit according to an embodiment of the present invention.

In FIG. 1, in this embodiment, the CPU 1
Accesses the storage device 4 via the address bus 2 and the data bus 3. Both the address bus 2 and the data bus 3 have a bus width of 32 bits. Address bus 2 is CP
When U1 accesses the storage device 4, it normally transfers address information. The data bus 3 transfers data information when the CPU 1 accesses the storage device 4.

The address decoder 5 inputs the address information from the address bus 2 via the address generation / switching circuit 6 to specify the address of the storage device 4. CP
U1 outputs an access control signal 7 to generate an address /
The operation of the switching circuit 6 and the storage device 4 is controlled.

FIG. 2 shows the address generation / switching circuit 6 of FIG.
It is a block diagram of. In FIG. 2, the address signal 2 ′ from the address bus 2 is input to the counter 8 and the multiplexer 9, and the multiplexer 9 outputs the counter 8 and the address bus signal 2 ′ from the address bus 2.
2) is selected by the access control signal 7 and output. The counter 8 counts up with the synchronization signal φ.

Next, the operation will be described. First, when the access control signal 7 is inactive, the storage device 4
In order to access, the CPU 1 outputs address data to the address bus 2. The address generation / switching circuit 6 is
Address data is fetched from the address bus 2 at a predetermined timing, the address data is directly input to the address decoder 5, and the output of the address decoder 5 causes
A predetermined storage data area of the storage device 4 is designated to read / write data from the data bus 3.

Next, when the access control signal 7 becomes active, the CPU 1 first outputs an access start address signal to the address bus 2 and the address generation / switching circuit 6 is started.
Entered in. In the address generation / switching circuit 6, the access start address signal is set in the counter 8 and the set data is directly input to the multiplexer 9 as the counter output. The multiplexer 9 receives the output of the counter 8 as the address information by the access control signal 7. Input to the address decoder 5. A predetermined storage data area of the storage device 4 is designated by the output of the address decoder 5, and data read / write is performed with respect to the data bus 3 and the address bus 2.

While the access control signal 7 is active, the address generation / switching circuit 6 outputs an address signal which sequentially increases at a constant rate, so that the CPU 1 accesses an arbitrary data length (for example, a 64-bit length). By setting the control signal 7 to be active, the data can be accessed from the address bus 2 and the data bus 3 without outputting the address signal.

When the control signal 7 becomes inactive again, the CPU 1 outputs the address information to the address bus 2 and the data access from the data bus 3 to the storage device 4 is performed.

FIG. 3 is a block diagram of a data access circuit according to another embodiment of the present invention. In FIG. 3, in this embodiment, the CPU 1 accesses the storage device 4 via the address bus 2 and the data bus 3. Both the address bus 2 and the data bus 3 have a bus width of 32 bits. The address bus 2 normally transfers address information when the CPU 1 accesses the storage device 4. Data bus 3 is CPU1
Transfers data information when the storage device 4 accesses the storage device 4. The address decoder 5 receives the address information from the address bus 2, and its output specifies the address of the memory device 4 via the decode address generation / switching circuit 6 '. The CPU 1 outputs the access control signal 7 and controls the operation of the decode address generation / switching circuit 6 ′ and the storage device 4.

FIG. 4 is a block diagram of the decode address generation / switching circuit 6'of FIG. In FIG. 4, the decode signal from the address decoder 5 is input to the counter 8'and the multiplexer 9 ', and the multiplexer 9'determines the output of the counter 8'and the decode signal from the address decode 5 as the access control signal 7'. , Either one of them is selected and output. The counter 8'counts up with the synchronizing signal φ.

Next, the operation will be described. First, when the access control signal 7 is inactive, the storage device 4 is
In order to access, the CPU 1 inputs address information to the address decoder 5 via the address bus 2, and the decode signal from the address decoder 5 is output to the decode address generation / switching circuit 6 '. In the decode address generation / switching circuit 6 ', the output decode signal of the address decode 5 is selected by the multiplexer 9', a predetermined storage area of the storage device 4 is selected, and data is read / written from the data bus 3 '. ..

Next, when the access control signal 7 becomes active, the CPU 1 first outputs the access start address signal to the address bus 2 and is decoded by the address decode 5, and the decoded output is the decoded address generation / switching circuit 6 '. Entered in. In the decode address generation / switching circuit 6 ', the address decode 5 is added to the counter 8'.
The decoded output of is set, and the set data is directly input to the multiplexer 9'as a counter output. The multiplexer 9'selects the output of the counter 8'in response to the access control signal 7, a predetermined storage data area of the storage device 4 is designated, and data read / write is performed on the address bus 2 and the data bus 3. Be seen.

Since the decode address generation / switching circuit 6'outputs the address decode signal which sequentially increases at a constant rate during the period when the access control signal 7 is active,
As in the case of the first embodiment, the CPU 1 can access the data from the data bus 2 and the address bus 3 without outputting the address signal by setting the control signal to be active during the access to the arbitrary data length.

In this embodiment, the address generation / switching is performed by the output after decoding, and the bit width of the signal after decoding is smaller than that of the address signal normally output by the CPU 1. Than one embodiment shown in 1.
There is an advantage that the circuit can be made smaller.

[0023]

As described above, the data of the present invention
Since the access circuit can use both the address bus and the data bus bus for reading / writing data, when accessing data whose data length exceeds the normal data bus width, for example, the data bus and the address bus 32
With the bit width, it is possible to access twice as much data by one access, and it is possible to shorten the access time without expanding the data bus width.

In the above embodiment, the data access by the microcomputer is explained as an example.
Controllers other than CPU, such as DMAC (Direct
tMemcry Access Control
It is also applicable to the data access of the device which itself outputs the address signal for r).

[Brief description of drawings]

FIG. 1 is a block diagram of a data access circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an address generation / switching circuit shown in FIG.

FIG. 3 is a block diagram of another embodiment of the present invention.

4 is a block diagram of a decode address generation / switching circuit shown in FIG.

FIG. 5 is a block diagram of a conventional data access circuit.

[Explanation of symbols]

 1 CPU 2 Address Bus 3 Data Bus 4 Storage Device 5 Address Decoder 6, 6'Address Generation / Switching Circuit 7 Access Control Signal 8, 8'Counter 9, 9 'Multiplexer φ Synchronous Signal

Claims (2)

[Claims] 1. A data access circuit comprising an address bus, a data bus, at least one or more storage devices, and an address generation circuit for generating an address signal of an arbitrary continuous data area, wherein the storage device is a storage device. Access means for switching between a signal designating an arbitrary data area of the storage device and a signal output from the previous address generation circuit via the address bus, and the storage device by the signal of the address generation circuit. A data access circuit, comprising: access means for reading / writing data to / from the address bus when accessing. 2. The data access circuit according to claim 1, wherein the address generation circuit is interposed between the address decoder and the storage circuit.