JPH0528751A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain a memory access interruption in a page mode cycle by providing a control signal control means, and invalidating one part of control signal outputted by a control signal outputting means. CONSTITUTION:A control signal outputting means 50 to which a clock signal CLK, and a signal CS indicating the start of a cycle are inputted, outputs an RW signal, XAL signal, RA signal, SE signal, YAL signal, RE signal, DE signal, OE signal, DL signal, and WE signal being control signals for controlling the cycle of the memory access in a page access mode. The RE signal, ED signal, OE signal, DL signal, and WE signal being one part of the control signals are controlled by a control signal control means 60 according to an outside noop control signal NOOP, so that the level can be invalidated to the memory access. As the result, the memory access can be interrupted in the page mode cycle, and the page access can be discontinuously operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a page access mode, and more particularly to a semiconductor memory device capable of controlling execution and non-execution of page access.

[0002]

2. Description of the Related Art MPUs and control ASICs on a system board in a recent computer system operate using a continuous external basic clock as a system clock. Therefore, some semiconductor memory devices (hereinafter referred to as "memory") used on the system board operate with a continuous external basic clock as the system clock. Such a semiconductor memory device has an external basic clock and a cycle. The cycle of memory access is controlled by the signal indicating the start of.

A conventional semiconductor memory device will be described below. FIG. 3 is a block diagram showing the configuration of a conventional semiconductor memory device, and FIG. 4 is a timing diagram for explaining the operation of the conventional semiconductor memory device in the page access mode. Note that FIG. 4 shows the operation in the write mode. In FIG. 3, 1 is a sense amplifier (SA), 2 is a transfer gate, 3 is a memory cell, 4 is a bit line,
5 is a column select gate, 6 is an IO bus, 7 is a column select gate enable signal line, 8 is a word line, and 9
Is a row address buffer, 10 is a column address buffer, 11 is a row decoder, 12 is a sense amplifier group, 13
Is a column decoder, 14 is a data amplifier, 15 is a data output buffer, 16 is a write amplifier, 17 is a data input buffer, 18 is a sequencer, 19 is a row sequencer, and 20 is a column sequencer.

In FIGS. 3 and 4, CLK is an external basic clock for memory access, CS is an external chip select signal, R / W is an external read / write control signal,
ADD (ADDRESS) is an external address, DATA is external data, / RAS is an internal row address strobe signal, / CAS is an internal column address strobe signal, R
W is an internal read / write control signal, XAL is a row address latch signal, RA is a row decoder activation signal, WLi
Is a word line (i-th), SE is a sense enable signal,
YAL is a column address latch signal, RE is a column decoder activation signal, YSWj is a column select gate enable signal (jth), DE is a data amplifier enable signal, DL is a data latch signal, and WE is a write amplifier enable signal.

In FIG. 4, R is an external row address, C1, C2 and C3 are external column addresses, and D is an external column address.
1, D2 and D3 indicate external data. Regarding the access timing of the conventional semiconductor memory device configured as above, in the normal read / write cycle (not in the page access mode), four basic clocks (first clock to fourth clock) become one cycle, The page mode cycle can be executed by repeating the second and third clocks a plurality of times. (In FIG. 4, three page mode cycles are performed.) Read / write control is performed by the external read / write control signal R / W.
If the R / W signal is high level, it becomes a read cycle, and if it is low level, it becomes a write cycle.

As the address, ADDRESS is given by multiplexing a row address at the first clock and a column address at the second clock. The data is DATA, and the input data is given at the second clock. Next, the internal operation of the conventional semiconductor memory device in the page access mode will be described.

First, the sequencer 18, the column sequencer 19 and the row sequencer 20 will be described.
The CLK signal and the CS signal given from the outside are converted into the / RAS signal and the / CAS signal by the sequencer 18. It should be noted that these signals correspond to the normal dynamic RA.
It is a signal equivalent to the / RAS signal and / CAS signal used in M.

The / RAS signal is supplied to the row-related sequencer 19, and the row-related sequencer 19 generates the XAL signal, the RA signal and the SE signal for controlling the row-related sequencer, and outputs the XA signal.
The L signal signal is input to the row address buffer 9 and RA
The signal is input to the row decoder 11, and the SE signal is input to the sense amplifier group 12 (see FIG. 3). Also, / CA
The S signal is supplied to the column sequencer 20, and the column sequencer 20 controls the YAL signal for controlling the column system,
The RE signal and the DE signal are generated, and the OE signal (not shown in FIG. 4) is generated in the read mode together with the RW signal, and the DL signal and the WE signal are generated in the write mode (see FIG. 4). The YAL signal is input to the column address buffer 10, the RE signal is input to the column decoder 13, and the DE signal is input to the data amplifier 14. In the read mode, the OE signal is output to the data output buffer 15, and in the write mode, the DL signal is output to the data input buffer 17 and the WE signal is output to the write amplifier 16.

Next, the row address buffer 9, the row decoder 11, the column decoder 13, the column address buffer 10 and the like will be described. In the row system, the external row address R is taken into the row address buffer 9 when the XAL signal rises, the row address of the row address buffer 9 is decoded by the row decoder 11 when the RA signal rises, and the word line corresponding to the row address is read. Activate WLi. Then, all the memory cell data on the word line WLi are output to the corresponding bit lines. (The j-th column is described in the drawing.) This bit line 4
The data output to is amplified when the sense amplifier 1 is activated when the SE signal rises.

In the column system, the external column address C1 is changed to the column address buffer 1 when the YAL signal rises.
When the RE signal rises, the column address of the column address buffer 10 is decoded by the column decoder 13, and the column select gate enable signal YSWj corresponding to the column address is activated. As a result, the data amplified on the bit line 4 is output on the IO bus 6. Next, when the DE signal rises, the data amplifier 1
4 is activated and the data on the IO bus 6 is amplified.
In the read mode, if the OE signal is activated, I
The data on the O bus 6 is output to the data terminal DATA via the output buffer 15.

The timing diagram shown in FIG. 4 describes the write mode. In the write mode, the DL signal rises at the same timing as the rise of the YAL signal, and the external data D1 is taken into the data input buffer 17. This input data (external data D1) is compulsorily written on the IO bus 6 via the write amplifier 16 when the WE signal rises after the DE signal rises in the column operation described above. At the end of writing, the column control signal (YAL
Signal, RE signal and DE signal) and input / output control signal (D
L signal and WE signal) are reset.

In the memory access cycle in the page access mode, the / CAS signal is repeated in response to the repetition of the second and third clocks and the column-related control signals (YAL signal, RE signal and DE signal).
By repeating the input and output control signals (DL signal and WE signal) in the same manner, the write cycle for the external data D2 and D3 of the external column addresses C2 and C3 is performed in the same manner as the external data D1. Be seen.

[0013]

However, the conventional semiconductor memory device (/ RAS, / C having the above-mentioned structure is used.
The page access (memory access in the page access mode) in the memory whose memory access is controlled by the external basic clock CLK and the external chip select signal CS, not the AS control, needs to be continuously performed. It was impossible to suspend the page access in the middle (hereinafter referred to as "page mode cycle"), that is, Knoop.

As a result, when it is attempted to execute a page mode cycle with three basic clocks due to the limitation of system performance, the page mode cycle of the memory operates in two basic clock units. Therefore, in this system, four basic clocks are used. It must be used to perform page access for one page address (the target page access is performed with two basic clocks, and the dummy read page access is performed with the remaining two basic clocks), resulting in a significant deterioration in system performance. There was a problem.

In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor memory device capable of interrupting a memory access during a page access mode cycle and minimizing deterioration of system performance. That is.

[0016]

A semiconductor memory device of the present invention is a control which outputs a plurality of control signals for controlling a cycle of memory access in a page access mode when a basic clock and a signal indicating the start of a cycle are input. The signal output means and a part of the control signal and the external Knoop control signal output from the control signal output means are input, and the output level of the part of the control signal is invalidated by the external Knoop control signal for memory access. And a control signal control means for controlling the above.

[0017]

According to the structure of the present invention, the control signal output means outputs a plurality of control signals for controlling the memory access cycle in the page access mode,
The control signal control means controls the output level of a part of the control signals based on the external Knoop control signal, and invalidates the control signal for memory access. Therefore, the memory access can be interrupted during the cycle of the page access mode, and the page access can be performed discontinuously.

[0018]

1 is a block diagram showing the structure of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG. 1 in a page access mode. 2 is a timing chart showing the operation in the write mode.

In FIG. 1, 1 is a sense amplifier (S
A), 2 is a transfer gate, 3 is a memory cell, 4
Is a bit line, 5 is a column select gate, 6 is an IO bus, 7 is a column select gate enable signal line, 8 is a word line, 9 is a row address buffer, 10 is a column address buffer, 11 is a row decoder, and 12 is a sense. Amplifier group, 13 is a column decoder, 14 is a data amplifier, 15 is a data output buffer, 16 is a write amplifier,
Reference numeral 17 is a data input buffer, 18 is a sequencer, 19 is a row sequencer, 20 is a column sequencer, 21 is a Knoop flag buffer, 22 is an AND gate, and 23 is an AND gate group. Further, 50 is a control signal output means including a sequencer 18, a row sequencer 19 and a column sequencer 20, and 60 is a Knoop flag buffer 2.
It is a control signal control means composed of 1 and an AND gate group 23.

In FIGS. 1 and 2, CLK is an external basic clock for memory access, CS is an external chip select signal indicating the start of a cycle, R / W is an external read / write control signal, and NOOP is an external Knoop control signal. ,
ADD (ADDRESS) is an external address, DATA is external data, / RAS is an internal row address strobe signal, / C
AS is an internal column address strobe signal, RW is an internal read / write control signal, XAL is a row address latch signal, RA is a row decoder activation signal, WLi is a word line (i-th), SE is a sense enable signal, and YAL is a column. Address latch signal, RE is column decoder activation signal, YSWj is column select gate enable signal (jth), DE is data amplifier enable signal, D
L indicates a data latch signal, and WE indicates a write amplifier enable signal.

In FIG. 2, R is an external row address, C1 and C2 are external column addresses, and D1 and D2 are external data. As shown in FIG. 1, the semiconductor memory device has a CS indicating a CLK signal and the start of a cycle.
A plurality of control signals for controlling the memory access cycle in the page access mode, that is, XAL signal, RA signal, SE signal, YAL signal,
Control signal output means 50 for outputting RE signal, DE signal, OE signal, DL signal and WE signal, and a part of control signals output from this control signal output means 50, namely RE
Signal, DE signal, OE signal, DL signal and WE signal and NOOP signal are input, and the output level of the RE signal, DE signal, OE signal, DL signal and WE signal becomes invalid for memory access by this NOOP signal. And a control signal control means 60 for controlling as described above.

With respect to the access timing of the semiconductor memory device thus configured, in a normal read / write cycle (not in page access mode), four basic clocks (first clock to fourth clock) are one cycle, The page mode cycle can be executed by repeating the second and third clocks a plurality of times. (Two page mode cycles are performed in FIG. 2.)
External read / write control signal R for read / write control
/ W. If the R / W signal is at high level, it becomes a read cycle, and if it is at low level, it becomes a write cycle.

The address is ADDRESS,
A row address is multiplexed at the first clock and a column address is multiplexed at the second clock. In addition, the data is input data as DATA at the second clock.
Next, the internal operation of this semiconductor memory device in the page access mode will be described.

The CLK signal and the CS signal given from the outside are supplied to the / RAS signal and the / CAS signal by the sequencer 18.
Convert to signal. Note that these signals are signals equivalent to the / RAS signal and / CAS signal used in a normal dynamic RAM. The row sequencer 19 supplied with the / RAS signal generates the XAL signal, the RA signal and the SE signal for controlling the row system. Then, the XAL signal is input to the row address buffer 9, the RA signal is input to the row decoder 11, and the SE signal is input to the sense amplifier group 12 (see FIG. 1).

The column sequencer 20 supplied with the / CAS signal controls the YAL signal, R, which controls the column system.
Generates E signal and DE signal, and OE signal in read mode together with RW signal (not shown in FIG. 2)
Generated, and in the write mode, DL signal and WE
Generate a signal (see FIG. 2). Then, the YAL signal is input to the Knoop flag buffer 21 and the column address buffer 10, and the RE signal, the DE signal, the OE signal, and the D signal are input.
The L signal and the WE signal are output to each AND gate 22 in the AND gate group 23.

However, the OE signal is output in the read mode, and the DL signal and the WE signal are output in the write mode. Also,
The output levels of the RE signal, DE signal, OE signal, DL signal and WE signal are controlled by the NOOP signal in units of / CAS cycle. In the row system, the external row address R is taken into the row address buffer 9 when the XAL signal rises, the row address of the row address buffer 9 is decoded by the row decoder 11 when the RA signal rises, and the word line WLi corresponding to the row address is obtained. Activate. Then, all the memory cell data on the word line WLi are output to the corresponding bit lines. (The j-th column is described in the drawing.) The data output to the bit line 4 is amplified by activating the sense amplifier 1 when the SE signal rises.

In the column system, the external column address C1 is set to the column address buffer 1 when the YAL signal rises.
The data of the external Knoop control signal NOOP is fetched into the Knoop flag buffer 21 while being fetched into 0. At this time, if it is not a NOOP cycle (when the data in the Knoop flag buffer 21 is 1), the AND gate group 23
Accordingly, the RE signal is output to the column decoder 13, the DE signal is output to the data amplifier 14, the OE signal is output to the data output buffer 15, the DL signal is output to the data input buffer 17, and the WE signal is output to the write amplifier 16. Output to.

However, the OE signal is output in the read mode, and the DL signal and the WE signal are output in the write mode. Then, when the RE signal rises, the column address of the column address buffer 10 is decoded by the column decoder 13, and the corresponding column select gate enable signal YSWj is activated. As a result, the data on the bit line 4 becomes IO.
It is output on the bus 6. Next, when the DE signal rises, the data amplifier 14 is activated and the data on the IO bus 6 is amplified. In the read mode, the data on the IO bus 6 is output to the data terminal DATA via the output buffer 15 by activating the OE signal.

The timing diagram shown in FIG. 2 describes the write mode. In the write mode, the DL signal rises at the same timing as the rise of the YAL signal, and the external data D1 is taken into the data input buffer 17. This input data (external data D1) is supplied to the write amplifier 1 when the WE signal rises after the DE signal rises in the column operation described above.
It is forcibly written on the IO bus 6 via 6. At the end of writing, column-related control signals (YAL signal, RE signal and DE signal) and input / output control signals (DL
Signal and WE signal) are reset.

In the page mode cycle, the / CAS signal is repeated in response to the repetition of the second and third clocks, and the column system control signals (YAL signal, RE signal and DE signal) and the input / output control signals (DL signal and The WE signal) is similarly repeated to access the external data D2 of the external column address C2. on the other hand,
In the case of NOOP cycle (that is, when the data in the Knoop flag buffer 21 is 0, the clock cycle described as N in the external basic clock CLK shown in FIG. 2)
In addition, the AND gate group 23 constituting the control signal control means 60 does not generate the RE signal, the DE signal, the OE signal, the DL signal and the WE signal (the output level is 0).
This is because the RE signal, the DE signal, the OE signal, the DL signal and the WE signal are generated by the AND operation of the output signal of the column sequencer 20 and the value of the Knoop flag buffer 21 by the AND gate 22. .. Also,/
The CAS signal is also reset immediately when the value of the Knoop flag buffer 21 is 0, so that the YAL signal is also reset. As a result, the column decoder 13, the data amplifier 14, the data output buffer 15, the write amplifier 16 and the data input buffer 17 do not operate, and the page access is interrupted. This makes it possible to control execution and non-execution of page access during the page address mode cycle.

[0031]

According to the semiconductor memory device of the present invention, the control signal output means outputs a plurality of control signals for controlling the cycle of memory access in the page access mode, and the control signal control means causes the external Knoop to operate. The output level of a part of the control signals is controlled based on the control signal, and the control signal is invalidated for the memory access. Therefore, the memory access can be interrupted during the cycle of the page access mode, and the page access can be performed discontinuously.

As a result, in order to increase the access speed to the memory (in the access without changing the row address), the page access can be intermittently performed without leaving the cycle of the page access mode. In addition, since the cycle time of the page access mode cycle can be set to a time other than twice the basic clock, it is possible to minimize the deterioration of system performance even when the basic clock frequency of the memory and the system clock frequency do not match. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the semiconductor memory device shown in FIG. 1 in a page access mode.

FIG. 3 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 4 is a timing diagram for explaining the operation of the conventional semiconductor memory device in the page access mode.

[Explanation of symbols]

50 Control signal output means 60 Control signal control means CLK Basic clock CS External chip select signal (signal indicating the start of cycle) NOOP External Knoop control signal

Claims (1)

Claim: What is claimed is: 1. A semiconductor memory device having a page access mode, wherein a cycle of memory access is controlled by a continuous basic clock and a signal indicating the start of a cycle. Control signal output means for inputting a signal indicating the start of a cycle and outputting a plurality of control signals for controlling the memory access cycle in the page access mode, and a part of the control signals output from the control signal output means And a control signal control means for receiving an external Knoop control signal and controlling the output level of the part of the control signals to be invalid for the memory access by the external Knoop control signal.