JPH01269140A - Memory extending circuit - Google Patents

Abstract

PURPOSE:To extend a memory area by automatically selecting a memory bank, in which a program is present, during the instruction fetching action period of a processor and selecting a memory bank corresponding to bank selecting data sent by a processor beforehand during the period except it. CONSTITUTION:When a register 2 holds bank selecting data sent from a processor 1 and a processor 1 executes an action to fetch the instruction in a program, a period signal generating part 3 detects the instruction fetching action period and a bank selecting part 4 selects a memory bank to store the program. During the period except the instruction fetching action period, a memory bank corresponding to the contents of the register to hold the bank selecting data sent from the processor beforehand is selected by the bank selecting part 4. Thus, a memory area to store data, etc., independently from the size of the program can be secured and the memory area can be extended.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory expansion circuit that allows a processor to access a memory area larger than the number of bits of an address bus of the processor. be.

[Conventional technology]

The size of the memory area that can be accessed by a processor such as an MPU is determined by the number of bits of the address bus that the processor has. For example, for a processor with a 16-bit address bus, 2'6 = 65536.
Can handle memory areas of addresses.

However, in devices that handle large amounts of programs and data, a problem arises in that the memory area normally available to the processor cannot accommodate the programs and data. For this purpose, a memory area expansion function is required. A bank switching method is generally known as a method for realizing such a function.

In a memory expansion circuit using this bank switching method, any one of a plurality of memory areas (one memory area is called a bank) provided in the same address space as seen from the processor is transferred to a bank that is sent out in advance from the processor. It is selected based on the selection data, and it appears to the processor that the access is within the memory area that the processor itself can handle, but in reality there are multiple banks in the same address space, so the added bank The memory area is expanded by the number of objects.

[Problem to be solved by the invention]

By the way, the contents that should be stored in the memory area of -C include programs and other data, but the memory expansion circuit using the conventional bank switching method stores only the bank that is uniquely determined by the bank selection data from the processor. Since the configuration is such that the selection is always made until the next bank selection data is sent from the processor, the program should be stored in common in each bank, or the program should be stored in a basic bank that is not subject to bank switching. However, it was necessary to provide a plurality of banks to be switched in an address space other than the address space occupied by the basic bank. For this reason, the larger the program size, the more limited the size of the memory area that can be expanded.Especially when the entire memory area that the processor can normally handle is required to store the program, expanding the memory area becomes more difficult. becomes impossible.

An object of the present invention is to provide a memory expansion circuit that can expand the memory area even in such a case.

[Means to solve the problem]

In order to achieve the above object, the memory expansion circuit of the present invention includes a register that holds bank selection data from a processor, and a period signal that detects an instruction fetch operation period of the processor and generates a signal indicating the period. A generation section,
Based on the signal from the period signal generator, the memory bank in which the program is stored is selected during the instruction fetch operation period of the processor, and the memory bank corresponding to the bank selection data held in the register is selected during other periods. It consists of a bank selection section that selects a bank.

[Effect]

In the memory expansion circuit of the present invention, the register holds the bank selection data sent from the processor, and when the processor performs an operation to fetch an instruction in the program, the period signal generation section detects the instruction fetch operation period. , a bank selection section selects a memory bank in which a program is stored.

Furthermore, during a period other than the instruction fetch operation period, the bank selection section selects a memory bank corresponding to the contents of a register that holds bank selection data sent in advance from the processor.

[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing a configuration example of a processor system to which a memory expansion circuit according to the present invention is applied, 1 indicates an address signal, an instruction fetch signal M1, a read signal MRD, a write signal 10W, and other various signals. It is a processor that outputs or inputs, the above address signal is a signal output to address bus 11 when processor 1 executes a program, and instruction fetch signal M1 indicates the timing at which processor 1 reads an instruction (instruction code). The write signal 10W is a signal indicating the timing at which the processor 1 writes data to a register or the like. Each of these signals is output within the processor 1 in synchronization with the original clock signal Φ. A register 2 internally holds bank selection data output to the data bus 9 by the program operation of the processor 1 in accordance with the timing of the write signal 10W. 3 is the original clock signal Φ and the processor l.
Based on the instruction fetch signal M1 output from the instruction decoder 7 and the timing control signal TC from the instruction decoder 7, which will be described later,
This is a fetch period signal generator that generates a fetch period signal AC that becomes "0" during an instruction fetch operation period of the processor 1. 4 is a memory bank 6-1 in which a program is stored, which will be described later, during a period in which a fetch period signal AC outputted from the fetch period signal generator 3 indicates "0", that is, during an instruction fetch operation period of the processor 1. It is a bank selection data generator that generates the corresponding bank selection data by itself and outputs it to the bank selection data bus 10, and outputs the bank selection data held in the register 2 to the bank selection data bus 10 during other periods. . 5 enables one of the bank selection signals C3 and -C3n (state "O") by decoding the bank selection data output from the bank selection data generator 4 to the bank selection data bus 10. This is a bank selection data decoder. 6-1 to 6-n are memory banks constituting the first to nth banks, respectively. In this embodiment, a program to be executed by the processor 1 is stored in the memory bank 6-1 constituting the first bank. Data and the like are stored in memory banks 6-2 to 6-n that constitute other banks.

Note that each memory bank 6-1 to 6-n has a memory capacity of 64K, for example.
7, which has a capacity of This is an instruction decoder that generates a timing control signal TC required to set the fetch period signal AC to "O" during the period, and sends it to the fetch period signal generator 3. 8 is an original clock oscillator that generates an original clock signal Φ.

FIG. 2 is an operation timing chart showing the waveforms of each part in FIG. 1 to an instruction consisting of one instruction element C8, and in the next period t8, as seen from the processor 1 of the memory bank 6-2, the address A! is the same as the instruction element C1! .

The data D1 is read from the memory bank 6-1 during the next period t3+"4, and an instruction consisting of two instruction elements cz-+ and cz-t is fetched from the address A23 of the memory bank 6-1. , when data D8 is read from the address bus of memory bank 6-2. FIG. 3 shows the transition of the memory bank to be accessed by processor 1 at that time.

The operation of this embodiment will be described below with reference to the example shown in FIG.

(1) Instruction fetch operation period t.

Before processing the data in the memory bank 6-2, the processor 1 sends and writes bank selection data S8 corresponding to the memory bank 6-2 to the data bus 9, as shown by the broken line in FIG. By keeping the signal 10W at "O" for a predetermined period of time, the bank selection data S is held in the register 2.

Processor 1 performs instruction fetch operation period 1. When you enter,
As shown in FIG. 2, the instruction fetch signal M1 is
0" and outputs the address (processor address) of the instruction to be fetched (processor address) to the address bus 11. When the instruction fetch signal M1 is set to "O" by the processor 1, the fetch period signal generator 3 As shown in FIG. 2, the fetch period signal AC is immediately set to "θ".

When the fetch period signal AC is set to "0", the bank selection data generator 4 sets the fetch period signal AC to "0" regardless of the bank selection data S2 held in the register 2.
During the period in which the program is stored, the bank selection data S1 corresponding to the memory bank 6-1 in which the program is stored is transferred to the second
As shown in the figure, the bank selection data is output to the bank selection data decoder 5 via the bank selection data bus 10.

The bank selection data decoder 5 receives this bank selection data S.
By decoding 1, only the bank selection signal C8I for the memory bank 6-1 is enabled (state B of "0").
Only memory bank 6-1 among memory banks 6-1 becomes valid.

Since the address All output from the processor 1 to the address bus 11 is added to the memory bank 6-1, the bank selection signal C81 becomes "0" and the read signal M
With the addition of RD, the instruction element C1 stored at address A□ is read onto data bus 9.

The instruction element C1 output to the data bus 9 is applied to the processor 1 and instruction decoder 7. The instruction decoder 7 takes in this instruction element C3 at the timing of the instruction fetch signal M1 output from the processor 1, and determines how many instruction elements the current instruction consists of by decoding its contents. , and outputs a timing control signal TC, matching the required number of instructions, to the fetch period signal generator 3.

The fetch period signal generator 3 takes in the timing control signal TC output from the instruction decoder 7 while the instruction fetch signal M1 output from the processor 1 is valid (10''), and the instruction fetch signal M1 is valid. From the time when the timing control signal TC becomes ``l'', that is, the timing control signal TC becomes ``l''.

As shown in FIG. 2, the fetch period signal AC is kept in the "0" state in synchronization with the original clock signal Φ for a period indicated by . As described above, the bank selection data generator 4 sends the bank selection data S1 corresponding to the memory bank 6-1 in which the program is stored to the bank selection data bus 10 while the fetch period signal AC is "0". Since the memory bank 6-1 is output, the memory bank 6-1 is selected during the period L1. Then, the fetch period signal AC is invalid (
As shown in FIG.
8 will be output to the bank selection data bus 10.

Further, the instruction element C1 sent from the memory bank 6-1 to the processor 1 via the data bus 9 is read into the processor 1 in synchronization with the read signal MRD output from the processor l, and is configured with the instruction element C1. The program operation is started by the command given.

(1) Also the data reading operation period.

Next, when a program operation is started by the instruction composed of the instruction element C1 read into the processor 1, the processor 1 starts the period! Proceed to the operation shown in .゛Here, a program operation based on an instruction composed of instruction element C1 is executed at address A8. of memory bank 6-2. Since it is assumed that the data D1 (same as the aforementioned program address) is to be read, the processor 1 first outputs the read address A□ to the address bus 11 in the period t.

As mentioned above, at the time when the period moves to , the bank selection data S8 for selecting the memory bank 6-2 has been output from the bank selection data generator 4 to the bank selection data bus 10, so this bank Selection data S! is decoded by bank selection data decoder 5, so that only bank selection signal C32 for memory bank 6-2 is enabled as shown in FIG. Therefore, when processor 1 outputs read signal MRD as shown in FIG. 2, only memory bank 6-2 operates.

The memory bank 6-2 receives the address A! which is output from the processor 1 to the address bus 11. 1 and read signal MRD
and bank selection signal C32, the address Az
Data D stored in +.

is output to the data bus 9 as shown in FIG.

During this period t2, the instruction fetch signal M1 output from the processor 1 is 1'', so the instruction decoder 7
And the fetch period signal generator 3 does not operate, and the data D
, is read into processor 1.

(3) Instruction fetch operation period t3+'4 Next, period t,
When the instruction fetch operation is performed again as shown in FIG.
The instruction element Cl-1 output from -1 to the data bus 9 is read into the processor 1, and the program operation of the instruction element C2-1 is performed. However, now the command element C
Since it is assumed that 2-1 alone does not constitute one instruction and another instruction element C8-2 is required, the following operation is performed.

During period t, the memory bank 6-1 receives the bank selection signal C81 output from the bank selection data decoder 5 and the address Δ output from the processor 1 to the address bus 11.
22 and the read signal MRD output from the processor 1, the instruction element C! is sent to the data bus 9. When -8 is output, the instruction decoder 7 analyzes this instruction element C8-9 and recognizes that it is an instruction type that requires two elements. and,
A timing control signal TC that matches this is output to the fetch period signal generator 3. The fetch period signal generator 3, which receives the timing control signal TO8 outputted from the instruction decoder 7, generates a fetch period signal AC over a period t to a period L4 in synchronization with the original clock signal φ, as shown in FIG. continues to be held at “0”. Therefore, the period t
4, the memory bank 6-1 continues to be selected, and the address A is output to the address bus 11 by the processor 1 in the memory bank 6-1. Command element C! stored in C! -1 is accessed, and the processor 1 reads and recognizes this instruction element C1-8 as the second instruction element.

(4) Data reading operation period t.

Instruction element Cz −+ + C read into processor 1
! The program operation is started by an instruction consisting of -g, and period 1. The operation shown in the 0 period t, which is the same as the operation shown in the period t2, is that the data D stored at address A+44 of the memory bank 6-2
, are read into the processor 1 via the data bus 9.

As described above, processor 1 performs an instruction fetch operation.

Repeat the cycle of operations according to this fetched instruction,
In accordance with this, the memory expansion circuit also repeats the operation of selecting the memory 6-1 in which the program is stored and the operation of selecting another memory specified by the bank selection data from the processor 1. , the explanation has focused on the read operation from the memory, but the same operation is performed even when writing to the memory occurs.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various other additions and changes are possible.For example, the address of the address bus 11 is added to the bank selection data decoder 5, Bank 6-1~6
The bank selection data decoder 5 may generate the chip selection signal of the memory chip composing the memory chip -n and the bank selection signals C3° to C311.

[Effects of the Invention] As explained above, according to the present invention, the memory bank in which the program exists is automatically selected during the instruction fetch operation period of the processor, and the memory bank in which the program exists is automatically selected during the instruction fetch operation period of the processor. Since the memory bank corresponding to the bank selection data is selected, a memory area for storing data etc. can be secured independent of the program size, especially a memory area where the program size is determined by the bit width of the address bus of the processor. even if it is equal to the size of
Memory area can be expanded. In addition, since detection during instruction fetch operations and bank switching between the memory bank where the program resides and other memory banks are performed by the memory expansion circuit itself, which operates independently of the processor, there is an increase in program load and processor overhead. It does not result in an increase in time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The operation timing chart of the device shown in the figure and FIG. 3 are diagrams showing the transition of memory banks to be accessed. In the figure, 1...Processor 2...Register 3...Fetch period signal generator 4...Bank selection data generator 5...Bank selection data decoder 6-1 to 6-n...Memory Bank 7... Instruction decoder 8... Original clock oscillator 9... Data bus 10... Bank selection data bus 11... Address bus AC... Fetch period signal TC... Timing control signal CS, ~C3n...bank selection signal

Claims (1)

[Scope of Claims] A register that holds bank selection data from a processor; a period signal generation unit that detects an instruction fetch operation period of the processor and generates a signal indicating the period; and a register that stores bank selection data from the period signal generation unit. a bank selection unit that selects a memory bank in which a program is stored during an instruction fetch operation period of the processor based on the signal, and selects a memory bank corresponding to bank selection data held in the register during other periods; A memory expansion circuit characterized by comprising: