JP3045731B2 - Sequence control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequencer control method controlled by a microprogram, and more particularly, to a sequencer capable of significantly reducing the required microprogram memory capacity.

[Prior art and its problems]

Microprogram-controlled sequencers are often used to generate a desired data sequence, such as a memory address sequence.

FIG. 2 shows a block diagram of this type of sequencer according to the prior art. The sequencer shown in FIG. 1 operates as an address generator that outputs addresses at fixed time intervals. The microinstruction read from the microprogram memory 201 is stored in Iin of the sequence control unit 203.
Terminal. Based on the microinstruction given in this way, the sequence control unit 203 gives an address to be output in the current operation cycle to the buffer 205 in synchronization with the clock given to the CLK terminal, and supplies the same address to the next time. The microinstruction to be read is given to the microprogram memory 201 as an address for designating the microinstruction.

However, such a conventional sequencer has a problem that the capacity of the microprogram needs to be considerably increased. For example, when this sequencer is used as an address generator as described above, if an attempt is made to generate an address sequence for a large-capacity memory, the word length of the address that must be generated becomes longer and the microprogram memory is provided. The number of words that must be exponentially increases. For example, if the word length of the address to be generated is 10 bits,
201 requires only 1024 words, whereas 16 bits requires 65536 words. Since the microprogram memory 201 is required to be extremely high-speed, preparing such a large-capacity memory has many problems such as cost, heat generation, mounting, and acquisition of a high-speed memory chip.

In order to reduce the required amount of the microprogram memory, a method in which the lower n bits of the address generated by the sequencer are not given to the microprogram memory, but only the upper part controls access to the microprogram memory can be considered. However, when such control is performed, the degree of freedom is impaired, for example, it becomes difficult to operate generated addresses in small units of less than 2 ⁿ . Therefore, such control can be adopted only in a limited situation.

Also, in a normal application such as an address generator, the required address sequence is not completely random, and for example, the sequence of addresses from address 1000 to address 1128 is repeated 100 times before proceeding to the next. In this case, a continuous series, that is, an address to be generated this time is an increment of the previous address. The proportion of changes in flow such as japs and calls is relatively small. The microinstruction corresponding to the continuous part is a so-called NOP instruction that does not perform any substantial operation. Therefore, most of the microprogram memory is filled with NOP instructions, and the utilization efficiency becomes extremely poor.

[Object of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to reduce the capacity of a microprogram memory without limiting the degree of freedom of sequence control.

[Summary of the Invention]

According to one embodiment of the present invention, there is provided a sequencer that reduces the size of the microprogram memory using the above-described properties of the sequence to be normally generated. That is, a continuous portion in the sequence is generated by incrementing the counter, and microprogram control is performed only for a portion where a jump, a call occurs, or may occur. As a result, the conventional series of NOP instructions can be removed from the microprogram, so that the capacity of the microprogram memory can be significantly reduced.

(Example of the invention)

FIG. 1 shows a block diagram of a sequencer configured based on one embodiment of the present invention.

In the figure, the execution of the microinstruction gives the next microinstruction address to the microprogram memory 101. The microinstruction read out by this is
This is supplied to the Iin terminal of the sequence control unit 103. At the same time, the first and last address series to be continuously generated are read from the microprogram memory 101 and latched by the counter 105 and the register 107, respectively, according to appropriate timing signals. Counter 105
Is latched in the buffer 111 in accordance with an appropriate clock, and is output to the outside.

The head address latched by the counter 105 is incremented by the clock A, and the increment result is latched by the buffer 111 and output. In parallel with this, the output of the counter 105 is compared with the final address latched in the register 107 by the comparator 109. Here, when a match is detected, the match detection signal opens the AND gate 113, and sends the clock A delayed by the delay 115 to the clock input CLK of the sequence control unit 103. As a result, the sequence control unit 103 executes the previously read microinstruction. By this execution,
At the same time that the microinstruction to be executed next is read and given to the sequence control unit 103, a new value read from the microprogram memory 101 is latched in the counter 105 and the register 107. Is repeated. The new value may be a start address and an end address of a continuous address series different from the previous value. Alternatively, in order to regenerate the same address series as the previous time, the same start address and last address as the previous time may be used. Further, when it is necessary to generate a random sequence instead of a continuous address sequence, the start address and the end address may be the same address.

Needless to say, the present invention is not limited to the above-described embodiment, but also includes an embodiment with extensive modifications.

To give just a part of such another example, instead of giving the end address together with the start address in the above-described embodiment, the length of a sequence to be generated continuously may be given.

Further, in the above-described embodiment, the sequence control unit 103
The microinstruction was executed after the arrival of the clock B from the gate 113, and the next start address and the last address were read from the microprogram memory 101 based on the execution result. If there is no conditional branch or the like due to an event external to the microprogram control device, the microinstruction is executed one step ahead and executed instead, and the result is stored in the intermediate buffer. (That is, the cycle of updating the address output via the buffer 111) can be shortened.

That is, an intermediate buffer for temporarily holding the output of the microprogram memory 101 is placed, and the next start address and last address, and the next microinstruction to be executed are placed there. Thus, when the comparison circuit 109 detects that the end of the continuous address sequence has been reached,
The data necessary for the generation of the next address sequence in a shorter time than in the above-described embodiment is stored in the counter 105 and the register 107.
Can be set to Also, the microinstruction placed in the intermediate buffer is executed at the same timing, and the next necessary data is set in the intermediate buffer.

Further, the sequencer of the present invention is not limited to the generation of an address sequence, but can be used for generating a sequence of data having the above-described properties in any application.

〔The invention's effect〕

As described in detail above, according to the present invention, the required capacity of the microprogram memory can be greatly reduced, so that it is easy and inexpensive to adopt a high-speed element in the microprogram memory for high-speed operation. Is obtained.

[Brief description of the drawings]

FIG. 1 is a view showing an embodiment of the present invention, and FIG. 2 is a view for explaining a conventional technique. 101: Microprogram memory 103: Sequence control unit 105: Counter 107: Register 109: Comparator 111: Buffer 113: AND gate 115: Delay

Claims (3)

(57) [Claims] 1. A sequencer comprising the following (a) to (e) and continuously generating an arbitrary data sequence: (a) including a start condition and an end condition of a data sequence having continuous values A microprogram memory including a microinstruction; (b) a function of reading and executing the microinstruction from the microprogram memory; and a sequence control unit performing the function in response to a first signal. (C) reading of the microinstruction. A counter that stores and counts the continuous value start condition in the microinstruction to be read and outputs a data sequence each time the operation is performed; (d) a register that stores an end condition of the continuous value in the microinstruction; (E) comparing the counter output with the contents of the register, generating the first signal when the end condition is satisfied, Comparator sends to the Sequence controller. 2. The sequencer according to claim 1, wherein start data and end data are used as the start condition and the end condition included in the microprogram, respectively. 3. The sequencer according to claim 1, wherein, as the start condition and the end condition included in the microprogram, a head data and a length of a sequence to be continuously generated are used, respectively.