JPH0626305B2 - Double memory configuration pulse programmer - Google Patents

Description

The present invention relates to a pulse programmer having a double memory structure for generating a plurality of pulse sequences in a programmable manner.

[Conventional technology]

FIG. 5 is a diagram for explaining an example of a conventional pulse programmer that programmablely generates a leak pulse sequence.

A recent application of pulse FT NMR (Fourier transform nuclear magnetic resonance apparatus) requires a function capable of freely generating various pulse sequences. A pulse programmer is one that generates a pulse sequence in a programmable manner in response to such a demand. This is basically the fifth
As shown in FIG. (A), a program code A ₁ composed of “1” (or “H”), “O” (or “L”) data and time width data corresponding to a plurality of pulse sequences, _{a 2, a 3, a 4} , sequentially read in chronological a ... it is configured to generate a plurality of pulse sequence shown in FIG. 5 (b).

The conventional program-type pulse programmer is a high-speed RAM (random write / read memory; Ra
ndam Access Memory) to store a fixed program code and execute this cyclically repeatedly, or to supply the required program code continuously from the host computer using FIFO (First In First Out). It was a thing.

[Problems to be solved by the invention]

By the way, of the above-mentioned conventional methods, the former is once RA
Since the program code stored in M is simply executed repeatedly, the load on the host computer will be eliminated after the host computer downloads the program code to the pulse programmer, but it will be sufficient to meet the recent demands for generation of complicated pulse sequences. Can not. Also, F
The latter method of continuously supplying the program code from the host computer using the IFO has a degree of freedom to cope with various complicated pulse sequences, but has a problem that the load on the host computer becomes heavy.

Further, the applicant of the present application has separately proposed a method in which a high-speed RAM is used in a ring buffer configuration, a table prepared in advance by a microprocessor is transferred to the ring buffer every cycle, and steps are executed infinitely. . However, this method also has the degree of freedom to cope with various complicated pulse sequences, but since it is necessary to transfer the program code of the next cycle one after another during the execution of the pulse sequence, it takes longer than the time required to transfer the program code. There is a constraint that the cycle cannot be executed repeatedly in a short time. Therefore, there arises a problem that it cannot cope with the speedup.

The present invention solves the above problems, and an object of the present invention is to provide a pulse programmer having a double memory configuration capable of generating an arbitrary pulse sequence and reducing the load on the host computer. It is what

[Means for solving problems]

Therefore, the pulse programmer of the double memory configuration of the present invention stores a pulse sequence code in which a program code consisting of output state and time width data is sequentially arranged in a sequence execution memory and controls a read address of the sequence execution memory. A pulse programmer having a double memory configuration for programmably generating a plurality of pulse sequences, which stores a table for storing the updated contents of the variable portion of the pulse sequence code and a pulse sequence code for each cycle 2 According to the table, one of the sequence execution memories generates a pulse sequence, while the other sequence execution memory updates the variable part, and switches between the two sequence execution memories. It is characterized in that to generate the Sequence.

[Action]

In the double memory configuration pulse programmer of the present invention,
Sequential program code is read from one sequence execution memory to generate a one-cycle pulse sequence, the variable part of the pulse sequence code of the other sequence execution memory is updated according to the table, and then the sequential program code is read from the other sequence execution memory. The pulse sequence of the next cycle is read out and the variable part of the pulse sequence code of one sequence execution memory is updated according to the table. In this way, while alternately switching between the two sequence execution memories, the variable part of the other sequence execution memory is updated while the pulse sequence is being generated by one sequence execution memory, so that the cycle repetition time can be shortened. It can respond and can generate a pulse sequence indefinitely.

〔Example〕

 Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining one embodiment of a pulse programmer having a double memory structure according to the present invention, FIG. 2 is a diagram for explaining the contents of a program code stored in a sequence execution memory, and FIG. FIG. 4 is a diagram for explaining the execution sequence of the program code shown in FIG. 2, and FIG. 4 is a diagram for explaining the transfer processing of the program code. In the figure, 1 is an MPU (microprocessor), 2
Is an I / O interface, 3 is a memory, 4a and 4b are sequence execution memories, 5 is an address sequencer, 6 is a state register, 7 is a time register, 8 is an instruction decoding / control circuit, 9 is timing logic,
Reference numeral 10 is a buffer, and 11 is a gate.

A pulse programmer having a double memory structure according to the present invention stores an MPU 1 for controlling the whole as shown in FIG. 1, an I / O interface 2 for receiving a pulse sequence from a host computer, and a pulse sequence table. Memory 3, two pulse sequence execution memories 4a and 4b which store a pulse sequence and output an ON / OFF state for a given time in the order of a given address, a pulse sequence execution memory 4a
And an address sequencer 5 for controlling the addresses of 4b, a state register 6 for temporarily storing the state data of the pulse sequence execution memories 4a and 4b, and a time data which is another output of the pulse sequence execution memories 4a and 4b. Time register 7, counts the given time data with a base clock (basic clock that gives the time reference), decodes the instruction logic of the timing logic 9 that gives the time timing, the output of the state register 6, and loops the pulse sequence. An instruction decoding / control circuit 8 for controlling the output of the state register 6 and a buffer 10 for taking out the output of the state register 6 to the outside. Also, the gate 11 is
MPU1 and its memory 3, I / O interface 2
Etc. and the pulse sequence execution memories 4a and 4b are controlled by the bus. The MPU 1 turns on when the sequence code is transferred to the sequence execution memories 4a and 4b, and the sequence execution memories 4a and 4b pulse at high speed. It turns off during execution of the sequence, and the sequence execution memory 4 which is a pulse sequence generation circuit.
It has a function of completely disconnecting a and 4b, the time register 7 and the state register 6 from the MPU 1. The judgment of these switching conditions is made based on the contents of the decoding and control in the instruction decoding / control circuit 8.

In the pulse sequence execution memories 4a and 4b, as shown in FIG. 2, a program code consisting of 32-bit state data and 32-bit time data is sequentially stored. Now, when each of these pairs is called a t-state, each t-state is ordered by addresses A, A + 1, A + 2, ... And the output state (state) of a certain time is determined by the state data and the time data. ) And time width (time). Therefore, by advancing the addresses of the pulse sequence execution memories 4a and 4b, the state data is held in the state register 6 and the time data is held in the time register 7, and the pulse sequence is shown in FIG.
Is generated like. At this time, the address sequencer 5
Switches the two sequence execution memories 4a and 4b and controls the address. In order to control this pulse sequence, 2 bits in the state are used as instruction bits. The instruction bit includes, for example, “STATE”,
Four instructions, "LOOP", "JNZ", and "JMP" are prepared. "STAT
"E" is used as an instruction for determining the time and output state, "LOOP", "JNZ" is used as an instruction for controlling the loop of the pulse sequence, and "JMP" is used as an unconditionally jumping instruction. It Therefore,
At times other than "STATE", t = 0 is selected.
Thus, a pulse sequence is created using these four instructions. Also, "STATE"
One bit of the instruction is "IRT" described later.
Used as a bit. These are decoded in the instruction decoding / control circuit 8, and the instruction decoding / control circuit 8 interrupts the CPU 1 according to the contents. Note that OBS shown in FIG. 3 means observation, and in GATE, a pulse generation step for exciting a nuclear spin for observation is designated, and RC
V indicates the step of observation, and ph indicates the pulse phase using 2 bits. In the case of the example shown in the figure, it is 90 ° in the step of A + 1 and 270 ° in the step of A + 3.

Next, the operation of the pulse programmer having the double memory structure according to the present invention will be described with reference to FIGS. First, before starting the sequence execution memories 4a and 4b
Stores program data of exactly the same sequence cycle. At the same time, different state variables or time variables are prepared in advance in the conversion table of the memory 3 for each cycle of the pulse sequence. Therefore, when the programmer is started, the program data in the sequence execution memory 4a is read by the address control of the address sequencer 5 and the state data is transferred to the state register 6
Then, the time data is held in the time register 7. Then, the state data held in the state register 6 is output through the buffer 10. The timing logic 9 counts the basic clock according to the time data held in the time register 7, and notifies the instruction decoding / control circuit 8 of the time information.
The instruction decoding / control circuit 8 decodes the state data (or the instruction bit of the sequence execution memories 4a and 4b) held in the state register 6, and in the case of the "STATE" instruction,
The "IRT" bit is checked, the time information from the timing logic 9 is monitored, and a control signal to the address sequencer 5 and an interrupt signal to the MPU 1 are issued. In the case of an instruction other than "STATE", a control signal to the address sequencer 5 is issued according to the content. The address sequencer 5 performs address updating, jumping and other address control according to the control signal from the instruction decoding / control circuit 8. For example, in the timing logic 9, the time data is set as a count value, this is counted down by the basic clock, and the instruction decoding / control circuit 8 sends a control signal for updating the address to the address sequencer 5 at "0".

As mentioned above, one bit of the "STATE" instruction is used as the "IRT" bit to MPU1 and the first "S" of one cycle of the pulse sequence.
The "IRT" bit of the "TATE" instruction is always set. Therefore, when this instruction is executed, an interrupt occurs in MPU1. MP
When U1 receives this interrupt, it executes the interrupt processing program and transfers only its variable portion from the table of the memory 3 to one of the sequence execution memories which is not used for generating the pulse sequence. Therefore,
This transfer is performed in parallel with the generation of the pulse sequence by the other sequence execution memory.
When the "STATE" instruction with the "T" bit set is executed, it starts at that instant and is done by the cycle steal to the sequence execution memory by MPU1. This control is performed by the gate 11. That is, after the “STATE” instruction is set in the state register 6 and the time register 7, the gate 11 is opened, and the MPU 1 interrupts the cycle steal before n counts when the count value of the timing logic 9 reaches “0”. Generate a signal. During this n count, the MPU 1 completes the instruction being executed, interrupts the transfer, and passes control to the sequence execution memory. By thus setting (turning on) the "IRT" bit in the first state of the pulse sequence, the generation of the pulse sequence by one of the sequence execution memories is started, and at the same time, the variable transfer to the other is started. As a result, the two sequence execution memories are alternately repeated by the above-described method, and as shown in FIG.
A pulse sequence can be generated infinitely while continuously changing the state or time variable alternately as →→ …….

As described above, the first "STA" of the pulse sequence
If the "IRT" bit of the "TE" instruction is set, the variable transfer to the other sequence execution memory is started immediately after the sequence execution is started, but the last "STATE" instruction of the pulse sequence " The "RTT" bit may be set. In this case, both of the sequence execution memories have been transferred before the sequence execution is started, and a variable is transferred to the sequence execution memory when the last "STATE" instruction of the first sequence execution memory is executed.

〔The invention's effect〕

As is clear from the above description, according to the present invention, MP
Since U receives an interrupt from the instruction decoding / control circuit and continuously supplies the variable part of the prepared pulse sequence code from the table storage memory to the sequence execution memory, it is possible to generate a pulse sequence with almost infinite steps. Becomes In addition, two sequence execution memories are prepared, and the sequence cycle is copied to each sequence execution memory in advance, and only the variable portion which is different for each cycle of the pulse sequence is alternately updated, and at the same time, the pulse sequence is stored in another sequence execution memory. As a result, the cycle repetition time can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining one embodiment of a pulse programmer having a double memory structure according to the present invention, FIG. 2 is a diagram for explaining the contents of a program code stored in a sequence execution memory, and FIG. FIG. 4 is a diagram for explaining the execution sequence of the program code shown in FIG. 2, FIG. 4 is a diagram for explaining the transfer processing of the program code, and FIG. 5 is a conventional pulse programmer for programmable generation of pulse sequences. FIG. 6 is a diagram for explaining an example of FIG. 1 ... MPU (microprocessor), 2 ... I / O interface, 3 ... Memory, 4a, 4b ... Sequence execution memory, 5 ... Address sequencer, 6 ... State register, 7 ... Time register, 8 ... Instruction decoding / control circuit, 9 ... Timing logic, 10 ... Buffer logic, 11 ... Gate.

Claims (4)

[Claims] 1. A pulse sequence code in which a program code consisting of output state and time width data is sequentially arranged is stored in a sequence execution memory, and a read address of the sequence execution memory is controlled to generate a plurality of pulse sequences. A programmable double-memory pulse programmer having a table for storing the updated contents of the variable portion of the pulse sequence code and two sequence execution memories for storing the pulse sequence code for each cycle, and according to the table A double memo characterized in that, while a pulse sequence is being generated by one sequence execution memory, the variable part of the other sequence execution memory is updated and two sequence execution memories are switched to generate a pulse sequence. Configuration of the pulse programmer. 2. A flag bit is provided in each program code of each sequence execution memory, the flag bit is checked when the program code is executed, and the variable part of the sequence execution memory is updated on condition that the flag bit is set. A pulse programmer having a double memory configuration according to claim 1, wherein the pulse programmer is implemented. 3. A double memory pulse programmer according to claim 2, wherein the flag bit of the first program code of each sequence execution memory is set. 4. The double memory pulse programmer according to claim 2, wherein the flag bit of the last program code of each sequence execution memory is set.