JPH02140805A - Sequence controller - Google Patents

Abstract

PURPOSE:To process a sequence edge instruction with one bit cpu by one step by storing instruction decoding and a data input in a result register at the raising time of a reference clock and a judgement result at the falling time of the reference clock. CONSTITUTION:At the raising time of the reference clock in a clock generator 6, a data signal from I/O 7 is inputted to the (a) terminal of a rising element 14 as address bit data through an I/O bit selector 8. On the other hand, a data signal from an I/O memory 4 is latched by a memory data/bit selector 9 and is inputted to the (b) terminal of the rising element 14 as one bit data. At the falling time of the reference clock, the output of the element 14 is written into the result register 12 of one bit cpu 1, the data from I/O 7 is stored in the I/O memory 4 through a memory buffer 16. Thus, the sequence edge instruction can be performed without shifting a control right to a multi bit micro computer 2 with one bit cpu 1 by one step.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a sequence controller that combines a 1-bit Qpu and a multi-bit microcomputer.

(Prior Art) In general, a sequence controller (hereinafter simply referred to as a controller) configured with a 1-bit CPU can process basic instructions in one step, but it cannot process judgment processes that involve storage, such as arithmetic instructions or edge instructions. Have difficulty. on the other hand,
In a controller configured with a multi-bit microcomputer (hereinafter abbreviated as M-microcomputer), one step of executing a sequence instruction takes several times the processing time of the 1-bit Qpu, so recently both of the above are being used. Controllers have been proposed that combine the best of both worlds.

FIG. 5 is a block diagram showing a conventional example of such a controller, which includes a 1-bit Apul input section and an 8-bit microcontroller 2.
An I/O memory 4 of 8 bits per word is provided between the data bus 3 and the sequence program stored in the program memory 5 is read out in synchronization with the reference clock of the clock generator 6. Decoding the instructions sequentially.

As a result, the input-related basic commands, as shown in FIG.
In addition, basic commands related to output are l/O7 as shown in Figure 7.
Application instructions that output data to the I/O memory 4, update data in the I/O memory 4, and perform judgment processing involving storage such as arithmetic processing or edge instructions, as shown in Figure 8, are applied instructions. Control authority over the /O7 and I/O memory 4 is transferred from the 1-bit cpul to the 8-bit microcomputer 2, and as a result, input-related application instructions are transferred to the 8-bit microcomputer 2.
reads data from the I/O 7 and updates data in the I/O memory 4.

At this time, the 8-bit microcomputer 2 performs several steps to several tens of steps for instruction processing and reading and storage processing of the I/O memory 4.

(Problem to be Solved by the Invention) Therefore, conventionally, execution of a sequence application instruction involves the steps of transferring control from the 1-bit CPU to the 8-bit microcomputer 2, the step of the 8-bit microcomputer 2 processing the sequence instruction, and The processing time for the step of reading and updating data in the I/O memory 4 is 1 bit c.
This method has the disadvantage that it takes several times as much processing time as pul's one-step processing.

The present invention aims to provide a controller that eliminates the above-mentioned drawbacks. An I/O memory that stores the I/O status and a memory data bit selector that specifies and latches bits of output data from the I/O memory are provided on the input part of the bit Qpu and the data bus of the microcontroller; I/O that specifies bits of data from /O.
O data bit selector, its output data and the output data of the memory data bit selector.

A logic element that performs edge determination is provided, and at the rising edge of the reference clock, the I/O data at the address specified by the sequence edge instruction code is read, and the data at the address corresponding to the predetermined address of the E/O memory is read out, and the reference clock is read out. At the falling edge of the clock, the logic element performs an edge judgment between the latched I/O memory data and the I/O data, and at the rising edge of the next reference clock, the judgment result is transferred to the 1-bit Qpu output register. This is achieved by a configuration that updates data in the I/O memory at the same time as writing.

(Operation) According to the present invention configured as described above, when the sequence application instruction is a sequence edge instruction that is a judgment process, 1
The bit CPU does not transfer control to the M/microcontroller,
Instruction decoding and data input are performed at the rising edge of the reference clock.
Also, since the judgment result is stored in the result register and the data in the I/O memory is updated at the falling edge of the reference clock, the sequence edge instruction can be executed by 1-bit CPU.
It becomes possible to perform processing in one step.

(Embodiment) FIG. 1 shows the configuration of a controller according to an embodiment of the present invention, and the same reference numerals as in the previous times refer to those with the same or identical functions.

Between the input part of the 1-bit cpul and the 8-bit microcomputer 2, there is an 8-bit signal input from the E/O 7 whose address is specified by the program memory 5 in which the instruction code is stored.
An I/O bit selector 8 that specifies the bit data, an I/O memory 4 that stores the state of the l/O 7, and a bit specifier for the 8 bits of the address corresponding to the predetermined address that will be output from now on. A memory data/bit selector 9 that performs latching, and these I/O bit selectors 8. A logic element /O that compares the output of the memory data bit selector 9 and a logic element /O that compares the output of the memory data bit selector 9 and a logic element /O that compares the output of the memory data bit selector 9.
A logic selector 11 for selecting O is provided.

Using the reference clock from the 1-bit cpul and the clock generator 6 of the 8-bit microcomputer 2, the timing controller 13 controls read/write of the I/O memory 4 and sends a write pulse to the internal output register 12 of the 1-bit cpu1. supply

FIG. 2 shows a sequence program code, and FIG. 3 shows an operation timing chart, and the following description will be made with reference to these.

First, at the rising edge of the reference clock of the clock generator 6 (FIG. 3(a)), the program memory 5 as shown in FIG. When the command is the first
The logic selector 11 shown in the figure selects the rising element 14 of the logic element /O, and also selects the data of I/O7 having the address specified by the instruction code a [(Q), (d) in the same figure]. Similarly, the bit designated by the instruction code a is selected by the I/O bit selector 8 and the memory data bit selector 9 and latched as shown in FIG.

The data signal from l/O7 is sent to I/O bit selector 8.
The signal is input as address bit data to the a terminal of the rising element 14 via the address bit data.

On the other hand, the data signal from the I/O memory 4 [(h) in the same figure] which is synchronized with the signal from the timing controller 13 [(f) in the same figure] is latched by the memory data bit selector 9 [(f) in the same figure]. j)] is input to the b terminal of the rising element 14 as 1-bit data. In addition, I/
The rising of O data means that the data changes from O to 1 as shown in FIG.
When the b terminal of the terminal is O and the a terminal is 1, 1 is output to the output terminal C [FIG. 6(j)]. This output is written into the 1-bit cpul register 12 at the falling edge of the reference clock from the clock generator 6 [(a) in the same figure] and into the output register 12 [(k) in the same figure].

At this time, the data from l/O7 is stored in the memory buffer 16.
The signal is input to the I/O memory 4 via the timing controller 13 and written to the I/O memory 4 at the falling edge of the reference clock in synchronization with the signal from the timing controller 13 [Fig. 3 (g)
).

According to the present invention, as shown in FIG. 3, the rising edge of the reference clock a is determined based on the data from the l/O 7 and the I/O memory 4 at the falling edge of the reference clock a, as shown in FIG.

Since the judgment result is written to the output register 12 and the data of l/O7 is stored in the I/O memory 4 at the falling edge of the reference clock, the sequence edge command can be executed in one bit without transferring control to the M/microcontroller. Just as cpul processes sequence basic instructions, it can be processed in one step.

(Effects of the Invention) As is clear from the detailed explanation above, the present invention provides that when the sequence application instruction is a sequence edge instruction that involves judgment processing that involves storage, the 1-bit Qpu transfers the control right to the M/microcontroller. Instead, instructions are decoded and data is input at the rising edge of the reference clock.

Since the determination result is stored in the result register and the data in the I/O memory is updated at the fall of the reference clock, sequence edge instructions can be processed in 1-bit cpul steps.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of an embodiment of the present invention, Fig. 2 is a sequence program code diagram, Fig. 3 is a timing chart, and Fig. 4 shows the logic elements and truth values of the main part of the present invention. FIG. 5 is a circuit block diagram of the conventional example, FIG. 6 is a basic instruction processing diagram related to input, FIG. 7 is a basic instruction processing diagram related to output, and FIG. 8 is an applied instruction processing diagram of the conventional example. . 1... 1-bit Qpu, 2... 8-bit microcomputer, 3... Data bus, 4... I/O memory, 5... Program memory, 6... Clock generator, 7... I,/Ol 8...
I/O bit selector, 9... Memory data bit selector, /O... Logic element, 11... Logic selector, 12... Result register, 13
...Timing controller, l4...Rise element, 15...Fall element. 16...Memory buffer.

Claims (1)

[Claims] In a sequence controller that combines a 1-bit CPU and a multi-bit microcontroller, an I/O memory that stores the I/O status and an output from the I/O memory are connected to the input section of the 1-bit CPU and the data bus of the microcontroller. A memory data bit selector that specifies and latches data bits, an I/O data bit selector that specifies bits of data from I/O, and the output data of the memory data bit selector and the output data of the memory data bit selector. A logic element that performs edge determination is provided, and the I/O of the address specified by the sequence edge instruction code is determined at the rising edge of the reference clock.
O data is read, and data at an address corresponding to the predetermined address of the I/O memory is read, and an edge determination between the latched I/O memory data and the I/O data is performed at the falling edge of the reference clock. A sequence controller characterized in that the logic element is used to write the determination result into a 1-bit CPU result register at the next rising edge of a reference clock, and at the same time update data in an I/O memory.