JP2764024B2 - Storage device table indexing method and indexing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for indexing a table in a storage device, and more particularly to a method and an apparatus for indexing a table in a storage device applied to a pipeline.

[0002]

2. Description of the Related Art In microcontrol performed by a microcontroller, normally used data, for example, numerical values for conversion and index data are read-only memory (RO).
M) and the transfer table is erected. The general hardware implementation device and implementation method will be described with reference to FIG. 2 showing the relationship between the structure of the table index portion of the conventional microcontroller and the table index operation. In FIG. 2, the microcontroller 10 includes a storage device 11 (for example, ROM), a program counter 12, an index register 13, a multiplexer 14, a data register 15, a control device 16, and a command decode execution device 17. The storage device 11 includes a command data storage section 111 and a table index data storage section 112.

In the command data storage section 111 and the table index data storage section 112, symbols PC and m are values included in the program counter 12 and the index register 13, respectively, and the addresses PC and
represents m. The code PC + 1 is obtained by adding 1 to the content value PC of the program counter 12 and represents the address PC + 1 of the storage device 11. And the sign (P
C), (PC + 1), and (m) are the values contained in the memory at addresses PC, PC + 1, and m of the storage device 11, respectively. It should be noted here that, in the present application, the code (PC),
(PC + 1) indicates a table index command and a subcommand in the command data storage section 111, respectively, and the symbol (m) indicates table index data stored in the table index data storage section 112.

[0004] A program of the second indexing work applied to FIG. 2 will be described. Step (a)-In response to the multiplexer control signal C ₁ , the memory enable signal E and the content PC of the program counter 12 generated by the controller 16 and in the first multiplexer control state, the storage device 11 issues the command. A table index command (P
After C) is output to the command decode execution device 17, the command is decoded by the command decode execution device 17, and the obtained table index signal L is output to start the table index program.

Step (b): At this time, the control device 16 generates the multiplexer control signal C ₁ in the second multiplexer control state according to the table index signal L and outputs the generated signal to the multiplexer 14 to indicate the index. The content m of the register 13 is stored in the table index data storage section 112.
And output.

Step (c) —Memory enable signal E
With table index data (m) is output from the storage device 11, the table index data in the data register 15 in response to the write signal C ₂ which is generated by the controller 16 (m) are stored in accordance with the.

Step (d)-If the table index signal L is not input to the control unit 16, the control unit 16 again generates a multiplexer control signal C1 in the _first multiplexer control state, and Is output to the program counter 1
The value PC + 1 after adding 1 to the content value PC of 4 is output to the command data storage section 111 and output to the sub-command (P
C + 1) and bind the table look-up program.

In the above table look-up program, switching between the program counter 12 and the contents included in the index register 13 must be performed in order to read data in the non-uniform address sections of the storage device 11. With the pipeline structure, the data reading operation takes an enormous amount of time, and further improvement is expected.

The pipeline structure is, as shown in the relationship between the operation of the pipeline of the microcontroller and the structure in FIG.
, A program counter 22, a command buffer 23,
This means a structure represented as the microcontroller 20 by the command register 24 and the command decode execution device 25.

FIG. 3B is a schematic diagram in which the extraction timing cycle FC and the execution timing cycle EC overlap each other to execute a pipeline operation. In the figure, n is a value contained in the program counter 22 used as an address of the storage device 21, (n) is a value contained in the address n in the storage device 21 (for example, a command), and T _{O to} T ₂ are timing periods T _{O to} T 2. ₂

The pipeline structure will be described in more detail with reference to FIGS. 3 (a) and 3 (b). At the timing cycle T _O , the extraction cycle EC period—the address n of the storage device 21 is output from the program counter 22 to read out the contents included in the address n: the command (n) comes to the command buffer 23.

In the timing cycle T ₁ , (1) the execution cycle EC period—the command (n) in the command buffer 23 is output to the command register 24, and is used for decoding and execution by the command decode execution device 25.

(2) Retrieval period FC period-addition of 1 to the value n contained in the program counter 22, the program counter 22 outputs the address n + 1 of the storage device 21, and reads the value contained in the address n + 1 of the storage device 21. : Command (n + 1) comes to command buffer 23.

In the timing cycle T ₂ , (1) the execution cycle EC period—the command (n + 1) in the command buffer 23 is output to the command register 24 to be used by the command decode execution device 25 for decoding and execution.

(2) Retrieval period FC period-addition of 1 to the content value n + 1 in the program counter 22, the address n + 2 of the storage device 21 is output from the program counter 22, and the content value in the address n + 2 of the storage device 21 is read. :
The command (n + 2) comes to the command buffer 23.

The above operation is repeated until the execution of the command stored in the storage device 21 is completed. Next, the structure of a two-layer pipeline is taken as an example. FIG. 4A is an exemplary diagram showing the relationship between the structure of the microcontroller table index portion and the table indexing operation in the conventional two-layer pipeline operation. In FIG. 4A, the microcontroller 30
Is a storage device 31 (for example, ROM), a program counter 32, an index register 33, a multiplexer 34,
It comprises a data register 35, a control device 36, a command buffer 38, and a command decode execution device 39, and the storage device 31 includes a command storage section 311 and a table index data storage section 312.

Symbols PC and m are the contents included in the program counter 32 and the command register 33, respectively, and are the addresses PC and m of the storage device, respectively. Also, the code PC
+1 and PC + 2 are the contents PC of the program counter 32
And 1 + 2, and the addresses PC + 1 and PC + 2 of the storage device 31. Also, (P
(C), (PC + 1), (PC + 2) and (m) are the values contained in the memory at the addresses PC, PC + 1, PC + 2 and m of the storage device 31, respectively. Similarly, reference numeral (PC) in the present application
And (PC + 1) mean the table index command and the subcommand stored in the command data storage section 311, respectively, and the symbol (m) means the table index data stored in the table index data storage section 312. I do.

FIG. 4B is a view showing an example of the timing of a microcontroller in a conventional pipeline operation. In FIG. 4B, reference numeral FC denotes an extraction period, and reference numeral EC denotes an execution period.

Here, the structure of FIG. 4A applied to the program for the table look-up operation will be described with reference to a timing diagram of the microcontroller shown in FIG. 4B.

In the timing period T _O , the fetch period FC period—generated by the controller 36 and according to the multiplexer control signal C ₁ , the memory enable signal E and the content PC of the program counter 32 in the first multi-control state. Then, the table index command (PC) is output from the command data storage section 311 to the command buffer 37 by the storage device 31.

In the timing cycle T ₁ , (1) execution cycle EC period—table index command (PC) in the command buffer 37 is output to the command register 38, and then the table index command (PC) is read from the command register by the command decode execution device 39. ) Is read and executed to generate and output a table index signal L.

(2) Extraction period FC period—the multiplexer control signal C ₁ in the first multiplexer control state,
In accordance with the memory enable signal and PC + 1 obtained by adding 1 to the content value PC of the program counter 32, the storage device 3
1, the sub-command (P
C + 1) is output to the command buffer 37.

[0023] In the timing period T ₂ (1) run periodic EC period - to hold the non-operation (NOP) state. (2) extraction period FC period - in accordance with the table index signal L by the controller 36, the multiplexer 3 multiplexer control signal C ₁ at the second multi-control condition occurs
4, the content m of the index register 33 is switched to the storage device 31 and output. At this time, by outputting the table index data (m) stored in the table index data section 312 from the storage device 31 to the command buffer 37 in response to the memory enable signal E, the take-out period FC of the original timing period T ₁ The sub-command (PC + 1) stored in the command buffer 37 is interrupted.

[0024]In timing the period T ₃  (1) Execution period EC period-text in the command buffer 37
The index data (m) is transmitted through the index register 38,
Write signal C generated by controller 36 _TwoRespond to
Is output to the data register 35 and the table lookup operation is performed.
Be completed.

(2) Removal cycle FC period—control device 36
Again generates a multiplexer control signal C _{1 in} the first multiplexer control state,
, The content value PC + 1 of the program counter 32 is output to the storage device 31, and the storage device 31 sends the subcommand (PC + 1) again from the command data storage section 31 in response to the memory enable signal E. Is output to the command buffer 37. The sub command stored in the command buffer 37 to the original take-out period FC duration of the timing period T ₁ (PC + ₁₎ is the timing period T ₂
, The value included in the program counter 32 at this time is still held at PC + 1.

The timing period T in ₄ (1) run periodic EC period - after outputting the subcommand (PC + 1) to the command register 38 in the instruction buffer 37, reads the sub-command (PC + 1) from the command register 38 by a command execution unit 39 Run.

(2) Take-out cycle FC period—instruction data from the storage device according to the multiplexer signal C ₁ in the first multiplexer control state, the memory enable signal E, and PC + 2 added to the content value PC + 1 of the program counter 32 The command (PC + 2) is output from the storage section 311 to the command buffer 37.

[0028]

In short, the controller 30 having the above-mentioned conventional two-layer pipeline structure performs the table indexing operation (after generating the table index signal L, the table index data (m) is stored in the data register 35). In order to complete the operation up to the input to the clock, three timing periods (T ₁₎
ＴT ₃ ), and the operation for reading the subcommand (PC + 1) is wasted in advance even with only one timing period among them, and the operation efficiency of the command buffer 37 is reduced. If the pipeline structure has three or more layers, the time wasted in the timing cycle is not a change in the linearity scheme, but a much larger non-linearity is expected. As a result, the working efficiency of the controller 30 is increased. Reduced to width.

A main object of the present invention is to provide a table indexing method for a storage device which can be applied to a pipeline structure and can reduce a table indexing time. A second object of the present invention is to provide a low-cost storage device table indexing device without significantly changing the conventional microcontroller.

[0030]

According to a first aspect of the present invention, there is provided a table indexing method for a storage device, comprising: a command buffer executing device, a control device, and a data register; In a table indexing method for outputting table index data to a data register, (a) in a first timing cycle, a table index command stored in advance by the command buffer executing device is executed to generate and output a table index signal. After that, the controller outputs the subcommand stored in the storage device to the command buffer execution device according to the table index signal,
(B) in the second timing period, after the control device generates a use prohibition signal and latches the subcommand in the command buffer execution device, a write command is generated in the control device and the command is transmitted to the command buffer. A table indexing method for a storage device, comprising the step of: outputting a table index data to the data register by generating a write signal in the command buffer executing unit by outputting the command index to the execution unit.

Preferably, the storage device includes a command data storage section and a table index data storage section. Preferably, both the table index command and the subcommand in the step (a) are stored in the command data storage section, and the table index data is stored in the table index data storage section.

Preferably, before the step (a), the control device outputs the table index command in the command data storage section to the command buffer execution device according to a program command count value. Step (c) is provided for executing the leverage command buffer execution device.

Preferably, the program command count value is used as an address of a command stored in the command data storage section. Preferably, the step (b) further, (b ₁₎ by using the disable signal generated output by the controller latches the subcommand located at the command buffer execution device, (b ₂₎ Outputting the table index data in the storage device to the data bus in accordance with the index value of the table index data, and (b ₃ ) the write command being generated by the control device and output to the command buffer execution device, Causing the command buffer execution device to execute the write command; and (b ₄ ) outputting the write signal from the command buffer execution device to the data register, whereby the table index data located on the data bus is updated. A step of inputting to the data register.

Preferably, in the step (b ₂ ),
An index value is stored in the index register according to the index value of the table index data. Preferably, the command buffer execution device includes a command buffer, a command register, and a command decode execution device.

Preferably, the command buffer latches the subcommand therein in response to the use prohibition signal. Preferably, the command register inputs and stores a write command generated and output by the control device.

Preferably, the command decode execution device sequentially decodes the table index command, write command and subcommand from the command register. A table indexing device for a storage device according to another invention of the present application has a table indexing command, a subcommand, and table indexing data, and stores the table indexing command, the subcommand, and the table indexing data in response to an index address control signal. A storage device for sequentially outputting, and a command that is electrically connected to the storage device and that generates a table index signal output when executing the table index command after the table index command and the subcommand are input from the storage device. A buffer execution device;
The index buffer control device is electrically connected to the command buffer execution device and the storage device, and the index address control signal is generated and output in response to the table index signal, thereby causing the storage device to output the table index data. When a use prohibition signal and a write command are generated and output to the command buffer execution device, the command buffer execution device latches the subcommand when the subcommand is input, and simultaneously responds to the write command. A control device that outputs the generated write signal, and a data register that is electrically connected to the storage device and the command buffer execution device, and that receives the table index data from the storage device according to the write signal. Become.

Preferably, the storage device is a read-only storage device (ROM). Preferably, the command buffer execution device is electrically connected to the storage device and the control device, and the table index command and the subcommand are sequentially input from the storage device, and the subcommand is input when the subcommand is input. A command buffer for latching the subcommand in response to a use prohibition signal, and the command buffer execution device, which is electrically connected to a control device and a data register, the table signal is generated when the table index command is executed. A command execution device that is output to the control device and executes the write command to generate the write signal and output the signal to the data register.

Preferably, the command execution device is electrically connected to the command buffer and the control device to sequentially store the table index command and the subcommand, and receives the write command from the control device. Command register, and by being electrically connected to the command register and the control device, by executing the table index command and the write command input from the command register, respectively, the table index signal and the A command decode execution device for generating a write signal and outputting the write signal to the control device.

Preferably, the table index device of the storage device further stores a program counter for storing the table index command and the subcommand at a storage address of the storage device, and stores the table index data at a storage address of the storage device. An index register to be executed and the program counter, the index register, a control device, and a storage device are electrically connected to each other, so that the program counter or the index register can be read in accordance with a multiplexer control signal output from the control device. A multiplexer for sequentially outputting the table index command, the subcommand, and the table index data to the storage device by sequentially using the included values as the index address control signal.

Preferably, the control device outputs the multiplexer control state in the first multiplexer control state when the table index signal is not input, and controls the contents contained in the program counter to the index address control. By using the signal as a signal, the storage device causes the table index command or the subcommand to be output, and when the table index signal is input to the control device, the multi control signal is By using the value contained in the index register as the index address control signal in the multiplexer control state of 2, the memory is stored and the table index data is output.

Preferably, the first and second multiplexer control states are a high level and a low level, respectively. Preferably, the first and second multiplexer control states are low and high, respectively.

Preferably, the table look-up device of the storage device is further electrically connected to the storage device, the command buffer execution device, the data register and the control device, so that the demultiplexer signal output from the control device is provided. And a demultiplexer for outputting the table index command and the next command to the command buffer execution device in accordance with the above, or outputting the table index data to the data register.

Preferably, the control device outputs the demultiplexer control signal in the first demultiplexer control state when the table index signal is not input, and outputs the table index command and the next command. When the table index data is input to the control device, the demultiplexer signal is in a second demultiplexer control state, and the table index data is output to the command buffer execution device. Output to data register.

Preferably, the first and second demultiplexer control states are a high level and a low level, respectively. Preferably, the first and second demultiplexer control states are a low level state and a high level state, respectively.

Preferably, the storage device has a command data storage section for storing the table index command and the next command.
A table index data storage section for storing the table index data.

[0046]

The microcontroller of the present invention comprises a storage device such as a ROM, a control device, a data register, a command buffer executing device, a program counter, an index register,
Comprising a multiplexer 47 and a data register, the command buffer execution device comprising a command buffer, a command execution device having a command register and a command decode execution device, and a storage device comprising a command data storage section;
Since the table index data storage section is provided, the table index operation requires only two timing periods, and even if the pipeline structure is changed to three or more layers, the required period is the same as the conventional one. 4A and 4B, the period is much shorter than that required, and the working efficiency of the microcontroller can be greatly improved.

According to the present invention, the table index data (m) is output according to the table index command (PC) and stored at the address m in the storage device, and the contents PC, PC + 1, PC + 2, etc. of the program counter are controlled by the index address. Since it can be used as the signal P, the index register and the multiplexer can be saved.

Further, according to the present invention, since the index address control signal P can be output by the control device, the program counter can be further saved.

[0049]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a block diagram showing a preferred embodiment of the present invention. In FIG. 1A, the microcontroller 40 includes a storage device 41 (for example, R
OM), a control device 42, a data register 43, a command buffer execution device 44, a program counter 45, an index register 46, a multiplexer 47, and a data register 48. The command buffer execution device 44 includes a command buffer 441, a command register 4421, and a command execution device 442 including a command decode execution device 4422.
The storage device 41 includes a command data storage section 411 and a table index data storage section 412.

Symbols PC and m are values included in the program counter 45 and the index register 46, and are addresses PC and m of the storage device 41, respectively. The sign PC +
1 and PC + 2 are obtained by adding 1 and 2 to the content value PC of the program counter 45, and are addresses PC + 1 and PC + 2 of the storage device 41. Reference numerals (PC), (PC + 1), (PC + 2) and (m) denote addresses PC, PC + 1, PC + 2 of the storage device 41, respectively.
m in memory, where the codes (PC) and (P
C + 1) indicates the table index command and the subcommand stored in the command data storage section 411, respectively, and the symbol (m) indicates the table index data storage section 412.
Means the table index data stored in the.

FIG. 1B is a timing chart of a preferred embodiment of the present invention.
C is an execution cycle. Here, the structure of FIG. 1A applied to the program for the table look-up operation will be described with reference to a timing diagram of the microcontroller shown in FIG. 1B.

The take-out period FC in the timing period T _O --the multiplexer control signal C _{1 first} generated by the controller 42 and in the first multiplexer control state, the multiplexer control signal C in the first demultiplexer control state _{2. In} accordance with the contents PC of the program counter 45 used as the memory enable signal E and the index address control signal P, the storage device 41 sends a table index command (PC) from the command data storage section 411 to the command buffer 441. Output.

In the timing cycle T ₁ , (1) execution period EC period—table index command (PC) in the command buffer 441 is output to the command register 4421, and then, the command decode execution unit 4422 outputs the table index command (PC) from the command register 4421. ) Is read and executed to generate and output a table index signal L.

(2) Extraction period FC period—the multiplexer control signal C ₁ in the first multiplexer control state,
In response to the multiplexer control signal C ₂ in the first demultiplexer control state, the memory enable signal E, and the PC + 1 obtained by adding 1 to the value PC included in the program counter 45, the storage device 41 causes the command data storage section 41 to store the command data.
Subcommand (PC + 1) from 1 to command buffer 441
Output to

In the timing cycle T ₂ , (1) execution cycle EC period—a use prohibition signal X is generated by the control device 42, and is output to the command buffer 441 to latch a subcommand. A write signal I is generated and transmitted to the command register 4
421, and the command decode execution device 4422 reads and executes the write command I in the command register 4421, thereby generating a write signal W and causing the data register 4
By outputting to 3, the input data of the data register 48 the data bus (i.e., the table index data output to the data bus D to the take-out period FC period at timing period T ₂ (m)) to them Let me know. (Refer to the part (B) in FIG. 7B.) (2) Take-out period FC period—The multiplexer 42 controls the multiplexer control signal L _{1 in} the second multiplexer control state according to the table index signal L by the controller 42. The index register 6 used as the index address control signal P is generated and output to the multiplexer 47, and the multiplexer signal C2 in the _second demultiplexer control state is generated and output to the demultiplexer 48. Is switched to the storage device 41 and the table index data (m) stored in the table index data storage section 412 is output to the data bus D by the storage device in response to the memory enable signal E. I do. (It has been referring to the code (A) portion in FIG. 1 (b)) (1) run periodic EC period at timing period T ₃ - command subcommand latched in the command buffer 441 (PC + 1) register 442
After that, the subcommand (PC +
1) is read and executed.

(2) Removal cycle FC period—Control device 42
Again in the first multiplexer state.
Lexer control signal C₁Is generated and output to the multiplexer 47.
And again in the first demulti control state
Demultiplexer control signal C _TwoMultiplex
Output from the program counter 45 and
The storage device 4 adds 1 to the included value PC + 1 to obtain PC + 2.
1 to the storage device 41
In response to the enable signal E, the command data storage section 41
1 outputs the command (PC + 2) to the command buffer 441.
I will force you.

[0057]

Therefore, in the microcontroller 40 applied to the two-layer pipeline structure of the present invention,
The table look-up operation (ie, the operation from the generation of the table look-up signal L to the input of the table look-up data (m) to the data register 48) is only two timing periods (ie, T ₁ , T ₂ ). Even if the pipeline structure is changed to three or more layers, the required period is much shorter than the required period of those shown in FIGS. The working efficiency of the controller can be greatly improved.

According to the present invention, table index data (m) is output by a table index command (PC) and stored at an address m in the storage device, and the contents PC, PC + 1, PC + 2, etc. of the program counter 45 are indexed. Since it can be used as the address control signal P, the index register 4
6 and the multiplexer 47 can be saved.

In the present invention, since the index address control signal P can be output by the control device 42, the program counter 45 can be further saved. In the present invention, the output terminal of the command data storage section 411 can be electrically connected to the command buffer 441.
Since the twelve output terminals can be electrically connected to the data register 48, the demultiplexer 48 can be saved.

When the number of bits of the contents included in the storage device 41 is larger than the number of bits of the data bus D, another data register can be added to store bits outside the frame. In short, the present invention provides a low-cost table indexing method and indexing device for a storage device without significantly changing the composition of a conventional microcontroller, and can be applied to a pipeline to reduce the time required for table indexing. Extremely high industrial utility value.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating the structure and timing of a preferred embodiment of the present invention.

FIG. 2 is an exemplary diagram showing a relationship between the structure of a conventional microcontroller table index portion and a table indexing operation.

FIGS. 3A and 3B are exemplary diagrams showing the relationship between a pipeline operation structure of a microcontroller, operations, and timings.

FIGS. 4A and 4B are illustrations showing the relationship and timing between the structure of a microcontroller part of a conventional two-layer pipeline and a table look-up operation.

[Explanation of symbols]

 41 storage device 42 control device 43,48 data register 44 command buffer execution device 45 program counter 46 index register 47 multiplexer 411 command data storage section 412 table index data storage section 441 command buffer 442 command execution device 4421 command register 4422 command buffer Execution device

Claims (11)

(57) [Claims] 1. A table indexing method for outputting table index data stored in a storage device to a data register using a command buffer execution device, a control device, and a data register, comprising: (a) a first timing period; In the above, after executing the table indexing command stored in advance by the command buffer executing device to generate and output the table indexing signal, the controller stores the sub index stored in the storage device in accordance with the table indexing signal. Outputting a command to the command buffer execution device; (b) in the second timing period, after the control device generates a use prohibition signal and latches the subcommand in the command buffer execution device, A write command is generated and output to the command buffer execution device, thereby writing the command buffer execution device. Table look method of a storage device which signal is generated consisting comprises a step of outputting the table data to the data register. 2. The storage device comprises a command data storage section and a table index data storage section, and both the table index command and the subcommand in the step (a) are stored in the command data storage section. The table index data is stored in the index data storage section, and before the step (a), further, (c) the control device controls the command data storage section in accordance with a program command count value. 2. The table indexing method for a storage device according to claim 1, wherein the table indexing command in a stage is output to the command buffer executing device and used for execution of the command buffer executing device. Wherein said step (b) further, (b ₁₎ by using the disable signal generated output by the controller latches the subcommand located at the command buffer execution device, (b ₂ (B) outputting the table index data in the storage device to the data bus in accordance with the index value of the table index data, and (b ₃ ) generating the write command from the control device and outputting it to the command buffer execution device. And causing the command buffer execution device to execute the write command. (B ₄ ) By outputting the write signal from the command buffer execution device to the data register, the table index data located on the data bus is Inputting the data to the data register;
_2. The table indexing method according to claim 1, wherein in step ₂ ), an index value is stored in an index register based on the index value of the table index data. 4. The command buffer execution device includes a command buffer, a command register, and a command decode execution device, wherein the command buffer stores the subcommand in response to the use prohibition signal. Latch,
The command register inputs and stores a write command generated and output by the control device, and the command decode executing device sequentially decodes and executes the table index command, the write command, and the subcommand from the command register. 2. The table indexing method for a storage device according to claim 1. 5. The storage device according to claim 1, wherein the storage device is a read-only storage device (R).
2. The table indexing method for a storage device according to claim 1, wherein the table index is OM). 6. A storage device having a table index command, a subcommand, and table index data, and sequentially outputting the table index command, the subcommand, and the table index data in response to an index address control signal. A command buffer execution device that generates a table index signal when the table index command is executed after the table index command and the subcommand are input from the storage device, and the command buffer execution device and the storage device The index address control signal is generated and output in response to the table index signal, thereby causing the storage device to output the table data, and generating a use prohibition signal and a write command. Is output to the command buffer execution device, and the command is executed by the command buffer execution device. A control device that latches the subcommand when input, and simultaneously outputs a write signal generated according to the write command, and is electrically connected to the storage device and the command buffer execution device, and responds to the write signal. A data register to which the table index data is input from the storage device; 7. The read-only storage device (R)
OM). The table indexing device for a storage device according to claim 6, wherein 8. The command buffer execution device is electrically connected to the storage device and the control device, and sequentially receives the table index command and the subcommand from the storage device and receives the subcommand. A command buffer that latches the subcommand in response to the use prohibition signal, and is electrically connected to the command buffer execution device, the control device, and the data register, and the table signal is generated when the table index command is executed. And a command execution device that generates the write signal and outputs the write signal to the data register by executing the write command. Is electrically connected to the command buffer and the control device to sequentially record the table index command and the subcommand. Remember, a command register to which the write command is input from the control device, and by being electrically connected to the command register and the control device,
A command decode execution device that generates the table index signal and the write signal and outputs the generated signal to the control device by executing the table index command and the write command input from the command register. A table indexing device for a storage device according to claim 6. 9. The table indexing device of the storage device further stores a program counter for storing the table index command and the subcommand at a storage address of the storage device, and stores the table index data at a storage address of the storage device. By being electrically connected to the index register and the program counter, the index register, the control device, and the storage device, an index register is included in the program counter or the index register according to a multiplexer control signal output from the control device. By using a value in order as the index address control signal, the table index command, a subcommand and a multiplexer for sequentially outputting the table index data to the storage device, wherein the control device, When the table index signal is not input Outputting the multiplexer control state in the first multiplexer control state and using the contents contained in the program counter as the index address control signal, thereby causing the storage device to execute the table index command or the subcommand. When the table index signal is input to the control device, the multi control signal enters the second multiplexer control state, and the content of the index register is changed to the index address control signal. The first and second multiplexer control states are a high level and a low level state, or are a low level and a high level state, respectively, by storing the data and outputting the table index data. Item 7. A table indexing device for a storage device according to Item 6. 10. The table look-up device of the storage device is further electrically connected to the storage device, the command buffer execution device, the data register, and the control device so that a demultiplexer signal output from the control device can be obtained. And a demultiplexer that outputs the table index command and the next command to the command buffer execution device, or outputs the table index data to the data register,
The controller outputs the demultiplexer control signal in the first demultiplexer control state when the table index signal is not input, and outputs the table index command and the next command to the command buffer execution device. On the other hand, when the table index data is input to the control device, the demultiplexer signal enters the second demultiplexer control state, and the table index data is output to the data register. 7. The apparatus according to claim 6, wherein the first and second demultiplexer control states are a high level and a low level, or a low level and a high level, respectively. 11. The storage device according to claim 6, wherein the storage device comprises a command data storage section for storing the table index command and the next command, and a table index data storage section for storing the table index data. Table indexing device for storage devices.