JPH0713758A - Instruction decoding method - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an instruction decoding method capable of easily adding a new instruction to the same instruction code. [Structure] Instruction register 2 read from main memory 1
The decoding method of the instruction code stored in is switched by the instruction operation mode flag 5 of the program execution status register 4 to generate different microprogram addresses stored in the RAM 7 for the same instruction code, and the execution unit 9
Configured to run. [Effect] By providing a flag for instructing an instruction decoding method, different microprogram execution start addresses can be generated for the same instruction code, and a new function is added without newly adding an instruction code in the existing instruction code system. You can easily add instructions with.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction decoding method for a microprogram in an information processing apparatus, and more particularly to an instruction decoding method capable of executing a large number of microprograms even with a small number of instruction codes.

[0002]

2. Description of the Related Art Generally, an information processing apparatus generates an address of a microprogram read from a storage means such as a RAM by an instruction decoding unit decoding an instruction code instructed by a higher-order device, and reads the microprogram from the storage means. Is configured to be executed by the execution unit. This information processing device has a problem that it is difficult to allocate a new instruction code in order to maintain object interchangeability with the conventional one when adding a new function instruction code after determining an instruction code system with a small number of instruction codes. was there. In other words, the information processing apparatus according to the conventional technology has a conventional instruction code system allocated within the bit number limit even when an attempt is made to add a high-performance instruction code due to an increase in the capacity of the storage device for storing microprograms. It was difficult to allocate a large number of new instruction codes in order to maintain the interchangeability with.

In order to solve this problem, an information processing apparatus according to the prior art is provided with a shift register for temporarily storing an instruction code and a plurality of decoders having different decoding methods, as described in Japanese Patent Laid-Open No. 4-158442, for example. It has been proposed to select and decode an arbitrary decoder from the plurality of decoders according to the length of a control signal written in the shift register.

[0004]

In the decoding method according to the prior art described above, although a large number of instruction codes can be assigned with a small number of instruction codes, a plurality of decoders are prepared according to the length of the instruction code stored in the register. Therefore, there was a problem that the hardware configuration became complicated.
An object of the present invention is to eliminate the above-mentioned problems caused by the conventional technique, and to provide an instruction decoding method which can easily add a new instruction code with a small hardware configuration.

[0005]

In order to achieve the above object, the present invention provides a microprogram read from a storage means, for example, a RAM, by an instruction decoding unit decoding an instruction code to generate an address, and based on the generated address. An instruction decoding method of an information processing device for executing
It is possible to allocate a different instruction to the same instruction code by providing a flag indicating the decoding type of the instruction code, and by decoding the instruction decoding unit so that the address of the microprogram read from the storage means is switched by the flag. Characterize.

[0006]

In the instruction decoding method according to the above feature, a limited number of instruction codes can be obtained by decoding the instruction decoding unit so as to switch the address of the microprogram read from the storage means by a flag indicating the decoding type of the instruction code. Even in the system, a new instruction code can be easily added by assigning different instructions to the same instruction code.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an instruction decoding method according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a concept of an information processing apparatus according to the present embodiment. The information processing apparatus includes a main storage device 1 for storing a plurality of instruction codes,
A program counter 10 for storing the address of the instruction code read from the main memory 1, an instruction register 2 for temporarily storing the instruction code read from the main memory 1, and an instruction code stored in the instruction register 2. An instruction decoding unit 3 for decoding the instruction code, a flag program execution state flag (PSW) register 4 for storing an instruction operation mode 5 corresponding to the instruction code, and a micro program counter 6 for counting the addresses decoded by the decoding unit 3. A RAM 7 for storing a plurality of microprograms to be executed in accordance with the address output from the counter 6, a microdata register 8 for temporarily storing the microprograms read from the RAM 7, and a predetermined process executed by the microprograms. Run Consisting of knit 9.

The instruction procedure for executing a predetermined microprogram according to the instruction code from the main memory 1 is as follows: an instruction read (IF) 40 for reading the instruction code from the main memory 1 as shown in FIG. An instruction decode (D) 41 for decoding the read instruction code, an address generation (A) 42 for generating an address to be read from the RAM by this decoding, an operand read (OP) 43 for performing a microprogram read of an address by the address generation 42, Execution commands (EX) 44 for executing the read microprogram are executed in this order.

This series of operations will be described with reference to FIGS. 1 and 2. First, the information processing apparatus reads the instruction code designated by the program counter 10 from the main memory 1 and stores it in the instruction register 2. The program execution status flag 5 corresponding to the instruction code is stored in the register 4. Next, the instruction decode register 3 decodes the instruction code stored in the register 2 according to the instruction operation flag 4 in the program execution state flag 5 stored in the register 4 to generate the address of the RAM 7. The decoding process at this time is the value "0" of the instruction operation flag 4.
Alternatively, it is generated by switching the address mapping 23 of the RAM 7 by '1'. For example, as shown in FIG.
The load instruction 50 shown in FIG. 5 is assigned to the address '0500' of the address mapping 23 of the AM7, and the address '300'.
When a branch instruction 51 is assigned to 0 ', the load instruction address'0500' is generated if the instruction operation flag 4 is' 0 ', and the branch instruction address'0500' is generated if the instruction operation flag 4 is' 1 '. It operates to generate the address '3000'. The generated address is temporarily stored in the counter 6 and sequentially counted up to RA.
A predetermined microprogram is read from M7 and executed by the execution unit 9 via the register 8.

FIG. 3 is a flow chart showing these operating procedures. This flow is based on the program counter 1
When the main memory address (: MMAD) to be read from the main memory 1 of 0 is designated as' 6 ', the instruction code' 08123 of the address' 6 'from the main memory 1
When the instruction fetch 30 for reading 456 'is performed, and the decode 31 corresponds to the instruction code and the instruction operation flag 4 is'0', the instruction code '08XX' and the flag 4 are written.
Generation of start address "0500" by value "0" of 3
2 is performed, and when the instruction operation flag 4 is "1", the start address "3000" is generated 34 by the instruction code "08XX" and the value "1" of the flag 4, and the load instruction corresponding to each address is executed. 33 or execution of branch instruction 3
Do 5.

As described above, in the present embodiment, the instruction decode unit 3 sets the value of the instruction operation flag 4 and the main memory 1.
By switching and generating the RAM start address of the microprogram to be executed according to the value of the instruction code read from, a new instruction code can be easily added without significantly changing the hardware configuration.

Next, in the new instruction mode, a new addition instruction (for example, two word length unified instruction) and a conventional instruction (for example, 1.
The operation of the embodiment in which the conventional instruction LG instruction, the new addition instruction $ ADD, and the conventional instruction MVC are executed in this order in a mixed manner (2.3.4 word length) will be described with reference to FIG. Here, the conventional instruction is a common instruction that is not controlled by the value of the instruction operation mode flag 5 of the program execution state flag, and the newly added instruction is the instruction operation mode flag 5 of "1".
Only in the case of, the instruction can be executed. Also, the old command is
The instruction can be executed only when the value of the instruction operation mode flag 5 is “0”. Therefore, in the new instruction mode when the value of the instruction operation mode flag 5 is "1", the new addition instruction and the conventional instruction can be executed. The conventional instruction described here has a different instruction code system from the newly added instruction.

For example, a conventional instruction (LG instruction) includes an instruction read (IF) 60 and an instruction decode (D) 6 as shown in FIG.
1, address generation (A) 62, operand read (O
F) 63, execution (EX) 64, instruction read (IF) 6
5, instruction decode (D) 66 is performed in this order. At the time of processing of this decode (D) 66, the instruction code and the value “1” of the instruction operation mode flag 5 are used to switch from the conventional instruction to the newly added instruction. Instead of directly branching to the microprogram start address of the $ ADD instruction, a specific microprogram start address (eg, 2C
4E) and the instruction is retaken. For example,
Instruction fetch (IF) 67, instruction fetch (IF) 6
8. Instruction fetch (IF) 69 is performed three times, and re-decoding (D) 70 is performed. After the above re-decoding (D) 70, $
Branch to the microprogram start address of the ADD instruction, and perform address generation (A) 71, operand reading (OF) 72, execution (EX) 73, instruction reading (IF) 74, and instruction decoding (D) 75 in this order. ,
At the time of decoding (D) 75, the instruction code and the value “1” of the instruction operation mode flag 5 change the newly added instruction from the conventional instruction. Therefore, instead of directly branching to the microprogram start address of the MVC instruction, the new addition A specific microprogram start address (for example, 2C4) for optimizing instruction fetch of a conventional instruction from an instruction
Branch to F) and re-execute the instruction. For example, instruction fetch (IF) 76, instruction fetch (IF) 77,
The instruction fetch (IF) 78 is performed three times or twice, and the re-decoding (D) 79 is performed. After the above re-decoding 79, M
Branch to the microprogram start address of the VC instruction, generate address (A) 80, read operand (O
F) 81, execution (EX) 82, instruction read (IF) 8
As described above, the conventional instruction (LG), the new addition instruction ($ ADD), and the conventional instruction (MVC) can be mixed and executed in the order of the instruction decode (D) 84.

In each of the above embodiments, the instruction operation mode flag 5 has a 1-bit configuration, but if this bit is made up of a plurality of bits, for example, 2 bits, an instruction of 4 modes is executed for the same instruction code. Is possible.

As described above, according to the present embodiment, the instruction decoding is switched according to the value of the instruction operation mode flag to optimize the instruction fetch at the transition between the instructions of different decoding methods, and the conventional instruction and the newly added instruction. And can be mixed and executed.

[0016]

As described above, according to the present invention, different microprogram execution start addresses can be generated for the same instruction code by providing the program execution status register with a flag for instructing the instruction decoding method. Therefore, it is possible to easily add an instruction having a new function without adding a new instruction code in the existing instruction code system. Further, when conventional instructions and new addition instructions coexist, by optimizing instruction fetch, it is possible to speed up an instruction group in which conventional instructions and new addition instructions coexist.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an information processing apparatus for carrying out an instruction decoding method according to the present invention.

FIG. 2 is a diagram showing address mapping for switching instruction decoding according to the present embodiment.

FIG. 3 is a diagram showing an instruction decoding switching operation according to the present embodiment.

FIG. 4 is an instruction operation procedure diagram showing a processing procedure operation of the information processing apparatus to which the embodiment is applied.

FIG. 5 is a diagram showing instruction formats of a load instruction and a branch instruction.

FIG. 6 is a diagram showing an instruction operation flow when a conventional instruction and a new addition instruction are mixed.

[Explanation of symbols]

1: Main memory device, 2: Instruction register (IR), 3: Instruction decode unit, 4: Program execution status register (PSW), 5: Instruction operation mode flag, 6: Micro program counter, 7: Micro program storing R
AM, 8: micro data register, 9: execution unit, 10: program counter.

Claims (1)

[Claims] 1. An instruction decoding method of an information processing apparatus, wherein an instruction decoding unit decodes an instruction code to generate an address, and executes a microprogram read from a storage means based on the generated address, the instruction code. Is provided, and a different instruction is assigned to the same instruction code by decoding the instruction decoding unit so that the instruction decoding unit switches the address of the microprogram read from the storage means by the flag. Instruction decoding method.