KR950003884B1 - Personal computer bus interface circuit - Google Patents

Abstract

The efficient 16bit data transmission is allowed by introducing this bus interface circuit comprising a low bus (LB) where a low byte data buffer (2) is connected; a high bus (HB) where a high byte data buffer (3) is connected; a low byte RAM (4) hooked up to the low byte data buffer; a high byte RAM (4) hooked up to the high byte data buffer (3); a state machine logic means (10) analyzing the word unit machine instructions on the PC bus to decode the 7 bits (LA17-LA22) and generates the MEM16 signal to operate the word unit memory control; and an intermediate buffer (12) buffering the intermediate data.

Description

Personal bus interface circuit

1 is a block diagram of a conventional PC bus interface circuit.

2 is a block diagram of a personal computer bus interface circuit according to the present invention;

3 is a timing chart of a personal computer AT bus according to the present invention. FIG. 16c operation timing chart when the instruction is executed in 3c or word units.

4 is a timing chart of a personal computer 386 bus according to the present invention. 4C or a 16-bit operation timing chart when performing an instruction in a word unit.

5 is a state machine state diagram in the present invention.

6 is a circuit diagram of an embodiment of a state machine logic section and a gate section in the present invention.

* Explanation of symbols for main parts of the drawings

10: state machine logic portion 11: gate portion

12: Mid byte data buffer.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer bus interface circuit, and is particularly suitable for at least AT class personal computers for 128K or less shared memory having a state machine when executing commands in units of words (hereinafter, abbreviated as movsw command). It relates to a personal computer bus interface circuit.

The conventional personal computer bus interface circuit includes a MEM 16 decoder 6 which generates a signal MEM 16 for performing a memory operation in units of words to use the high bus HB of the AT bus as shown in FIG. After the signal MEM 16 is input, the address buffer 1 which applies the address signal output from the low bus LB to the low byte RAM 4 and the high byte RAM 5 and the low on the low bus LB A low byte data buffer 2 for applying byte data to the low byte RAM 4, a high byte data buffer 3 for applying high byte data from the high bus HB to the high byte RAM 5, It consists of a low byte RAM 4 and a high byte RAM 5 which store low and high byte data, respectively.

The conventional circuit configured as described above has a high bus (HB) when an address from the AT bus is used to form an AT bus interface circuit that performs 16-bit operation, and a memory using the address at the time of output is a 16-bit card that desires 16-bit operation. ), A signal (MEM 16) is inputted to indicate that the card used by the user is a 16-bit card.

At this time, the address used to generate the signal MEM 16 cannot use the signals SA ₀ -SA ₁₉ generated from the low bus LB, and the upper 7 bit addresses LA ₁₇ -generated from the high bus HB. LA ₂₃ ) must be used.

The reason is that the upper 7-bit address LA ₁₇ -LA ₂ has a value which is faster than the signal SA ₀ -SA ₁₉ .

When the generated signal MEM 16 is input to the high bus HB by the decoder 6, a 16-bit address is first input from the low bus LB to the RAM through the buffer 1, which is a low byte. The operation is where data is transferred to the low byte RAM 4 via the low byte data buffer 2 and the high byte operation is when the data is transferred from the high bus HB to the high byte RAM 5 via the high byte data buffer 3. Is sent).

However, such a conventional circuit must use the upper 7-bit address (LA ₁₇ -LA ₂₉ ) to generate a signal (MEM 16), so at least memory capacity must be 128K or higher, so 16-bit transfer is not possible when using 128K or less memory. Impossible, when using more than 128K memory has to use a large memory capacity there was a problem that the product cost increases.

SUMMARY OF THE INVENTION In view of such a conventional problem, an object of the present invention is to provide a personal computer bus interface circuit which enables 16-bit transfer operation even with a memory capacity of 128K or less by using a specific state machine by the movsw command.

Hereinafter, the present invention will be described in detail by the accompanying drawings.

2 is a block diagram of a personal computer bus interface circuit according to the present invention, wherein the PC AT. State machine for analyzing the movsw command during the 16-bit operation of the 386 PC bus, decoding the upper 7 bits (LA ₁₇ -LA ₂₃ ), and inputting a signal (MEM 16) to operate the memory in the word unit on the AT bus. The logic unit 10 and the gate unit 11 are interposed between the low bus LA and the high byte RAM 5 through an intermediate byte data buffer 12 that buffers intermediate byte data.

In addition, the circuit structure to which the same number has been assigned represents the 1st degree and the same structure.

In addition, the circuit configuration of a specific embodiment of the state machine logic section 10 and the gate section 11 as described above is a plurality of inverters I ₁ -I ₅ and end gates A ₁ -A ₄ as shown in FIG. , Or gates OR ₁ -OR ₆ and de flip-flop FF ₁ (FF ₂ ).

The operation and effect of the present invention configured as described above will be described with reference to FIGS. 3 to 5.

First, the operation of the state machine logic unit 10 by the MOVSW command will be described. When a command is executed in units of bytes as shown in FIG. 3A (movsb command), the 8-bit operation timing is composed of four periods.

Cycle 1 reads the low byte of the PC's main memory, and cycle 2 writes this low byte to the corresponding buffer on the card in the bus slot.

Cycle 3 reads the high byte of the PC's main memory. Cycle 4 writes this high byte to the corresponding buffer of the card in the bus slot.

Next, as shown in FIG. 3B, when the command is performed in units of words (movsw command), the 8-bit operation timing is composed of two cycles.

One cycle is the CPU reading the word in the PC's main memory, and two cycles write the word into two consecutive byte operations by auto-incrementing the address in the corresponding buffer of the card in the AT bus slot.

Next, as shown in FIG. 3C, when the instruction is performed in units of words, the 16-bit operation timing is composed of two periods.

Cycle 1 reads the word from the PC's main memory, and cycle 2 writes the word to the corresponding buffer on the card in the AT bus slot.

As shown in FIG. 4A, when the PC 386 executes instructions in byte units, an 8-bit operation timing is composed of two cycles.

First, access the low byte of main memory from inside the PC, and then write the low byte to the corresponding buffer of the card in the bus slot in one cycle, and then access the high byte inside the PC, and then write this high byte in the second cycle. Write to the buffer.

As shown in FIG. 4B, when the instruction is performed in the word unit of the PC 386, the 8-bit operation timing is composed of two cycles.

First, access the word of the main memory from inside the PC, and then write the word's low byte to the card in the bus slot in one cycle and the word's high byte in two cycles.

As shown in FIG. 4C, when the instruction is executed in the word unit of the PC 386, the 16-bit operation timing consists of one cycle.

First, access the word of main memory from inside the PC and write it to the corresponding buffer of the card in the bus slot in one cycle.

The above timing reads the main memory of the PC and writes it to the corresponding buffer of the card, and vice versa.

The state machine state diagram converted from the timing to the movsw of the 16-bit card after the movsw operation of the 8-bit card is shown in FIG.

First, an 8-bit operation is performed when the movsw command is executed, and two 8-bit operations are successively performed when the 8-bit movsw command is performed, and then the 16-bit operation is converted.

Subsequently, in order to exit the movsw command in 16-bit operation, that is, to exit Q ₁ = 0, which is the output signal Q of the flip-flop (FF ₂ ) of FIG. Returns.

That is, when the state of the state machine logic unit 10 of FIG. 2 is Q ₁ = 1, the state is operated as follows in an 8-bit operating state.

In the low bus LB, an address is inputted through the address buffer 1 into the low byte RAM 4 and the high byte RAM 5, and data is input through the low byte data buffer 2 and the intermediate byte data buffer 12. It is sent to each RAM 4, 5.

On the other hand, when the state of the state machine logic unit 10 is Q ₁ = 0, the state is operated as follows in the 16-bit operating state.

Wherein the input to _{Q 1 = 0, Q 0 =} 0 in the case, and the PC 386 Q ₁ = 0 is high bus (HB) signal (MEM 16), in the case where the PC 286 by the gate section 11 are in the PC The card in the bus slot announces that it requires 16-bit operation.

As such, when the signal MEM 16 recognizes that the card in the bus slot is a 16-bit operation card, the address is stored in the low bus LB through the address buffer 1 through the low byte RAM 4 and the high byte RAM. The data is outputted to (5), and data is transferred to each RAM (4) (5) through the low byte data buffer (2) and the high byte data buffer (3).

A circuit configuration for performing such a series of operations can be configured as shown in FIG.

As described above, the present invention enables a 16-bit transfer operation even at a proper memory capacity of 128K or less by a specific state machine, and thus, it is possible to reduce the reliability and cost of the product.

Claims (2)

A personal bus interface circuit in which a low byte RAM 4 and a high byte RAM 5 are connected to a low bus LB and a high bus HB through corresponding byte data buffers 2 and 3, respectively. Signal for operating memory in word unit after decoding upper 7 bits (LA ₁₇ -LA ₂₃ ) by analyzing movsw command during 16 bit operation of PC AT 386 between (LB) and high bus (HB) An intermediate byte for buffering intermediate byte data between the low bus LB and the high byte RAM 5 via a state vertex logic section 10 and a gate section 11 for inputting (MEM 16) to the AT bus. A personal computer bus interface circuit comprising a data buffer (12). According to claim 1, wherein the state machine logic section 10 and the gate section 11 is a plurality of inverters (I ₁ -I ₅ ), and gates (A ₁ -A ₄ ), or gates (OR ₁ -OR ₆₎ And a flip-flop (FF ₁ ) (FF ₂ ).