KR950003883B1 - Memory logic controller - Google Patents

Abstract

A memory control logic device in a computer system for drawing data recorded in a memory by address and controlling signals of CPU includes: a first memory for recording the command word or data corresponding to even words; a second memory for recording the command word or data corresponding to odd words; an address buffer for latching the address of CPU into an upper/lower address, counting the lower address in a predetermined page area to thereby increase the address; and a control logic part for decoding the address of CPU.

Description

Memory control logic device

1 is a system block diagram of controlling a conventional memory.

2 is a system block diagram having a memory control logic apparatus according to the present invention.

3 is a logical address format assigned to first and second memory means.

4 shows a waveform according to FIG.

* Explanation of symbols for main parts of the drawings

10: central processing unit 11,200: control logic

12: memory 13201: address buffer

14,28,30: Command buffer 15,29,31: Data buffer

20: decoder 21: state machine

22: control signal generator 23: counter

24: first latch 25: second latch

26: first memory means 27: second memory means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control logic apparatus for a computer system, and more particularly, to a burst mode memory control logic apparatus capable of fetching one instruction or data at a system clock by interleaving a slow access memory. It is about.

Generally, a memory control logic device is a logic device that controls to fetch instructions or data recorded in a memory by a control signal and an address of a central processing unit (hereinafter referred to as a CPU). Personal computers), graphics systems for CAD / CAM, medium and large computers, or computer communication systems such as local area networks (LANs) or integrated services digital networks (ISDN). In addition, since the memory control logic affects the overall system performance, it must be controlled so that the memory can be accessed efficiently for high-speed processing capability.

FIG. 1 is a system block diagram of controlling a conventional memory to retrieve an instruction or data, and is an example of application to a system using an erasable programmable memory only memory (EPROM) memory. The memory contains the commands and data necessary for operating the system. The CPU 10 needs to withdraw instructions from the memory 12 to execute a program. At this time, the CPU 10 generates an address and a control signal corresponding to the memory area to be fetched. The address buffer 13 latches an address and applies it to the memory 12. The control logic unit 11 decodes an address and receives a control signal to control the address buffer 13, the command buffer 14, and the data buffer 15. The chip select signal and the output enable signal of the memory 12 are also generated. In addition, an instruction of a memory 12 area addressed according to the output enable signal and the chip select signal of the memory 12 is output. The output command is input to the CPU 10 through the command buffer 14 according to the control signal of the control logic unit 11.

In performing the instruction fetch, the control logic unit 11 considers the system clock speed of the CPU 10 and the access speed of the memory 12 until the instruction is valid on the instruction bus. The output enable signal and the chip select signal must be continuously applied, and the CPU 10 must also not release the address and control signals.

As described above, a system for controlling a conventional memory has a disadvantage of using a memory that is twice as fast as the CPU system clock speed in order to fetch one instruction in one system clock, and the system clock speed is limited because the memory access speed is limited. As the value increases, one instruction is drawn to two clocks or four clocks, and the system performance drops by less than half. In addition, to increase the performance of the system, use fast access memory. However, as memory access speeds up, the price increases exponentially, significantly affecting system costs.

Accordingly, an object of the present invention is to provide a burst control memory control apparatus capable of drawing one instruction to a system clock by configuring a memory having a slow access speed in an interleaved manner.

In order to achieve the above object, the present invention provides a computer system for retrieving information recorded in a memory by an address and a control signal of a central processing unit, wherein the command access signal and data are decoded by decoding the address and control signal of the central processing unit. A decoder for outputting an access signal determined by determining one of the access signals, a state machine for applying an operation state signal according to the access signal determined by the decoder, and three programmable array logics (PALs) Latches a control signal generator including a control signal generator, a counter for loading a lower address and counting an address every access, a first latch for latching an upper address, and an address corresponding to an odd word among lower addresses. The second latch and an even word It characterized in that it comprises a second memory means as a command or data is recorded first memory means, a command or data corresponding to the odd-numbered word is written.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a system block diagram having a memory control logic apparatus according to the present invention. First, the central processing unit 10 uses a reduced instruction computing (RISC) processor. RISC processors not only form simple instructions, all form a fixed instruction field, but also relatively simple addressing mode, which simplifies the data path to process them, resulting in faster execution of all instructions and reduced chip area of hardware. Simplify In this system, the CPU 10 is a 32-bit word type and has three buses: an address bus, an instruction bus, and a data bus. It is also designed to support memory access in burst mode. The CPU 10 generates an address and a control signal corresponding to the instruction or data area in order to retrieve the instruction or data recorded in the first memory means 26 and the second memory means 27. The control signal output from the CPU 10 includes an instruction access request signal, a data access request signal, a burst mode instruction access request signal, a burst mode data access request signal, an address space area signal of an instruction request, an address space area signal of a data access, There are a selection signal of an access unit (word, byte, half word), and the like. The control signals described above are applied to the decoder 20 and the state machine 21, respectively.

The decoder 20 decodes an address and a control signal generated from the CPU 10. The decoder 20 determines whether to access an instruction or data according to the control signal. If the burst mode command access request signal and the command space address signal are applied from the CPU 10, it is the instruction access, and if the burst mode data access request signal and the address space area signal of the command word are applied, it is data access. The decoder 20 also applies a command access signal or a data access signal to the state machine 21 in accordance with the determination of the command or data access.

The state machine 21 receives the signals output from the CPU 10 and the decoder 20 and applies each state signal according to the initial access to the control signal generator 22 when the access signal is valid.

The control signal generator 22 is composed of an instruction control PAL, a data control PAL, and a lower address control PAL to generate an overall signal in accordance with access to the first and second memory means 26 and 27.

The instruction control PAL decodes a status signal according to instruction access to control an output enable signal of the instruction buffers 28 and 30 so that the instructions of the addressed memory region are loaded on the instruction bus, and a handshake with the CPU 10 is performed. Instruction Ready signals IRDY and Instruction Burst Acknowledgments IBACK, which are signals, are applied to the CPU 1 at the timing of initial access. The command burst recognition signal is a signal that burst mode access continues between the first and second memory means 26,27 and the command bus. The instruction ready signal is a signal that each instruction access is completed and ready to send instructions to the CPU 10.

The data control PAL is the same as the command control PAL and controls the output enable signal of the data buffers 29 and 31 in accordance with data access in the first and second memory means 26 and 27. In addition, a data ready signal (Data Ready, DRDY) and a data burst recognition signal (Data Burst Acknowledge, DBACK) is generated and applied to the CPU 10.

The lower address control PAL controls the counter 23 so that a burst mode is supported within a predetermined page area in the address output from the CPU 10 upon initial access, and the odd address word is accessed when the first memory means 26 is accessed. The timing is controlled so that the corresponding lower address is temporarily latched in the second latch 25.

The counter 23 increments the address by latching the initial lower address and triggering on the rising-edge of the count signal for the address corresponding to the predetermined page area. This is because the CPU 10 does not generate an address every time a plurality of instructions or data are fetched, but only an initial address and increments the address in the counter 23, so that the instruction or data can be fetched in the burst mode.

The first memory means 26 and the second memory means 27 are used as EPROM memories and are configured in an interleaved manner. The interleaved method is a method of designating addresses at a distance of a predetermined number without assigning addresses sequentially to connected memories in a storage module.

The memory of the apparatus is divided into two memory modules so that an address corresponding to an even word is assigned to the first memory means 26 and an address corresponding to an odd word is assigned to the second memory means 27.

3 is a logical address type assigned to the first memory means 26 and the second memory means 27. As shown in FIG.

The CPU 10 generates addresses in units of bytes and has 32-bit processor processing power, so 32 bits correspond to one word. In addition, when divided by byte, four bytes correspond to one word. If the least significant byte of each word is ××× 0, ××× 8, it corresponds to the even word, so it is assigned to the first memory means 26. If the least significant byte is ××× 4, ××× C, As such, it is assigned to the second memory means 27. Therefore, only the least significant byte ××× 0, ××× 4, ××× 8, ××× C is determined for each word, and the first memory means is alternately interleaved regardless of the upper byte in the predetermined page area. The second memory means 27 can be accessed.

For example, referring to FIG. 3, when an address occurs from the 30000th byte, 3 corresponding to the most significant byte is temporarily latched in the first latch 24, and an address corresponding to the 3000th byte, the initial address, is loaded into the counter ( start counting when loaded). By counting up to 3000 to 3003 bytes, the first memory means 26 is accessed as the 0th word in the initial access reference. While the first memory means 16 is accessed, 3004-3007 bytes are counted and temporarily latched in the second latch 25 as the first word. When the first memory means 26 is accessed, the first word latched in the second latch 25 accesses the second memory means 27. The first memory means 26 and the second memory means 27 alternately perform an access operation while increasing the address in the counter 23 until the end of the address.

4 is a timing diagram of accessing an instruction when the initial access is an address of an even word. FIG. 4 (a) is a system clock, and FIG. 4 (b) is used to request instruction access as an instruction request (IREQ) signal. That is, if the signal of the fourth (b) is active, the address to be accessed is displayed on the address bus. The fourth signal (c) is an instruction burst request (IBREQ) signal and is used to request burst mode instruction access. The fourth (d) degree signal is an instruction access (IACC) signal, and the fourth (e) degree signal is an instruction burst request delay (IBREQD) signal. This signal is delayed to be active in the area. The fourth (f) to fourth (i) degrees signals are control signals of the state machine 21, the fourth (j) degrees signals are command burst recognition signals, and the fourth (k) degrees signals are currently accessed. Signal indicating initial access. The fourth (l) degree signal is a signal for loading the lower address into the counter 23 during the initial access, and the fourth (m) degree signal latches the upper address in the first latch 24 during the initial access. The fourth (n) signal is a memory selection signal, which is toggled when the initial access ends and the burst mode access starts. That is, the signal decodes the second address bus of the CPU 10 during the burst mode access so that the first memory means is selected at the low level and the second memory means is selected at the high level. The fourth (o) degree signal is a count signal, the fourth (p) degree signal is a signal which causes the second latch 25 to latch the odd-numbered address generated by the counter 23, and the fourth (q) degree signal. Is a signal indicating that the current access is a burst access, and the fourth (r) degree signal and the fourth (s) degree signal are unit signals that logically classify the first memory means and the second memory means, and the fourth (t) arrival The call is an instruction ready signal, and the fourth (u) degree signal is an output enable signal of the memory buffers 28 and 30.

Among the above-mentioned signals, the fourth (f) to fourth (i) and fourth (k) degrees signals, which are state machine control signals, are active at high level and other signals are low level. Activating at

Next, the signal processing relationship of the above-described operation contents will be described with reference to FIG. 2 and FIG.

When the CPU 10 intends to withdraw an instruction from the first memory means 26 and the second memory means 27, the CPU 10 activates the signal of FIG. 4 (b) and outputs an address on the address bus. Let's do it. Since it is a burst access, the signal of FIG. 4 (c) is accessed. Next, the decoder 20 decodes the address to indicate that the instruction access is started by the signal of FIG. The signal in FIG. 4 (e) delays the signal in FIG. 4 (c) so that the signal in FIG. 4 (c) is active in the rising region of the system clock 2. FIG. The state machine 21 generates signals of FIGS. 4 (f) to (i) which are state machine control signals.

The counter 23 latches the lower address of the CPU 10 when the next signal of Fig. 4 (l) is activated. The signal in FIG. 4 (m) latches the upper address of the CPU 10 to the first latch 24. As shown in FIG. Since the signal of FIG. 4 (n) is in the low level state, the first memory means 26 is selected so that the burst mode is started by the signal of FIG. 4 (q).

Next, the first memory means 26 is accessed while the signal of FIG. 4 (o) is counted. An initial access operation occurs at the system clock 6. Before the initial access operation, the lower address corresponding to the odd word is temporarily latched in the second latch 25 by the signal of FIG. 4 (p). Then, when the initial access operation is completed, the count drops to the falling region in the system clock 6 to access the second memory means 27. Since the signal of FIG. 4 (t) and the signal of FIG. 4 (u) are in an active state, an instruction of an area addressed through the instruction buffers 28 and 30 is applied to the CPU 10.

In the initial access, four system clocks are required because the burst mode command request signal is generated in the system clock (2) and the access operation has occurred in the system clock (6). The second memory means 27 access operation takes place at the second memory device 27, and the first memory means 26 access operation occurs at the access clock 8 to perform one memory access operation to one system clock. That is, one instruction fetch is made to one system clock.

As described above, in the memory control logic apparatus of a computer system, the access speed is slow by configuring the memory in two interleaved manners and accessing the memory in a burst mode that can fetch one instruction to one system clock. Using low-cost memory, you can design and build high-performance computer systems.

Claims (9)

A computer system for retrieving information recorded in a memory by an address and a control signal of a central processing unit (10), comprising: first memory means (26) in which instructions or data corresponding to an even word are recorded; Second memory means 27 in which an instruction or data corresponding to an odd word is recorded; The first memory means 26 and the second memory means are latched by the address of the CPU 10 to the upper address and the lower address, respectively, and the address is increased by counting the lower addresses in a predetermined page area. Address buffer means 201 for applying an address to 27; Decode the address of the CPU 10, receive a control signal to determine the operation state according to the access signal of the command or data, and the first memory means 26 and the second memory means 27 and And a control logic unit (200) for controlling the address buffer means (201). The memory according to claim 1, wherein the first memory means (26) and the second memory means (27) are configured in an interleaved manner, and output instructions or data to the CPU 10, respectively. Control logic device. The apparatus of claim 1, wherein the address buffer means 201 loads a lower address supplied from the central processing unit 10 to increase an address upon every access, and the central processing unit A first latch 24 for latching an upper address supplied from (10), and a second latch 25 for latching a lower address corresponding to an odd word among lower addresses loaded on the counter 23; Memory control logic device, characterized in that configured. The apparatus of claim 1, wherein the control logic unit 200 is configured to decode an address and a control signal supplied from the CPU 10, and an operation state according to an access signal output from the decoder. Memory control logic, characterized in that it comprises a control signal generator 22 for controlling the state machine 21, the first memory means 26, the second memory means 27, and the address buffer 201 to determine. Device. 5. The counter 23 according to claim 4, wherein the counter 23 for loading a lower address supplied from the central processing unit 10 to increase the address at every access, and the upper address supplied from the central processing unit 10 Memory control logic, comprising: a first latch 24 for latching a second latch; and a second latch 25 for latching a lower address corresponding to an odd word among lower addresses loaded in the counter 23. Device. 5. The control signal generator (22) according to claim 4, wherein the control signal generator (22) is adapted to control instruction control programmable array logic (PAL) for instruction access, data control programmable array logic (PAL) for data access, and lower address. A memory control logic device comprising lower address control programmable array logic (PAL). A memory control logic apparatus for controlling a plurality of memories configured in an interleaved manner in a burst mode in which one instruction or data can be fetched in one system clock, comprising: latching an upper address and a lower address and predetermined page area; Address buffer means for applying an address to said several memories by counting a lower address within said address and increasing said address; And a control logic section for controlling the plurality of memory selections and the address buffer means. 8. The address buffering device of claim 7, wherein the address buffer means includes a latch means for latching an upper address, a counter means for latching and counting a lower address, and a lower word corresponding to a turn word to the next word while being applied to one memory. And a latch means for latching a corresponding lower address. 10. The apparatus of claim 8, wherein the control logic consists of programmable array logic (PAL).