JPH09319657A - Processor provided with buffer for reading instruction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an instruction from being uselessly read in the case of performing prefetch for enlarging a cache line or for reading the continuous areas of high read possibility into a cache before a request from a processor in order to accelerate transfer speed by utilizing the high-speed page mode of a dynamic random access memory (DRAM) or the like when constituting the instruction cache. SOLUTION: An instruction cache 105 is constituted in the minimum size of a cache line, namely, composed of one line-one instruction and between the instruction cache 105 and a main memory 101, an instruction stream buffer 108 is provided. The instruction stream buffer 108 can write an instruction stream read from the main memory 101 for a variable length in the integer multiple size of the cache line and outputting to the instruction cache 105 is enabled for the unit of a cache line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction cache memory for a processor used in an information processing device such as a personal computer.

[0002]

2. Description of the Related Art A high-performance processor is installed in an information processing apparatus such as a current personal computer or a workstation, and various processing such as moving image processing and three-dimensional image processing is possible. The high-performance processor used in such an information processing apparatus raises the operating frequency in order to improve the operating speed, and the operating frequency inside the chip has reached several tens of megahertz to several hundreds of megahertz. Moreover, as the performance of the processor becomes higher, the size of programs and data that can be handled by the information processing apparatus is also increasing, and it is necessary that the main memory for storing them also has a large capacity. SRAM
It is difficult to configure with a (static random access memory) in terms of cost and technology, and it is configured with a relatively low speed DRAM (dynamic random access memory). The DRAMs currently on the market are 4 megabit products and 16 megabit products, and the access time is about 60 nanoseconds. Even if a high-speed access method called fast page mode access is used, the access time is half that of 30 nanoseconds. 1 access can be performed. However, when calculating the frequency at which the maximum number of times data can be accessed per second is about 33 MHz, it is impossible to continuously supply instructions and data to a processor operating at several hundred MHz. High performance cannot be achieved.

Therefore, a small amount of high speed memory (hereinafter referred to as cache) is provided between the processor and the low speed main memory to realize high performance. When the processor stores the area once read from the main memory in the cache and the processor needs the area again, the program and data can be supplied to the processor at high speed by accessing the cache. A cache hit means that the area that the processor wants to read exists in the cache, and a cache miss hit means that the area that the processor wants to read does not exist in the cache. When a cache hits a cache, the required area is read from the main memory and read into a free area in the cache, or if there is no free space, it is replaced with a partial area on the cache. Capture the area inside.

Recent processors are divided into an instruction cache for reading only instruction sequences used by the processor and a data cache used only for accessing data. Of these, the instruction cache is a cache for reading only the instruction string, so from the perspective of the processor,
It is read-only.

When this instruction cache causes a mishit, the supply of instructions to the processor is stopped, so that the processor is stopped until the instruction is read from the main memory, which causes a deterioration in performance. Various methods have been devised to reduce this mishit. In general, there is a method called prefetch in which an area expected to be used in advance is read in a cache by utilizing the fact that an instruction sequence used by a processor has a property of being continuous and repeating. Japanese Unexamined Patent Publication No. 6-103169 discloses a mechanism that utilizes the repeatability of an instruction sequence, obtains a past access history, and performs prefetch based on this. Further, in Japanese Patent Application Laid-Open No. 7-105098, the continuity of instruction sequences is used to make a FIFO between a cache and a main memory.
If a cache causes a mishit, first, the data of the FIFO capacity is read from the address causing the mishit, and if the data necessary for reading the subsequent instruction of the processor is in the FIFO, F
A mechanism for speeding up by reading from the IFO is disclosed.

[0006]

When the instruction cache is constructed, the instruction sequence used by the processor has continuity. Therefore, when an instruction at a certain place is read, the next instruction is likely to be used. Therefore, by taking a large unit (hereinafter referred to as a cache line) for reading the instruction sequence into the instruction cache, the transfer speed between the main memory and the instruction cache can be improved by using the high speed page mode of the DRAM. Can be expected to improve. The transfer rate is
The larger the cache line size, the better. However, this cache line may read an unused instruction that is not used into the cache due to the influence of a branch instruction. This is because, as the cache line size is increased, this useless reading increases, the transfer rate of effective instructions decreases, and the transfer band of the main memory is wasted,
This will cause a decrease in performance as a whole. In addition, in prefetch in which a continuous area that is likely to be read next due to the nature of the instruction sequence is read into the cache before being requested by the processor, a large area is read while keeping the cache line size small. Can do things,
Therefore, although the high-speed page mode of the DRAM is used to improve the transfer rate, the possibility of reading a wasteful instruction is still large, and the performance may be deteriorated.

[0007]

The above-mentioned problems can be solved by the following constitution.

The instruction cache has a minimum cache line size, that is, one instruction per line, and an instruction stream buffer is provided between the instruction cache and the main memory. This instruction stream buffer has a variable length that is a positive multiple of the cache line size and is capable of writing the instruction sequence read from the main memory and outputting to the instruction cache in cache line units. .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention for realizing the above means will be described with reference to the drawings.

An embodiment will be described with reference to FIGS. 1 to 15.

FIG. 1 is a block diagram of the entire data flow of this embodiment. In the figure, 101 is a main memory, 102 is a main memory interface, 103 is a processor, 104 is a memory bus, 105 is an instruction cache, 106 is a data cache, and 107 is another I / O device connected to the main memory interface. Yes, this is provided with 108 instruction stream buffers.

The main memory 101 stores instruction sequences and data used by the processor 103, and the main memory interface 102 reads and writes data from outside the main memory.

The main memory interface 102 is 10
3 assists access to the main memory of the processor or 107 of other I / O devices, etc.
The instruction sequence and data are input / output from the main memory of and the result is returned to the request source.

The processor 103 stores the instruction sequence and data stored in the main memory 101, through the main memory interface 102, and processes them.

A memory bus 104 is connected to a memory bus interface 102 and a processor 103 and an I / O device 107 which access the main memory by using the memory bus interface.

An instruction cache 105 temporarily stores an instruction string read from the main memory 101 by an instruction read request from the processor 103. If the instruction requested by the processor is stored here, the instruction is sent to the processor from here and the main memory is not accessed.

A data cache 106 temporarily stores the data string read from the main memory 101 by a data read request from the processor 103.
If the data requested by the processor is stored here, the data is sent from here to the processor and the main memory is not accessed. Further, when writing data, there are cases where data is written to the data cache and simultaneously written to the main memory, and data is written only to the data cache and when the data on the cache is erased for some reason, the data is written to the main memory.

The I / O device 107 accesses the main memory 101 (DMA) independently of the processor 103.
Perform

There are 10 instruction stream buffers, 10
The main memory interface 102 which has received the instruction request of the processor 3 receives the instruction sequence read from the main memory 101 and transmitted through the memory bus 104, and transmits a part thereof to the processor's 105 instruction cache as necessary. To do.

FIG. 2 shows the internal structure of the instruction stream buffer block 108 in FIG. 1 of the embodiment. In the figure, 201 is a memory bus interface, 202 is an instruction buffer,
Reference numeral 203 is an instruction valid buffer, 204 is an address tag, and 205 is an instruction stream buffer controller.

The memory bus interface of 201 is
This block connects the instruction stream buffer block 108 to the main memory interface 102 by a memory bus. In response to the main memory read command issued by the instruction stream buffer controller 205, the main memory is accessed to write to the instruction buffer 202 and to the instruction valid buffer 203 that the instruction is valid.

The instruction buffer 202 stores the instruction string output from the memory bus interface 201.
Further, the instruction stream buffer controller 205 reads the data and writes it to the processor 103 and the instruction cache 105.

The instruction valid buffer 203 is 202
The instruction buffer is composed of 1-bit width latches with the same number of rows. A main memory read command issued by the instruction stream buffer controller 205 is cleared, and all are cleared, and an instruction buffer write signal issued by the instruction stream buffer controller is also received, and the bit in the same row as the instruction buffer is set. This allows you to find the line in the instruction buffer that contains a valid instruction.

The address tag 204 holds the address on the main memory of the instruction stored in this instruction stream buffer. Upon receiving the main memory read command issued by the instruction stream buffer controller 205, the main memory read address issued at the same time is stored and held until the next main memory read command is received.

The instruction stream buffer controller 205 receives the read request from the processor 103, determines whether the requested instruction is stored in the instruction buffer 202, and if so, the instruction buffer controller. If there is not, the main memory read instruction is issued to the memory bus interface 201, and, out of the instructions read and stored in the instruction buffer, the instruction requested by the processor 103 and the processor 105 To the instruction cache of.

With the above configuration, the instruction stream buffer block operates as follows.

The instruction stored in the main memory 101 is set to 1
When requested by the 03 processor, the 205 instruction stream buffer receives it and checks to see if it is stored in the 202 instruction buffer. If it is stored at this time, the instruction is fetched and the processor and 105
To the instruction cache of. If not stored, the main memory read command is issued to the memory bus interface 201, and the command requested by the processor in the command string read out and stored in the command buffer is stored in the processor and the command cache of 105. Send.

FIG. 3 is a block diagram of the memory bus interface of the embodiment. In the figure, 301 is a read buffer, 302 is a start address buffer, 303 is a current address counter, 304 is a memory bus controller, 305 is an instruction buffer write controller, 30
6 is the memory bus data, 307 is the memory bus address,
308 is a memory bus control signal, 309 is a read instruction string, 310 is an instruction buffer write address, 311 is an instruction buffer control signal, 312 is a start address, 313 is a main memory read request signal, 314 is a main memory reread signal, and 315 is A read buffer enable signal, 316 is an instruction buffer write control signal, 317 is a start load address, and 318 is a counter control signal. The read buffer 301 holds and holds the memory bus data 306 at the read buffer enable signal timing 315 output from the memory bus controller 316. The content held is 3
The read command sequence of 09 is output to the command buffer of 202.

The start address buffer 302 is 2
The start address of 312 which is also issued at the timing of the main memory read request signal of 313 issued from the instruction stream buffer of 05 is stored. This address is output to the memory bus 104 as the memory bus address 307, and is also output as the start load address 317 used as the initial value of the current address counter 303. The current address counter of 303 outputs 318 of the instruction buffer write controller with the start load address of 317 as an initial value.
The counter is incremented by the counter control signal of. The output of this counter is output to the instruction buffer 202 as the instruction buffer write address 310.

The memory bus controller 304 has 20
5, a memory bus control signal 308 is created based on the main memory read request signal 313 and the main memory reread signal 314 output from the instruction buffer stream controller 5 and is output to the memory bus 104. The read buffer enable signal is generated and output to the read buffer 305. Further, the write timing to the instruction buffer is output as an instruction buffer write control signal 316.

The instruction buffer write controller 305 stores 30 based on the instruction buffer write control signal 316.
A counter control signal of 318, which is a write address creation timing for the instruction buffer of 310 of the current address counter of 3, is output. Also, the instruction buffer control signal 311 is created and the instruction buffer control signal 202 is written.

With this configuration, in response to the request from the processor 103, the main memory read request signal 313 and the main memory reread signal 314 output from the instruction stream buffer 205 are received, and a predetermined instruction from the main memory 102 is received. The column can be read and written to the instruction buffer 202.

FIG. 4 is a detailed diagram of the instruction buffer block of the embodiment. In the figure, 401 is a write side decoder, 402
Is a storage element array, 403 is a read side decoder, 40
Reference numeral 4 is an instruction buffer write address, 405 is a write instruction sequence, 406 is a write control signal, 407 is an instruction buffer read address, 408 is a read instruction sequence, and 409 is a read control signal.

This block stores a write command sequence in the storage element array 402 and outputs the contents as a read command sequence. The writing method is to input the instruction buffer write address 404 and the write instruction string 405,
By issuing the write control signal 406, the write instruction sequence is stored in the row indicated by the write address in the storage element array 402. In the read method, when an instruction buffer read address 407 is input and a read control signal 409 is issued, the read instruction string 408 outputs the instruction string stored in the read address row. At this time, since the write side and the read side each have an address port and an instruction string port, and each has a decoder, reading and writing can be performed at independent timings.

FIG. 5 is a detailed diagram of the instruction valid buffer of the embodiment. In the figure, 501 is a latch, 502 is an address decoder, 503 is an address, 504 is a set signal, 5
Reference numeral 05 is a clear signal, and 506 is an instruction valid signal.

Reference numeral 501 denotes a 1-bit latch, which outputs 1 when a set signal is 504 and 0 when a clear signal is 505. When both are 0, the previous value is held.

Reference numeral 502 denotes an address decoder which, when the address 503 is input, corresponds to the address 504.
Only the set signal of 1 is set to 1.

With this configuration, it is possible to indicate a valid line of the instructions written in the instruction buffer 202.

FIG. 6 is a block diagram of the instruction stream buffer controller of the embodiment. In the figure, 601 is an instruction stream buffer state determination block, 602 is an instruction stream buffer hit determination block, 603 is an instruction stream buffer read controller, 604 is an instruction stream buffer valid signal, 605 is a read address, 606 is an address tag, and 312 is main memory. A read address, 313 is a main memory read request signal, 314 is a main memory reread request signal, 610 is an instruction buffer read address, 611 is an instruction buffer read control signal, 612 is a read request signal, and 613 is an instruction stream buffer reread request signal. , 614 is an instruction stream buffer readable signal, 615 is a read instruction valid signal, and 616 is an instruction stream buffer hit signal.

The instruction stream buffer state determination block 601 receives the read address 605 and the instruction stream buffer valid signal 604, receives an instruction stream buffer reread request signal 613, an instruction stream buffer read enable signal 614, and a signal 615. The read command valid signal is output.

The instruction stream buffer hit determination block 602 determines whether the instruction stored in the instruction buffer 202 is valid from the read address 605, the address tag 606, and the read instruction valid signal 615. , And outputs the result as an instruction stream buffer hit signal 616.

The instruction stream buffer read controller 603 issues 612 issued by the processor 103.
Read request signal and read address of 605, 60
An instruction stream buffer re-reading request signal 613 and an instruction stream buffer readable signal 614 output from the instruction stream buffer state determination block 1;
The instruction stream buffer hit signal of 616 output from the instruction stream buffer hit determination block of 602 is input to determine the current state of the instruction stream buffer, and then determine how the instruction stream buffer operates. The result is the main memory read address of 312, the main memory read request signal of 313, 31
It is reflected in the main memory reread request signal of No. 4, the instruction buffer read address of 610, and the instruction buffer read control signal of 611, and output.

With this configuration, the instruction stored in the 202 instruction buffer is valid from the instruction valid buffer 203, the address tag information 204, the read request signal 612 and the read address request 605 from the processor. If it is invalid, a read request from the main memory is issued, and finally the instruction can be read from the instruction buffer.

FIG. 7 is an internal detailed diagram of the instruction stream buffer hit determination block 602. In the figure, 701 is a comparator, 702 is an AND circuit, and 703 is an address hit signal.

The comparator 701 compares the read address of the input 605 with the address tag of 606. If they match, the address hit signal of 703 is set to true, and otherwise it is set to false.

The AND circuit 702 receives the input 615.
The logical product of the read command valid signal of (1) and the address hit signal of 703 is calculated, and the result is output as an instruction stream buffer hit signal of 616.

With this configuration, when the input read address 605 and the value of the address tag 606 match and the read instruction valid signal 615 is true, the instruction stream buffer hit signal 616 is true. It becomes possible to operate as.

FIG. 8 shows an instruction stream buffer state determination block 601. In the figure, reference numeral 801 is an address decoder, 802 is a selector, 803 is an instruction stream buffer readability determination block, 804 is an instruction stream buffer reread request determination block, and 805 is a select signal.

The address decoder 801 converts the input read address of 605 into a select signal of 805, which is a format in which the selector of 802 can be controlled.

The selector 802 inputs 60
8 out of 4 instruction stream buffer valid signals
The value at the bit position indicated by the select signal 05 is selected and output as a read command valid signal 615. With this configuration, it is possible to indicate that the instruction in the row indicated by the read address 605 in the instruction buffer 202 can be read.

The instruction stream buffer readable determination block 803 determines from the instruction stream buffer valid signal 604 whether the instruction stream buffer can be read and outputs it as an instruction stream buffer readable signal 614. The instruction stream buffer re-reading request decision block 804 decides from the instruction stream buffer valid signal 604 and the select signal 805 whether or not a re-reading request to the main memory should be made, and the result is read in the instruction stream buffer re-reading instruction 613 It is output as a read request signal.

FIG. 9 is a detailed diagram of the instruction stream buffer readability judgment block 803. In the figure, 901 is an n-bit input OR circuit. This circuit takes the logical sum of n-bit input signals and outputs it as a 1-bit output signal.
By inputting the instruction stream buffer valid signal 604 to this circuit and taking the logical sum of each bit, 2
The instruction stream buffer read enable signal 614 indicating that at least one row is readable in the instruction buffer 02 is created. FIG. 10 is a detailed diagram of the instruction stream buffer reread request determination block 804. In the figure, 1001 is an OR circuit, 10
Reference numeral 02 is a NOT circuit, and 1003 is a re-reading unnecessary signal.

An OR circuit 1001 takes the logical sum of two inputs and outputs it. 1002 is a NOT circuit,
Outputs the inverted signal of the input. As described above, the selector 802 selects and outputs the value of the bit position indicated by the select signal 805.

The re-reading unnecessary signal of 1003 is 604
In each bit of the instruction stream buffer valid signal of, it is created by taking the logical sum of all the signals located in the lower row and all of its own values. This signal is selected by the selector of 802 by the select signal of 805, and the NOT circuit of 1002 inverts the result.
Creates an instruction stream buffer reread request signal.

FIG. 11 is a detailed diagram of the instruction stream buffer read controller 603. In the figure, 1101 is an address queue, 1102 and 1103 are address selectors, 1104 is a retry address, and 1105 is a write retry selection signal.

The address queue 1101 is composed of a latch having the same bit width as the read address of 605. The read address of 605 is stored as a read request signal of 612 and held as a retry address of 1104.

The address selectors 1102 and 1103 receive two sets of addresses and a selection signal, and one of the two sets of addresses determined by the value of the selection signal is output. 1102 is 6 as an input address
The read address of 05 and the retry address of 1104 are input and selected by the main memory reread request signal of 314. If true, the retry address of 1104 is selected, and if false, the read address of 605 is selected. , 312 as the main memory read address. The address selector 1103 receives the read address 605 and the retry address 1104 as input addresses, and takes the logical sum of the main memory read request signal 313 and the main memory reread request signal 314 to retry the write retry 1105. The retry address is selected by 1104 when selected by the selection signal, and when it is true, the retry address is selected by 605, and when it is false, the read address of 605 is selected and output as the instruction buffer read address of 610.

The read request signal 612 which is the input signal of this block, the instruction stream buffer re-read request signal 613, the instruction stream buffer read enable signal 614, the instruction stream buffer hit signal 616, and the output signal 312. 12 shows the relationship among the main memory read address of 313, the main memory read request signal of 313, the main memory reread request signal of 314, the instruction buffer read address of 610, and the instruction buffer read control signal of 611 as a truth table of FIG.

The truth table of FIG. 12 shows the relationship between the input signal and the output signal of the instruction stream buffer read controller of FIG. The left half of the figure shows the input signal,
The right half represents the output.

[0060]

According to the present invention, continuous transfer from the main memory can be performed at the maximum storage capacity of the instruction stream buffer, so that the transfer speed from the main memory can be improved and the cache line can be minimized. Therefore, there is no possibility of reading unnecessary instructions into the cache. further,
In the prefetch, the instruction string was transferred to the cache by prediction, but in the present invention, only the requested one is transferred to the cache, so that unnecessary instructions on the cache are not read. Further, by making it possible to interrupt the transfer from the main memory to the instruction stream buffer, it is possible to reduce wasteful transfer from the main memory and speed up the transition to the next necessary transfer.

[Brief description of drawings]

FIG. 1 is a block diagram of the external configuration data flow of the present invention.

FIG. 2 is a block diagram of an instruction stream buffer of the present invention.

FIG. 3 is an explanatory diagram of a memory bus interface of the present invention.

FIG. 4 is an explanatory diagram of an example of an instruction buffer block of the present invention.

FIG. 5 is an explanatory diagram of an example of an instruction valid buffer of the present invention.

FIG. 6 is an explanatory diagram of an example of an instruction stream buffer controller of the present invention.

FIG. 7 is an explanatory diagram of an example of an instruction stream buffer hit determination block of the present invention.

FIG. 8 is an explanatory diagram of an example of an instruction stream buffer state determination block of the present invention.

FIG. 9 is an explanatory diagram of an example of an instruction stream buffer readability determination block of the present invention.

FIG. 10 is an explanatory diagram of an example of an instruction stream buffer reread request determination block according to the present invention.

FIG. 11 is an explanatory diagram of an example of an instruction stream buffer read controller of the present invention.

FIG. 12 is an explanatory diagram of an example of a truth table of the instruction stream buffer read controller of the present invention.

[Explanation of symbols]

101 ... Main memory, 102 ... Main memory interface, 1
03 ... Processor, 104 ... Instruction cache, 105 ...
Data cache, 106 ... Other I / O devices, 10
7 ... Instruction stream buffer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyokazu Nishioka 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi Systems Development Laboratory, Inc. (72) Inventor Toru Nojiri 1099, Ozenji, Aso-ku, Kawasaki, Kanagawa Hitachi Manufacturing Systems Development Laboratory

Claims (6)

[Claims] 1. A processor having a cache used to read instructions, and means of connecting the processor to a mass storage device, and information of arbitrary size between the caches and having its own capacity as an upper limit. A small-capacity storage device having means for reading out from the above-mentioned large-capacity storage device is provided, the continuous instruction sequence read out from the large-capacity storage device is temporarily stored, and the processor itself responds to requests from the processor. If the requested information is stored in the storage device, the requested information is transmitted to the processor and the cache, and if not, the requested information is stored in its own memory by means for reading the information from the mass storage device. After storing in the device,
A storage device characterized by transmitting this to a processor and a cache. 2. A processor comprising the storage device of claim 1. 3. The method according to claim 1, wherein, in addition to the means for reading information of an arbitrary size from the mass storage device, a means for stopping the reading operation currently being performed and a new reading operation are started. If a request is issued from the processor while the storage device is performing a read operation from the mass storage device by providing means, the read operation currently being performed is interrupted and a new read operation is started. A storage device that stores requested information in its own storage device and then sends it to the processor and cache. 4. A processor comprising the storage device of claim 3. 5. The method according to claim 3, wherein in addition to the means for stopping the read operation currently being performed and the means for starting a new read operation, a request is made from the processor during the read operation. In response to the occurrence, a means is provided for determining whether the requested information is obtained by the current reading operation, and the above-mentioned current reading is performed only when the determination determines that the information cannot be obtained. By activating the means for stopping the work and the means for starting a new read work, the current read work is interrupted, the new read work is started, and the requested information is stored in its own storage device. A storage device that sends it above to the processor and cache. 6. A processor comprising the storage device of claim 5.