JPH09128288A - D-ram access speeding-up circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To write data to a D-RAM(dynamic RAM) or read data out of the D-RAM in a short time by decreasing the number of clocks required to access the D-RAM. SOLUTION: When 8-bit or 16-bit data (e.g. print data) outputted from host equipment are outputted from a microprocessor unit(MPU) 1, an address signal is outputted to an address latch 5a through an address bus and a comparator 8 compares it with the last address signal; while both the address signals match each other, the data outputted from the MPU 1 are written to F/Fs 11a-11d through data selectors 12a-12d. When both the address signals become discrepant, oh the other hand, the data are written to D-RAMs 2a-2d while it is considered that that data consisting of, for example, 32 bits are stored in the F/Fs 11a-11d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access speed-up circuit for a D-RAM (dynamic RAM) used in electronic equipment such as a computer.

[0002]

2. Description of the Related Art A D-RAM is a storage means that stores data by accumulating charges in a capacitor.
-Higher integration of storage elements is possible compared to RAM (static RAM). However, since the electric charge accumulated in the capacitor is gradually discharged, it is necessary to rewrite (refresh) data in a predetermined cycle. Also, D-RAM
To access RAS (row address strobe) signal, CAS (column address strobe)
Requires a signal and requires precharging of data. Therefore, there is a problem that the access speed is reduced.

For example, 16 bytes of data are stored in the D-RAM.
If data is written in byte units, the D-RAM is accessed 16 times, and the data precharge and the RAS signal are required at each access.
It takes a long time to output the CAS signal. For example, the following shows this by calculation.

It should be noted that access to the first 1 byte does not require data precharge, requires 1 clock for data precharge in the second and subsequent bytes, and
Considering driving of the sense amplifier in the D-RAM, R
It is assumed that 3 clocks are required to output the AS signal and the CAS signal. Assuming the above, 3 clocks are required for the first access of the first byte, and 4 clocks are required for the access of the second and subsequent bytes. Therefore, as a whole, 3 × 1 + 4 × 15 = 63 (clocks), which is 63 clocks.

On the other hand, a flip-flop (FF)
When inputting data to, since 2 clocks are required for access, 2 × 16 = 32 (clocks), that is, 32 clocks are required for the same 16-byte access as described above.

[0006]

Therefore, the conventional D
In the RAM access method, for example, about twice as many clocks are required as compared with the case of inputting data to the flip-flop (FF), and it takes a long time to access the D-RAM.

An object of the present invention is to reduce the number of clocks required for accessing the D-RAM, to write the data in the D-RAM, and to read the data from the D-RAM in a short time. A high speed circuit is provided.

[0008]

In order to achieve the above object, the present invention provides a D-RAM for storing data and the D-RAM.
Address latch means for latching the address signal for accessing the address, comparing means for comparing the address signal latched by the address latch means, and the comparison processing by the comparing means, when the both address signals match as a result, the data is flip-flopped. This can be achieved by providing a D-RAM access speed-up circuit having a data write means for storing the data stored in the flip-flop and storing the data stored in the flip-flop to the D-RAM when the two address signals do not match.

The data stored in the buffer is
For example, 8-bit data in units of bytes, or 16
It is halfword data in bit units. The present invention is configured as described above, and when using an address signal capable of designating a 32-bit address area, for example, 4
D- until the byte data is input to the flip-flop
Without accessing the RAM, the data is written to the D-RAM after all 4-byte data is input. In the case of half-word data, half-word data in 16-bit units is input twice, and the 32-bit data is not accessed until all 32-bit data is input. After that, data is written to the D-RAM. By controlling in this way, D-R
The number of times of accessing the AM is reduced, and writing of data to the D-RAM and reading of data from the D-RAM are performed in a short time.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment to which the present invention is applied will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a D-RAM access speed-up circuit used in the description of the present embodiment. The D-RAM access speedup circuit of this embodiment is a circuit applied to, for example, a printer device. Therefore, in the figure, reference numeral 1 denotes an MPU (microprocessor unit), and in the description of the present embodiment, for example, system control of the entire printer is performed. Also, 2
Reference characters a to 2d are D-RAMs, which are objects to be accessed in the present embodiment for speeding up the access, and store, for example, print data in an area designated by an address signal described later. In addition to the MPU 1 and D-RAMs 2a to 2d, this circuit includes sequencers 3 and 4, address latches 5a and 5b, an address selector 7, a comparator 8, a RAM address selector 9, and F / F.
F10a to 10d, 11a to 11d, data selector 1
2a to 12d, flag storage units 14a to 14d, 14a '
-14d ', 3-state buffers 15a-15d, 16
a to 16d, etc. Sequencer 3
Reference numerals 4 and 4 denote circuits that output various control signals when accessing the D-RAMs 2a to 2d. The decoder 13 decodes the address signal output from the MPU 1 via the address bus, and the decoded data and MPU 1 to be described later are used. Various control signals are created by taking in the control signals of.

A request signal (DREQ) and a read signal (R) for accessing the D-RAMs 2a to 2d.
The / write signal (W) and the access type instruction signal are output from the MPU 1 to the sequencers 3 and 4. The access type instruction signal is, for example, a byte access instruction signal, a half word access instruction signal, or a word access instruction signal.

The various control signals output from the sequencers 3 and 4 will now be described. The sequencer 3 uses the RAS signal, CAS signal, OE signal, WE signal, RAM address select signal, address select signal, address latch b signal, and data. Select signal, flag clock signal a to
Output d, a'to d '. The RAS signal and the CAS signal are necessary for accessing the D-RAMs 2a to 2d as described above, and the OE signal is the D-RAMs 2a to 2d.
Is a signal for instructing the reading of data from. Also,
The write signal (WE) is a signal for instructing the writing of data to the D-RAMs 2a to 2d. The RAM address select signal is output to the RAM address selector 9 and used for the row address and column address selection processing by the RAM address selector 9. The address select signal is output to the address selector 7, and the address signal output from the address latch 5a is output to the address latch 5a.
Used when transferring to b. The address latch b signal is output to the address latch 5b, and the address latch 5b latches the address signal output from the address latch 5a. Further, the data select signal is the data selector 1
2a to 12d, and output to MPU1 or F / F10a to 1
It is used to select the data to be output from 0d. Further, the flag clock signals a to d and a ′ to d ′ are the corresponding flag storage units 14 a to 14 d and 14 of the flag storage unit 14.
It is output to a'to 14d 'and used for flag setting.

On the other hand, the sequencer 4 includes a buffer all enable signal, a buffer A enable signal, a buffer B enable signal, flag set signals a to d, a'to d'and flag reset signals a to d, a 'to d', F. / F clock signals a to d, a'to d ', and an address latch a signal are output. The buffer all enable signal is output to the 3-state buffers 15a to 15d and 16a to 16d,
The buffer A enable signal is a signal that changes all the buffers from the high impedance state to the data output enabled state, and the buffer A enable signal is a signal that changes the three state buffers 15a to 15d from the high impedance state to the data output enabled state.
The buffer B enable signal is a 3-state buffer 16a.
-16d is a signal that changes from a high impedance state to a data output enabled state. Further, the flag set signals a to
d, a'-d 'and flag reset signals a-d, a'-
d ′ is the flag storage unit 14 of the corresponding flag storage unit 14.
a to 14d, 14a 'to 14d' set flags,
Alternatively, it is a signal for resetting. Further, the F / F clock signals a to d and a'to d'are the F / Fs 10a to 10d and 11 respectively.
This is a signal used when accessing a to 11d. Furthermore, the address latch a signal is a signal which is output to the address latch 5a and used when the address signal output from the MPU 1 is latched in the address latch 5a.

Next, the structure of another circuit driven based on the above-mentioned various signals output from the sequencers 3 and 4 will be described. First, the address latch 5a outputs from the MPU 1 according to the address latch a signal as described above. The address signal to be input is input and latched. The address selector 7 receives the address signal latched by the address latch 5a or M
The address signal output from PU1 is selected according to the instruction of the address select signal described above, and is output to the address latch 5b. The comparator 8 compares the address signal latched in the address latch 5b with the address signal output from the MPU 1, and outputs a coincidence signal to the sequencers 3 and 4 when both signals coincide with each other, and both signals are in agreement. The time mismatch signal is output to the sequencers 3 and 4 described above (or the match signal is not output to the sequencers 3 and 4 when both signals do not match).

Here, the comparison / non-coincidence determination in the comparator 8 does not include the access type instruction signal output from the MPU 1. Therefore, there are four addresses at the time of byte access having an 8-bit width that match the addresses at the time of word access having a 32-bit width. Hereinafter, an address that the comparator 8 determines to match is referred to as an address match.

If, for example, a non-coincidence signal is output from the comparator 8, the address select signal is output from the sequencer 3 to the address selector 7, and the address signal latched in the address latch 5a is transferred via the address selector 7 to the address latch 5b. Transfer to. When the comparator 8 outputs the coincidence signal, the sequencer 3 does not output the address select signal, so that the address signal latched by the address latch 5a is not transferred to the address latch 5b.
The address signals latched in the address latches 5a and 5b remain unchanged.

The address signal output from the address latch 5b to the RAM address selector 9 includes a row address signal and a column address signal, and the RAM address selector 9 is based on the aforementioned RAM address select signal.
Outputs a row address signal to the D-RAMs 2a to 2d,
Then, the column address signal is output to the D-RAMs 2a to 2d. The row address signal is output to the D-RAMs 2a to 2d before the RAS signal is output, and the column address signal is output to the D-RAM 2a to 2d before the CAS signal is output.
The data is output to the RAMs 2a to 2d, and the data is written to the address designated by the row address signal and the column address signal in synchronization with the write signal (WE).

On the other hand, at the above-mentioned timing, the D-RAM 2a
The data to be written in to 2d are, for example, (printing) data held in the F / Fs 11a to 11d. This data is sent to the MPU 1 or F / via the data selectors 12a to 12d.
Output from F10a-10d, F / F11a-11d
Is the data written to. Specifically, when the address match signal is output from the comparator 8, the data selectors 12a to 12d output the data output from the MPU 1 to the F / Fs 11a to 11d according to the data select signal, and the corresponding F / Fs 11a to 11d. Store data. on the other hand,
When the address mismatch signal is output from the comparator 8, MP
The data output from U1 is temporarily stored in the F / Fs 10a to 10d. The data once stored in the F / Fs 10a to 10d is changed by the data select signal output thereafter.
It is transferred to the F / Fs 11a to 11d. In the above process, the writing of data to the F / Fs 10a to 10d is executed by the F / F clock signals a to d output from the sequencer 4, and the writing of data to the F / Fs 11a to 11d is performed from the sequencer 4. F / F clock signals a'to d'to be output
Run by.

On the other hand, the flag storage unit 14 stores the F / F 10a.
When the above-mentioned data is once stored in 10d, a flag is set in the corresponding flag storages 14a to 14d. For example, once the data is stored in the F / F 10a, the flag is set in the flag storage 14a. Also, F / F1
Once the data is stored in 0b, the flag is set in the flag storage section 14b. Similarly, the flag storage units 14a ′ to 1
4d 'is a configuration for setting a flag when temporarily storing data in the F / Fs 11a to 11d. For example, once the data is stored in the F / F 11a, the flag is set in the flag storage unit 14a' and the data is stored in the F / F 11b. Once stored, the flag is set in the flag storage section 14b '.

Therefore, from F / F 10a to 10d to F
When data is transferred to / F11a to 11d, the flag set signals a'to d'and the flag reset signal a to
d and outputs the flag data (flag information) of the flag storage units 14a to 14d at the same time.
This is a configuration for transferring to d '. That is, the flag storage unit 1
If the flag data stored in 4a to 14d is confirmed, F
It is possible to know the data once stored in the / F 10a to 10d, and it is possible to know the data stored in the F / F 11a to 11d by checking the flag data stored in the flag storage units 14a 'to 14d'.

The flag storage units 14a'-14 described above are used.
The output of d'is output to the corresponding gate circuits 17a to 17d, and the gate circuits 17a to 17d generate necessary signals. The signals generated by the gate circuits 17a to 17d are
The CAS0 signal to the CAS3 signal and the buffer enable signal. The CAS0 signal to the CAS3 signal are C
The AS0 signal is the D-RAM2 of the D-RAM2a to 2d.
a, the CAS1 signal is output to the D-RAM2b, and the CAS2 signal is output to the D-RAM2c.
3 signals are output to the D-RAM 2d, and the corresponding D-RA
It is used for processing column address signals in M2a to 2d.

The three-state buffers 15a to 15d are also provided.
Is a buffer used when outputting data from the D-RAMs 2a to 2d, and is a 3-state buffer 16a to 16d.
Is a buffer used when outputting data from the F / Fs 11a to 11d. Also, this 3-state buffer 15
Switching of a to 15d and 16a to 16d is performed by the buffer all enable signal, the buffer A enable signal, the buffer B enable signal output from the sequencer 4 and the enable signal output from the gate circuits 17a to 17d. Incidentally, the above-mentioned three-state buffer 15a
The data output via -15d and 16a-16d are output to, for example, a printer unit and used as print data.

The operation of the D-RAM access speed-up circuit having the above configuration will be described below with reference to the flowcharts of FIGS. 2 and 3. 2 shows the processing operation of the sequencer 3, and FIG. 3 shows the processing operation of the sequencer 4. Further, for convenience of description, the case of writing data in the D-RAMs 2a to 2d and the case of reading data from the D-RAMs 2a to 2d will be separately described below.

First, the case of writing data in the D-RAMs 2a to 2d will be described. In the initial state, the sequencers 3 and 4 are both in a standby state (step (hereinafter indicated by V in FIG. 2) 1, step (hereinafter indicated by W in FIG. 3) 1). Next, a RAM area (D-RAM 2a-2
It is determined whether to access d) (V2, W2). This determination is made based on whether the MPU 1 outputs a data access request signal (DREQ) to the sequencers 3 and 4 and whether the address is within the RAM area. Therefore, while the request signal (DREQ) is not output from the MPU 1 (V2 is N (no) and W2 is N), the standby state described above is continued.

On the other hand, the request signal (DR
When EQ) is output and the address of the RAM area is output (V2 is Y (yes), W2 is Y), the sequencer 4 causes the sequencer 3 to perform the processes of W5 to W7 (specific details of W5 to W7). Will be described later) is determined (W3).

Here, the sequencer 3 processes (V5 to V
If 7) is being executed, since the D-RAMs 2a to 2d are being accessed at this time, the above-described standby state is returned (W3 is Y). On the other hand, if the sequencer 3 has not performed the above-described processing (V5 to V7), then the sequencers 3 and 4 determine whether to write (write) data or read (read) data (V3, W4). Here, the judgment of the data writing or reading process is performed by (V
3, W4), and the R / W signal output from the MPU 1. As described above, for the sake of convenience in the description of the present embodiment, the data write processing to the D-RAMs 2a to 2d will be described first. V3 and W4) are written, and then the address signals latched by the address latch 5b are compared and judged (V4, W5).

This judgment is made, for example, by the comparator 8 by the address latch 5b every time new print data is input to the MPU 1.
Is a process of comparing the address signal stored in the memory with the address signal output from the MPU 1. If both address signals match, the sequencer 4 executes the process (W6) (note that
At this time, the process of the sequencer 3 returns to the standby state as shown in the flowchart of FIG. 2 (V4 coincides, V1). In this processing (W6), the sequencer 4 performs F / F conversion on the data supplied from the MPU 1 based on the designated access type.
This is a process of outputting to F11a to 11d. In particular,
The sequencer 3 outputs a data select signal to the data selectors 12a to 12d, and the data selectors 12a to 12d
d is set on the MPU1 side, the data output from the MPU1 is output to the F / Fs 11a to 11d, the sequencer 4 outputs the F / F clock signals a'to d ', and the data is output to the corresponding F / Fs 11a to 11d. Is latched (this processing is called processing content “W6” in FIG. 3). That is, M
When the address signal output from PU1 does not change and the address signal latched by the address latch 5b matches the address signal output from MPU1, the F / F11a ...
The data output from the MPU 1 is stored in 11d, for example, 1
For each byte (every 8 bits), the corresponding F / F 11a-
11d. Not only when data is input byte by byte, but data may be input in half word (16 bits) units even if the address signal does not change. The word data may be output once. Which F / F1
For data written in 1a to 11d, see F
Flag storage unit 14a 'corresponding to / F11a to 11d
This can be seen by setting the flag at 14d '. For example,
When 2-byte data is written to the F / Fs 11a and 11b, the flags are sequentially set in the flag storage units 14a 'and 14b'. Further, when data is written to the F / Fs 11c and 11d in units of half words (16 bits), the flags are simultaneously set in the flag storage units 14c 'and 14d'.

On the other hand, when the address signal latched by the address latch 5b does not match the address signal output from the MPU 1 (V4 does not match, W5 does not match), that is, when the address signal output from the MPU 1 changes,
The sequencer 3 executes processing (V5 to V7), and the sequencer 4 executes processing (W7) (this processing is referred to as processing content “W7” in FIG. 3). Here, the process (V5) performed by the sequencer 3 is a process in which the sequencer 3 outputs the RAS signal to the D-RAMs 2a to 2d, and the process (V6) is the sequencer 3 outputs the RAS signal to the D-RAMs 2a to 2d. This is a process of outputting a CAS signal and a write signal (W). By executing this process, the F / F 11a-
The data held in 11d is first the D-RAM 2a-2.
It is output to d and written to the specified address. Specifically, the address signal latched by the address latch 5b is output to the RAM address selector 9 to be divided into a row address and a column address, and D at a predetermined timing.
-D-RAM which is output to the RAMs 2a to 2d and is synchronized with the above-mentioned RAS signal and CAS signal output from the sequencer 3.
Write to designated addresses 2a to 2d. By processing in this way, the data output from the F / Fs 11a to 11d can be written to the designated addresses of the D-RAMs 2a to 2d.

Furthermore, the above-mentioned processing (V6) executes the following processing (this processing is called processing content "V6" as shown in FIG. 2). That is, the sequencer 3 outputs an address select signal and the address selector 7 connects the address latches 5a and 5b. In addition, the sequencer 3 outputs a data select signal to set the data selectors 12a to 12d on the F / F 10a to 10d side. By this processing, F / F 11a-11
During the above-described process of outputting the data stored in d to the D-RAMs 2a to 2d, the new address signal output from the MPU1 is latched by the address latch 5a, and the new data output from the MPU1 is stored in the F / F10a. It is temporarily stored in 10d. In addition to the processing described above, the lag storage unit 14a to 10d corresponding to the F / Fs 10a to 10d storing the date and time.
Set a flag on 14d.

In the process (V7) following the above process, the data in the address latch 5a is transferred to the address latch 5b via the address selector 7, and the data selector 12a is operated.
This is a process of transferring the data stored in the F / Fs 10a to 10d to the F / Fs 11a to 11d via the -12d (this process is referred to as a process content "V7" as shown in FIG. 2). That is, the address signal latched by the address latch 5a is transferred to the address latch 5b, and the F / Fs 10a-1.
The data temporarily stored in 0d is transferred to the F / Fs 11a to 11d. Then, the flag data set in the flag storage units 14a to 14d is directly used as the flag storage units 14a 'to 14a.
shift to d ', and F is stored in the flag storage units 14a' to 14d '.
/ F11a to 11d sets the data storage state.

As described above, after the new address signal is stored in the address latch 5b and the new (printing) data is stored in the F / Fs 11a to 11d, the standby state is restored (V7 → V1).

Thereafter, as in the above, the MPU 1 to D-R
When there is an access request to the AMs 2a to 2d (V2 is Y and W2 is Y), the write (write) process or the read (read) process is determined (V3, W4), and then latched by the address latch 5b. Address signal and MPU
The address signal output from 1 is compared (V
4, W5), and corresponding processing is performed according to whether or not both signals match. That is, when the address signals match, the F / Fs 11a to 11 are sequentially processed according to the access type.
d, and corresponding flag storage units 14a ′ to 14d ′.
Set the flag to. Then, each time new data is output together with the address signal, it is determined whether the address signals match, and the data is written to the F / Fs 11a to 11d until the address signals change (unmatch). When the address signals do not match, the F / F 11a ...
The data stored in 11d is written in the D-RAMs 2a to 2d. By controlling in this manner, the MPU 1 can convert 1-word data (32-bit data) into the F / F 11a-1.
Since the data is not written to the D-RAMs 2a to 2d until the data is stored in the 1-d, the number of times of writing data to the D-RAMs 2a to 2d is reduced and the number of accesses to the D-RAMs 2a to 2d is reduced. To D-RA
The M2a to 2d can be accessed at high speed.

Here, how much the access speed of the D-RAMs 2a to 2d becomes faster is calculated. Here, assuming that the latch requires 2 clocks and the RAM access takes 4 clocks in a continuous clock, 16 clocks (4 × 4 clocks) are required for one word (4 bytes) in the conventional example. According to the invention, 10 clocks (2 × 3
+4 clocks) will be enough. Therefore, D-
The RAMs 2a to 2d can be accessed at high speed. Although the above calculation assumes data input in byte units, the access speed of the D-RAM can be similarly improved in half word units.

Next, the case of reading data from the D-RAMs 2a to 2d will be described. In this case also, in the initial state, the sequencers 3 and 4 are both in the standby state (V
1, W1). This state continues until there is a RAM access request (V1 is N, W1 is N), and when the request (DREQ) is output from the MPU1 and the RAM area address is output (V1 is Y, W1 is Y). After confirming that the sequencer 4 is not performing the above-described processing (V5 to V7) (W3 is N), the write processing (write) or the read processing is performed (read) is determined (V).
3, W4). Since this explanation is for the reading process (read) of the data, the judgment (V3, W4) is read, the sequencer 3 outputs the RAS signal by the process (V8), and the RAS by the process (V9). Signal, CAS
Signal and OE signal are output.

On the other hand, the sequencer 4 determines whether the address signal latched in the address latch 5b and the address signal output from the MPU 1 thereafter match (W8), and if both address signals match (W8 matches). ), Processing (W
Go to 9). This process (W9) is performed by the flag storage unit 1
F / F1 in which flags are set in 4a 'to 14d'
Data is read from 1a to 11d, an enable signal is output to the corresponding buffers of the three-state buffers 16a to 16d, and data is output from the F / Fs 11a to 11d via the three-state buffers 16a to 16d. Further, the corresponding 3-state buffers 15 of the DRAMs 2a to 2d whose flags are not set in the flags 14a 'to 14d'
The enable signals are output to the corresponding buffers of a to 15d, and the DRAMs 2a to 2d to the 3-state buffer 15a.
The data is output via ˜15d (this processing is called processing content “W9” as shown in FIG. 3).

That is, in this case, F / Fs 11a to 11d
The data stored in will be stored in the D-RAMs 2a to 2d in the future.
This is the data to be output to, and the data is not stored for 32 bits. Therefore, in this case, the enable signal is output to the corresponding 3-state buffers 16a to 16d, the data is read from the F / F in which the data is stored in the F / Fs 11a to 11d, and the data is read via the 3-state buffers 16a to 16d. Output to the data bus.

In the final judgment (W10), it is judged whether the sequencer 3 is outputting the RAS signal, the CAS signal, and the W signal. If it is outputting, W9 is continued, and when the output is completed, it returns to the standby state ( W10 is Y, W1).

On the other hand, when both address signals do not match (W
8 does not match), and the process proceeds to (W11). in this case,
The process (W11) performed by the sequencer 4 is the D-RAM 2a.
The sequencer 4 outputs the buffer A enable signal to the 3-state buffers 15a to 15d and the data stored in the D-RAMs 2a to 2d via the 3-state buffers 15a to 15d. A state in which the data can be output to the data bus (this processing is called processing content “W11” as shown in FIG. 3). At this time, the processing of the sequencer 3 outputs the RAS signal, the CAS signal, and the OE signal according to the flowchart shown in FIG. 2, and is stored in the D-RAMs 2a to 2d according to the address signal latched by the address latch 5b. Read data to the data bus.

The final judgment (W12) is a process for judging whether the sequencer 3 is outputting the RAS signal, the CAS signal or the like. If it is judged that these signals are not outputted from the sequencer 3, the standby state is obtained. It returns to the state (W12 is Y, W1).

[0040]

According to the present invention, the number of clocks required for access can be reduced when writing data to the D-RAM, and the number of clocks required for access can be reduced when reading data from the D-RAM. Therefore, the access speed of the D-RAM can be increased as a whole.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-speed D-RAM access circuit used to describe an embodiment.

FIG. 2 is a flowchart illustrating the operation of a sequencer.

FIG. 3 is a flowchart illustrating the operation of another sequencer.

[Explanation of symbols]

 1 MPU 2a-2d D-RAM 3, 4 Sequencer 5a, 5b Address latch 7 Address selector 8 Comparator 9 RAM address selector 10a-10d, 11a-11d F / F 12a-12d Data selector 13 Decoder 14a-14d, 14a ' ˜14d ′ Flag storage unit 15a to 15d, 16a to 16d Three-state buffer 17a to 17d Gate circuit

Claims (3)

[Claims] 1. A D-RAM for storing data, an address latch means for latching an address signal for accessing the D-RAM, a comparison means for comparing the address signal latched by the address latch means, and the comparison. As a result of the comparison processing by the means, when both address signals match, the data is stored in the buffer, and when both address signals do not match, the data stored in the buffer is D-RA.
A data write means for outputting to M, and a D-RAM access speed-up circuit. 2. The data according to claim 1, wherein the data stored in the buffer is byte-unit data.
-RAM access speed-up circuit. 3. The high-speed D-RAM access circuit according to claim 1, wherein the data stored in the buffer is data in units of half words.