JPS61161509A - System and device for operating high speed sequence - Google Patents

Abstract

PURPOSE:To perform high-speed sequence operation by storing an operation OP code and an I/O address of an instruction word in a sequence memory while shifting them from each other and adding a simple converting circuit to a programmable controller. CONSTITUTION:A high speed programmable controller PC consists essentially of a CPU10, an OS-ROM11, a sequence memory 12, instruction fetch part 13, a sequence operating part 14, etc. The CPU10 executes not only the service to an input/output peripheral device 22 of an I/O module 21 through an I/O interface part 19 or the like but also function instructions of a timer, a counter, etc. which cannot be processed in the sequence operating part 14. With respect to the processing of an input instruction, bit operation of corresponding I/O information which is read out in advance and is latched is started when the OP code is fetched from the sequence memory 12. The operation is started similarly with respect to an output instruction, and the OP code following said OP code part is set to the non-operation state automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a high-speed sequence calculation method and apparatus for calculating a sequence at high speed.

(Technical background of the invention and its problems) Figure 4 (A) shows a state in which the instruction word of a conventional sequence program is stored in memory, and Figure 4 (B) shows a state in which this instruction word is fetched. It is a diagram. The calculation method of conventional programmable controller PCs is the operation code (hereinafter referred to as OP code) and input/output address (
In order to execute the instruction words of a sequence program consisting of an I/O address (hereinafter referred to as an I/O address), as shown in FIG. The on/off information was input/output by outputting to the . In this conventional method, 1
In order to process one instruction word, at least the time to read the OP code and the time to read the I/O address are required, which is twice the memory access time.

However, in the arithmetic processing of a programmable controller, fetching from the sequence memory requires the most time, so this conventional programmable controller has the problem that high-speed sequence arithmetic cannot be performed.

(Object of the invention) This invention was made under the above circumstances,
Utilizing the sequential processing characteristics of the programmable controller, the OP code and i/.

By shifting the address one step and storing it in the sequence memory, when fetching the OP code, the next I/O address is read ahead at the same time, and when the next OP code is 7 eft, this i10 address is also fetched. It is an object of the present invention to provide a high-speed sequence operation method for a programmable controller and its device, which can perform arithmetic processing immediately and process an instruction word in one memory access, thereby speeding up the sequence operation.

(Summary of the Invention) The present invention relates to a high-speed sequence operation method and device for a programmable controller, and utilizes the property that sequence operations are executed sequentially without jumps in a programmable controller to generate instructions consisting of an OF code and an I/O address. The I/O address part of the word sequence is stored in the sequence memory one step ahead of the corresponding OP code, and the operation of one instruction word is performed in one step.
This makes it possible to access the sequence memory only once.

In other words, in this invention, when an OP code is fetched from the sequence memory for input instruction processing, bit operations are started immediately with the corresponding i10 information that has been previously read and latched in a separately provided tree flop. On the other hand, for output instruction processing, when the OF code is fetched, the I/O address is also fetched and the bit operation starts immediately, but after the operation processing, the I/O address is also fetched.
Since the I/O address is required until the write is completed in o memory, the same i10 address is output to both the previous OP code and its output command, and the OP code part of the sequence memory is The next OF code automatically returns No? without a command. ) to be put into a state.

(Embodiments of the Invention) In the high-speed sequence operation method of the programmable controller of the present invention, each instruction word in the sequence is 16 bits as follows.

15 141312 111098713543
21G Here, the T/E flag is the patent application No. 55-5071.
The top of the input instruction sequence (TOP) or the end of the output instruction (END) for the column cyclic operation in the programmable controller disclosed in Specification No. 3
).

The OP code is represented by 3 bits and is 8 bits as shown in Table 1 below.
Two OP codes function corresponding to symbols in the sequence program. The OF code "000", that is, the symbol NOP of the sequence program, must be written at the top of the sequence operation section and at a part of the OP next to the output instruction. CPUI, CPU2 instructions are CPU
In order to perform processing, the sequence calculation unit only performs the operation of passing the bus to the CPU. In addition, op code 11
The detailed distinction between 0 and 111 is performed in the location section.

The input location part consists of 12 bits, therefore 409 bits.
Up to 6 points can be addressed. The aforementioned column cyclic operations always require unconditional on, off, and pseudo output instructions, but in this invention these instructions are executed by specifying a specific location as shown in Table 2 below. .

Figure 1 (A shows the state in which the instruction words of the sequence program in this invention are stored in the sequence memory, and FIG. 1 (B) shows the state in which these instruction words are fetched into the instruction register. As shown in Fig. 1 (A), the top of the OP code of a sequence program is always a NoP instruction, and the i /
If the primary OP code whose o7 address is set in memory is an input command, this N is first stored in the first stage of the sequence program memory.

i/ which corresponds to P and the OP code OPI of the next instruction word
O address 1101 is stored, and from then on, OPi and 1102.0P are stored in the memory in response to input commands.
The input address part of the input command is stored in the sequence memory one step ahead of the corresponding OF code, such as 2, i/o 3, +1#. When fetching instruction words from a sequence program.

I/O 7 addresses that precede the OP code by one step are fetched at the same time, such as OPI and I/O 2, OF2 and i10/3, and so on. On the other hand, if the OP code is an output instruction, the output address includes the same address in both the previous instruction word and the location part of that output instruction,
Further, the OP code after the output command is a NOP command.

FIG. 2 is a diagram showing a detailed example of storing instruction words in the sequence memory according to the present invention. As mentioned above, there is a NOP instruction at the top of the program that executes any function, and the input address for the code of the next input instruction is set.The input address for the OP code of the 0 manual instruction is all the same as that of the previous instruction word. The output address for the OF code of the output instruction contained in the location section is stored in both the previous location section and the location section of the output instruction, and a NOP instruction is written for the next instruction after the output instruction. .

The distinction between the timer and counter of the CPUI instruction and their addresses are also included in the location part of the instruction word immediately before the CPUI instruction. The CPU2 instruction includes parameters, which are included in the location part of one instruction word. The CPU2 instruction includes parameters, which are included in the location part of one instruction word.

FIG. 3 is a diagram showing an embodiment of the high-speed sequence calculation device of the present invention. This high-speed sequence arithmetic unit, that is, the high-speed programmable controller 5PC, is mainly a cPUl
0.05-ROM11, sequence memory section 12. Command word fe + m 13, sea care X performance 3E
O614, i/Ofi% recess 12. Instruction word fetch gIA13. Sequence calculation unit 14, i/
It consists of an o memory section 15, an I/O interface 19, and a peripheral device interface 20, which are connected by a data bus, an address bus, and a control line. CPU10 is O3 (Operating System)-R
It operates based on the OS program stored in the OMll and controls the operation of the entire programmable controller. This CPU10 is i/.

I/O module 2 via interface 19
In addition to the input/output of 1 and services to the peripheral device 2i22 via the peripheral device interface 20, it also executes function instructions such as timer, counter, and four arithmetic operations that cannot be processed by the sequence calculation section 14. Sequence memory section 1
As explained in FIG. 1(A) and FIG. 2, the instruction word 2 is stored, and when the CPU 10 starts up, the instruction word is issued and output to the instruction word fetch unit 13 which is a register. When the sequence calculation unit 14 is activated by a control signal from the CPU10, the instruction word fetch unit 13
At the same time, the OP code is fetched from the sequence memory section 12 or the flip-flop 18 to be described later.
/o Fetch the address and perform bitwise logical operations directly at high speed without involving CPU10. This sequence calculation unit 14 and CPU10 are connected to the bus request signal B.
They are connected by USRQ and a pass clearance signal BUSAK, and are switched to prevent buses from colliding. If there is a timer, counter, or function instruction word in the OP code of the instruction word being processed by the sequence calculation unit 14, the bus is switched to crtrt0 and the CPU 10 executes processing for the OP code. The I/O address read by the instruction word fetch unit 13 is temporarily stored in the 8-bit memory unit 15 as a byte address, and simultaneously stored in the 8 tol decoder and 1-bit write circuit 17 as a bit address. i10 memory section 15 is C
Access is made in byte units from PU10, while access is made in bit units from the sequence calculation unit 14, which improves memory efficiency and enables faster transfer with the I/O module 21 or execution of function instructions. For the input information shown in FIG. 3, the 8tol decoder 16 extracts one necessary bit from the byte data of the I/O memory section 15 for the input address, and latches it into the flip-flop 18 consisting of one bit at the time of OP food fetch. The output information from the sequence calculation unit 14 is OP
If the code is an output instruction, the same I/O address will be output twice, and the byte data of the output address included in the previous instruction word will be latched so that the next instruction will be a NOP instruction. Since it is stored in the I/O memory section 12 again by the 1-bit write circuit 17, the manual information in FIG. The sequence operation unit 14 immediately performs bit operations.
According to the column cyclic calculation method shown in the specification of No. 13, the ladder calculation is performed by a circuit dedicated to ladder calculation, which only sets input information and branch information in an input shift register. Therefore, an input instruction with T/E=0 requires l clocks, T
An input command with /E=1 can be executed in two clocks, and the execution time of the l instruction can be completed in the time equivalent to one memory access. With the circuit configuration described above, when using a memory with an access time of 100 ns, the input command is 100 ns.
s.

High-speed calculation with an output command of 200 ns can be executed.

(Effects of the Invention) As explained above, the present invention enables high-speed sequence operations by shifting the instruction word OP code and I/O address and storing them in the sequence memory, and adding a simple conversion circuit to the programmable controller. I can do it.

[Brief explanation of the drawing]

FIG. 1(A) is a diagram showing the storage state of the instruction word in the sequence memory in this invention, FIG. 1(B) is a diagram showing the fetch state of the instruction word, and FIG. 2 is a diagram showing the instruction word sequence in this invention. FIG. 3 is a diagram showing a detailed example of storage in memory, FIG. 3 is a diagram showing an embodiment of the high-speed sequence arithmetic device of the present invention, and FIG. The figure shown in FIG. 4(B) is a diagram showing the fetch state. lO...CPU, 11...03-ROM, 12...
・Sequence memory unit, 13... instruction word fetch unit,
14... Sequence calculation unit, 15... I/O memory unit, 1B... 8tol decoder, 17... 1-bit write circuit, 18... Flip-flop, 13...
- i10 interface, 20...peripheral interface. Applicant's agent: Yu Yasugata, Mitsuru l Figure (,11) CB>

Claims (2)

[Claims] (1) In a sequence operation method in which a sequence consisting of an operation code and an input/output address is stored in a sequence memory, sequentially fetched, and bit-operated, there is no operation N in the operation code at the start.
The OP instruction is stored, and the input/output address for the input/output instruction is stored one step ahead of the corresponding operation code, and for the output instruction, the address is the same as both the previous operation code and its output instruction. The output address of the NOP instruction without operation is stored in the OP code next to the output instruction, and the input/output address corresponding to the OP code next to the NOP instruction without operation is stored in the input/output address. A high-speed sequence operation method characterized in that a preceding input/output address fetched together with a code is latched in a flip-flop, and a corresponding input/output address is also fetched at the same time as an operation code is fetched, so that operations can be performed immediately. (2) A CPU that controls the operation of the entire device, a sequence memory section that stores sequences consisting of operation codes and input/output addresses, and an instruction word fetch section that is an instruction register that fetches sequences from this sequence memory section. , an input/output memory section that temporarily stores input/output addresses from the instruction word fetch section, and a sequence operation section that performs bit operations using operation codes and input/output addresses. Extract the necessary 1 bit from the input/output address in the form of byte data from the output memory section 1
an 8tol decoder that outputs bit input information; a flip-flop that latches the input information when fetching an operation code; A high-speed sequence arithmetic device comprising a 1-bit write circuit that rewrites only 1 bit of an output address and inputs it again to the input/output memory section.