JP2738683B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a data processing technique and an instruction execution cycle.
For example, instruction pre-fetching sequentially
Applied to microprocessors that have
And effective technology. [Prior Art] In a data processing device such as a microprocessor
Is a so-called pipeline process in which instructions are prefetched and processed.
Therefore, the data processing speed can be improved. Departure
The authors stated that microphones employing such command prefetch control
As a microprocessor, for example, a microprocessor as shown in FIG.
Microprocessor was studied. In FIG. 9, DI / OBUFs are external data buses EDBUS, respectively.
Input buffer DIBUF and data output coupled to
Data input / output buffer consisting of buffer DOBUF, IIBUF
Command input buffer coupled to the external data bus EDBUS
And CONT are supplied from the instruction input buffer IIBUF
Instruction decoder for decoding instructions and its decoder
Control to supply control signals to each part based on code results
ALU is an arithmetic and logic unit, REG
Is a register array composed of various registers, AO
BUF supplies address signal to external address bus EABUS
Address output buffer, IDBUS
Path DI / OBUF, arithmetic logic unit ALU, register array REG
The combined internal data bus and IABUS
Circuit DI / OBUF, arithmetic logic unit ALU, register REG, address
Internal address bus coupled to output buffer AOBUF
You. In FIG. 9, the clock signal line and the control signal
Lines are omitted. The internal data bus IDBUS, external data bus EDBUS, internal
The external address bus EABUS and the external address bus IABUS
Although not particularly limited, each has a width of 16 bits, and 16 bits
Address output, 8-bit or 16-bit data transfer
It is possible. The instruction input buffer IIBUF is not particularly limited.
However, the so-called master-slave flip-flops
And selectively select the contents on the external data bus EDBUS.
Captured in the master flip-flop,
Select flip-flop contents as slave flip-flops
Can be transferred to The decoder / control unit CONT is not particularly limited,
PLA (Programmable Logic Array) or My
Micro ROM as read-only control memory (read only
Memory) etc., and the instruction input buffer IIBUF
Non-selectively fetch the contents of slave flip-flops
Then, based on the result of the decryption,
Control the operation of the unit. The arithmetic and logic unit ALU includes an internal data bus IDBUS and
Incorporates the contents of the internal address bus IABUS and performs arithmetic processing
And outputs the result to the internal data bus IDBUS. Although the register array REG is not particularly limited,
Of the internal address bus IABUS and internal data bus IDBUS
16-bit flip-flops corresponding to width
Are provided, for example, eight, and data and addresses are provided.
Is used as a temporary storage area. In this register REG
Is the program counter PC, prefetch counter PF
C, condition code register CCR, stack point
And SP are included. Register array REG is internal
Input / output (not shown) between the data bus and IDBUS
A gate is provided, and the internal address bus IABUS
Output gates (not shown) are provided between
The operation of these gates (not shown)
Data, input / output buffer DI / O
BUF, arithmetic logic unit ALU, address output buffer AOBUF
Data and address information can be transferred between
I am able to do it. The data output buffer is used for data input as described above.
By input buffer DIBUF and data output buffer DOBUF
External data bus EDBUS and internal data bus
Data bus IDBUS and internal address bus IABUS.
You. The address output buffer AOBUF has an internal address
Selectively capture the contents of bus IABUS and remove the contents
Output to the local address bus EABUS. The microprocessor MPU shown in FIG.
Although not limited, using a known semiconductor integrated circuit manufacturing technology
Together with a memory or other peripheral circuits (not shown).
Formed on one semiconductor substrate such as crystalline silicon
To form a single-chip microcomputer. Construct this single-chip microcomputer
Microprocessor MPU is a diagram that stores programs
Read the instruction from the memory that does not
The instruction is transferred to the instruction input buffer IIBUF
In the flip-flop. This instruction is
Transfer to lip-flop and solve in decoder / control unit CONT
Read it and supply the corresponding control signal to each part to
Execute the instruction. At this time, instruction fetching (F), instruction decoding
The three stages of (D) and instruction execution (E) are performed by
Using separate functional blocks in the microprocessor MPU
Therefore, the prefetch control of instructions that performs these in parallel
Has been adopted. That is, as shown in FIG.
In parallel with decryption of i (D), fetching of instruction j (F)
In parallel with the execution (E) of the instruction i,
Decryption (D) and fetch of instruction k (F) are performed. to this
Therefore, the effective processing speed of the microprocessor MPU is improved.
You can aim up. Here, many instructions of the microprocessor MPU include:
Address of a variable, such as an operand, used in the instruction
Is included. For example, the
The format is shown in FIG. In FIG. 11, R1 and R2 are register numbers, and Imm is
Media data, abs is an absolute address,
They specify the variables themselves or their addresses. Also
OP is an instruction code that performs operations such as addition, logical product, and branch
Specify the content. The instruction format is shown in Fig. 11.
There is also a format that is modified or expanded from the format shown.
However, a detailed description thereof will be omitted. The contents of R1 and R2 are decoded by the decoder / control unit CONT.
Then, a predetermined resist is selected according to the result. cash register
In direct star mode, the contents of the specified register
Is a variable. Specified in register indirect mode
Accesses memory using the contents of the
The contents obtained from the process are used as variables. Imm
The contents as they are or with sign extension or zero extension are
Is done. abs is the content itself or sign extension or zero extension
The content that is added is used as an address, thereby
The content obtained by accessing is a variable. Therefore, in the immediate mode, the instruction
The contents included in the format are transferred to the arithmetic and logic unit ALU
It needs to be captured. That is, the instruction input buffer
A path to transfer data from IIBUF to the arithmetic logic unit ALU is required.
Is required. In absolute address mode, instruction
From the instruction input buffer IIBUF
A route to transfer data to the address output buffer AOBUF is required.
Is required. These two paths are illustrated in FIG.
Not from the instruction input buffer IIBUF to the internal address
Shared by providing a dedicated route to the bus IABUS
It is possible. [Problems to be Solved by the Invention] However, from the above-described instruction input buffer IIBUF
Provision of a dedicated route to the internal address bus IABUS
Is connected to the instruction input buffer IIBUF and the internal address bus IABUS.
The circuit configuration becomes complicated due to the physical arrangement of
Instruction execution may be affected by such complicated data transfer control.
It has been observed by the present inventors that the line time may be extended.
I was sent out. Therefore, the present inventors have set the instruction code into an instruction input buffer.
Data input buffer DIBUF
As a result of studying a configuration that incorporates
The circuit configuration and the
The control method can be simplified, but the following questions
Clarified that there is a title. That is, in such a system, for example, the instruction i of FIG.
During execution, the contents of instruction j are
Data buffer DIBUF and data input buffer DIBUF.
Must be held, but by execution of instruction i (E)
Read the memory and take in the data on the memory
Use the data input buffer DIBUF
Not thereby, on the data input buffer DIBUF
The contents of the instruction j are destroyed. Born like this
Data input buffer to prevent
Can be dealt with by providing two sets, one of which is dedicated to instruction input
However, if this is done, the circuit scale will increase.
Further, the control method becomes complicated. An object of the present invention is to complicate a circuit configuration and a control method.
Efficient instruction execution processing such as instruction prefetch control
To provide a data processing device that can be realized
It is in. The above and other objects and novel features of the present invention
Will become apparent from the description of the present specification and the accompanying drawings.
Would. [Means for Solving the Problems] Summary of typical inventions disclosed in the present application
The summary is as follows. That is, in the microprocessor, the external bus
Input or output buffer and internal bus to be combined
And storage means coupled to the storage means. [Operation] According to the above-described means, the storage device on the input buffer side is used.
Some or all of the prefetched instructions are retained in the column
Depending on the operands required for instruction execution.
To prevent destroyed preempted instructions. In addition, the storage unit on the output buffer side
By storing the address of the instruction following the instruction,
Is a subroutine call instruction,
The address held in the storage means is stored in the stack area.
Back up for high-speed execution of subroutine call instructions, etc.
Aim. FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention.
It is. This embodiment has been described with reference to FIG.
Is applied to such a microprocessor MPU,
In the following description, it is the same as the functional block shown in FIG.
Functional blocks having functions are assigned the same reference numerals and detailed
Detailed description is omitted. The configuration shown in FIG. 1 is equivalent to the microstructure shown in FIG.
According to the data input buffer DIBUF in the processor MPU
In the figure, IS is an input storage.
This input storage IS is held by the data input buffer
Captures information, especially instructions, and selectively addresses
Registers that can be output to bus IABUS and internal data bus IDBUS
It is constituted by such a circuit. In command prefetch control, a predetermined command is
Loaded into the instruction input buffer IIBUF in the processor MPU
Instruction, the instruction is also stored in the data input buffer DIBUF.
Will be delivered. The storage IS includes a data input buffer DIBU.
After the instruction is held in F, the instruction is transferred.
In this way, the contents held in the input storage IS
When required, the required data
Appears on the internal address bus IABUS or internal data bus IDBUS.
Is forced. On the other hand, data such as parameters or variables
Etc. are taken after the data input buffer DIBUF
Directly, internal address bus IABUS or internal data bus IDBUS
Is output to Therefore, based on instruction prefetch control
A sequential instruction is executed when the instruction input buffer IIBUF and the data input buffer
When loaded into DIBUF, the current instruction
Necessary data is taken into the data input buffer DIBUF
Even if the instruction required for executing the next instruction is
At the cash register, such data
To prevent later needed instructions from being destroyed. FIG. 2 shows, for example, the register indirect mode.
Data such as variables on the memory is stored in the register array REG.
The micro flow of the instruction to transfer to the specified register is shown.
Is done. That is, the contents of the source register (RS) are added.
Data on the memory (not shown)
Microfloor for storing in the application register (RD)
It is. The micro-flow shown in FIG.
Instructions. The previous instruction runs in parallel with its own operation.
And the program counter (or prefetch counter)
Based on the contents of the PC, given instructions from memory (not shown)
And read it out using the arithmetic and logic unit ALU.
A predetermined value, for example, “2” is added to the gram counter.
"2" is added because the memory address is in byte units
Instruction read is 16 bits
That is, it is performed in units of 2 bytes. In the previous instruction,
Finally, the contents on the external data bus EDBUS, ie, 2 steps
The subsequent instruction is transferred to the instruction input buffer IIBUF and the data input buffer.
Input to the input buffer DIBUF (step S0)
Terminates execution of. The transfer instruction does not operate in the first step S1
(Non-operation), followed by step S2,
Address output of the contents of the specified source register (RS)
Set buffer AOBUF, and do not show
A memory read operation is performed (step S3). Next
On the external data bus EDBUS read from the memory
While taking data into the data input buffer DIBUF,
Address output buffer AO for program counter PC
Set it to BUF and transfer it to the arithmetic and logic unit ALU
"2" is added (step S4). The result of the addition is professional
It is stored in the gram counter PC. Data input buffer DI
The contents of BUF, that is, the contents read from the memory, are arithmetic
The data is transferred to the ALU and the data is inspected.
Is executed, and the next instruction is read from a memory (not shown).
Issue (step S5). Based on the inspection results,
Set or reset the option flag and
The data as a number is the specified destination
Stored in register (RD). Furthermore, external data bus ED
The next instruction read to BUS is the instruction input buffer IIB
It is captured by the UF and the data input buffer DIBUF (step
Step S6), the transfer instruction ends. Although the condition flag is not particularly limited,
Set or reset by detecting zero and negative numbers
It is. In FIG. 2, the instruction input buffer IIBUF
Or description of operation related to decoder / control unit CONT is omitted.
Have been. The unit cycle of the external buses EDBUS and EABUS is
Although not particularly limited, the internal operation of the microprocessor
It is twice the unit state. For this reason, memory
Exists on the external data bus EDBUS in the state following the read
Effective value will appear. As described above, the content of the instruction following the transfer instruction is
The contents of the next instruction are stored in the data
Not destroyed by However, the data input in step S2
Transfer from the input buffer DIBUF to the input storage IS.
Therefore, the contents of the input storage IS are
Needed to be used in Step S1. FIG. 3 is a specific logical diagram of one bit in FIG.
It is. In FIG. 3, the data input buffer DIBUF is connected in series.
Connected static master flip-flop DI
BUFM and static slave flip-flop DIBU
It is composed of FS. Master flip-flop DI
The external data bus EDBUS is connected to the input terminal of BUFM.
Output terminal of slave flip-flop DIBUFS
Input such as that constituted by the flip-flop
Force storage IS is connected. Also, slave flip
Output of flip-flop DIBUFS and input storage IS
Terminals are connected via tri-state output gates TOG1 to TOG4
To the internal data bus IDBUS and the internal address bus IABUS
Are combined. FIG. 4 shows the operation of the circuit configuration of FIG.
The time chart is shown. In Fig. 4 ₁ Or φ ₄ Is the clock signal and
Lock signal φ ₁ From the rising edge of the signal to the next rising edge of the same signal
The clock signal φ corresponds to the unit cycle of the external bus. ₁ of
Clock signal φ from rising ₃ Until the rise of
Signal φ ₃ Clock signal φ from the rising edge of ₁ Until the rise
Is a unit state of the internal operation. The contents of the external data bus EDBUS in synchronization with the bus cycle
Is the master flip-flop of the data input buffer
Is taken into the DIBUSM, and non-selectively
Transferred to lip-flop DIBUFS. Slave flip
Transfer from flop DIBUFS to input storage IS is optional.
That is, only the instruction is executed by the control signal φsi.
You. FIG. 5 shows a modification of the configuration shown in FIG.
You. In FIG. 5, the internal data bus IDBUS and the internal address
The lesbus IABUS is a dynamic type.
The flip-flop DIBUF is also configured as a dynamic type.
ing. This reduces the number of transistors that make up the circuit
For example, according to this embodiment, 16 bits generally
126 transistors are reduced. Especially in the case of Fig. 5
Has a double configuration of DIBUFS slave flip-flops.
To the internal data bus IDBUS and the internal address bus IABUS.
Each is dedicated. FIG. 6 is a block diagram showing a main part of a second embodiment of the present invention.
It is. This embodiment has been described with reference to FIG.
Is applied to such a microprocessor MPU,
In the following description, it is the same as the functional block shown in FIG.
Functional blocks having functions are assigned the same reference numerals and detailed
Detailed description is omitted. The configuration shown in FIG. 6 is equivalent to the microstructure shown in FIG.
Pertains to data output buffer DOBUF in processor MPU
In the figure, OS is an output storage.
This output storage OS is connected to the internal data bus IDBUS.
Address bus IABUS, data output buffer DOBUF,
Data output buffer DOBU
The content that is different from the content of F
The contents of the data bus IDBUS and the internal address bus IABUS are
Data can be captured in the output buffer DOBUF almost without delay.
Have been. Based on the micro flow described with reference to FIG.
Prefetch control of the
Switch is performed in synchronization with the operation specific to the instruction, and is currently being executed.
Of each instruction and the instruction that the instruction prefetches
Because the response is unique, the program counter
PC and prefetch counter PFC are one counter
For example, a program counter PC can also be used. this
In this case, as shown in FIG.
It is effective to store the refetch address.
In other words, the address of the instruction being executed is
Is stored, every time prefetch is performed, "4" is
The added value is stored in the address output buffer AOBUF, and
The value obtained by adding “2” is stored in the program counter PC again.
Must be stored, which complicates control.
As a result, the time required for executing the instruction becomes longer. Store prefetch address in program counter PC
In this case, the inventor has found that the following problems exist.
Is out. That is, when the subroutine call instruction is executed
Returns to re-fetch the instruction on return.
Must be saved to the stack area.
However, when a subroutine call instruction is executed,
The counter PC is assigned to the address of the subroutine call instruction.
Because the value to which "4" has been added is stored, save it first.
It is necessary to stand and subtract “2”, which
Control becomes complicated and instruction execution time is extended
Will be done. Subroutine call for subtraction of "2"
The same is true if the instruction is performed not in the instruction but in the return instruction. In this regard, the data output buffer DOBU shown in FIG.
F and the output storage OS,
This is addressed by making minor modifications. That is, in step S4 of FIG.
Set the contents of the interface PC to the address output buffer AOBUF
And transfers it to the arithmetic and logic unit ALU to add the specified value
At the same time, set it to the output storage OS. This
As a result, at the start of execution of the next instruction, the program
The value obtained by adding "4" to the address of the next instruction is stored in the
"2" is stored in the address of the next instruction in the output storage OS.
Is stored. Next instruction is subroutine
If the instruction is a call routine,
Data to the data output buffer DOBUF,
By writing to the memory area, the return destination
Is evacuated. Therefore, the return destination address
The evacuation control method has been simplified,
Execution can be sped up. At this time, the program
Control to transfer the counter PC to the output storage OS
RAM counter PC as address output buffer AOBUF or arithmetic
By also using the control to transfer to the logical operation unit ALU,
Further, the control method can be simplified. FIG. 7 shows the subroutine code in the register direct mode.
5 shows an example of a microflow of a rule instruction. This micro
The flow corresponds to the register corresponding to the number R1 included in the instruction code.
Branches to a subroutine whose contents are the start address
Content. In this micro flow, first,
The stack pointer SP is transferred to the arithmetic and logic unit ALU, and the
A predetermined value, for example, “2” is subtracted therefrom (step S1).
When the result is set in the address output buffer AOBUF
Both are stored in the stack pointer SP. Output storage OS
The address of the next instruction held in the
To the buffer DOBUF (step S2) and show the contents
Write to the missing memory (step S3). Next,
The contents of the register (R1) specified by the
Output buffer AOBUF as well as arithmetic logic
Transfer to the ALU and add “2” to it (step
S4). The result of the addition is transferred to the arithmetic and logic unit ALU.
At the same time, the top
Command to the external data bus EDBUS (step S5),
The instruction on the external data bus EDBUS is
Take in IBUF and data input buffer DIBUF. Blog
RAM counter PC contents to address output buffer AOBUF
At the same time, transfer it to the arithmetic logic unit ALU,
Is added to "2" and the contents of the program counter PC
Is set in the output storage OS (step S6). Next
Read the second instruction of the subroutine from memory
(Step S7). Read the contents of the data input buffer DIBUF
Transfer to input storage IS, and finally, external data
The instruction read on the bus EDBUS is used for the instruction input buffer IIB.
UF and data input buffer DIBUF (step
Step S8), the execution of the instruction ends. Note that the stack pointer
SP is not particularly limited, but indicates the top of the stack area.
Shall be FIG. 8 shows a specific logical structure for one bit in FIG.
FIG. In FIG. 8, the data output buffer DOBUF is connected in series.
Connected static master flip-flop DO
BUFM and dynamic slave flip-flop DO
It is composed of BUFS. Slave flip flow
The external data bus EDBUS is connected to the output terminal of the
Connected and also the input of the master flip-flop DOBUFM
The terminal has an output like a flip-flop.
Force storage OS is connected. Output storage OS input
Terminals are connected via tri-state input gates TIG1 and TIG2.
Connected to the internal data bus IDBUS and internal address bus IABUS
Has been continued. Output storage OS and master flip-flop
Control signal φ to selectively connect and disconnect _SO Is a note
Can be shared with the rewrite signal. Note that the normal
When writing a peland to memory, output the operand.
When data is transferred to the storage OS, the data output buffer is
It is configured to be able to transfer to DOBUF. According to the above embodiment, the following effects can be obtained.
You. (1) Instructions are sequentially input based on instruction prefetch control.
Buffer IIBUF and data input buffer DIBUF
The data needed to execute the current instruction
Even if the data is input to the data input buffer DIBUF, the next instruction
Instructions required for execution are held in the input storage IS as they are.
Required later by such data
Can be prevented from being destroyed. (2) The above effect is obtained by input storage IS such as a latch circuit.
Is provided on the data input buffer DIBUF side.
Input only instructions from the contents taken in DIBUF
It can be obtained by basically controlling only the transfer to the storage IS.
Can complicate the circuit configuration and control method.
Command prefetch control can be realized efficiently
You. (3) The output storage OS stores the address of the instruction following the instruction being executed.
When the next instruction is in the subroutine
If it is a call instruction, the output storage OS
Part to the data output buffer DOBUF and start it.
By writing to the memory area, the return destination
Is evacuated. Therefore, the return destination address
The evacuation control method has been simplified,
Execution can be sped up. The invention made by the inventor above is based on the embodiment.
However, the present invention is limited to the above-described embodiment.
Various changes without departing from the gist of the
Can be. For example, internal bus and external bus configurations,
Decoder, instruction control method, instruction format, etc.
The present invention is not limited to the description of the above-described embodiment, and may employ any format.
can do. Also, the present invention is applicable to instruction prefetch control.
Without limitation, information is taken from outside the microprocessor.
Order and the information used inside the microprocessor.
Use a control format that uses a different order
Can be applied. Also, external to the microprocessor
The contents to be output to the
Apply to those that adopt the control format used earlier
be able to. In the above description, the invention mainly made by the inventor has been described.
As a background, the use of instruction prefetch
Explanation about application to microprocessor with
However, there is a control form other than the instruction prefetching form.
It can be applied to various data processing devices. [Effects of the Invention] According to the representative inventions disclosed in the present application,
The effect of what can be obtained is briefly described as follows
It is. That is, the storage means on the input buffer side
By holding some or all of the issued instructions,
Depending on the operands required for execution,
Can prevent the broken instructions from being destroyed.
Then, the storage means on the output buffer side
By storing the address of the next instruction, the next instruction is supported.
If it is a routine call instruction,
Saves the address stored in the stack unit to the stack area
To execute subroutine call instructions at high speed
And thereby complicate the circuit configuration and control method.
Achieve more efficient instruction prefetch control without
Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention, FIG. 2 is a micro flowchart of a transfer instruction applied to the first embodiment, FIG. 3 is FIG. 4 is a specific logical configuration diagram for one bit in the configuration of FIG. 4, FIG. 4 is a time chart for explaining the operation of the configuration shown in FIG. 3, and FIG. 5 is a description showing a modification of the logical configuration shown in FIG. FIG. 6, FIG. 6 is a block diagram showing a main part of a second embodiment of the present invention, FIG. 7 is a micro-flowchart of a subroutine call instruction to which the second embodiment is applied, and FIG. FIG. 9 is a block diagram showing the basic configuration of a microprocessor to which the present invention is applied, and FIG. 10 is a time chart for explaining the operation by the instruction prefetch control in the microprocessor shown in FIG. Chart, Fig. 11 Is an explanatory diagram showing an example of a major instruction formats of the microprocessor shown in FIG. MPU: Microprocessor, DI / OBUF: Data input / output buffer, DIBUF: Data input buffer, DOBUF: Data output buffer, IIBUF: Instruction input buffer, CONT
…… Decoder / control unit, REG …… Register array, AOBUF
…… Address output buffer, ALU …… Arithmetic logic unit, I
DBUS: Internal data bus, EDBUS: External data bus, I
ABUS ... internal address bus, EABUS ... external address bus, PC ... program counter, SP ... stack pointer, IS ... input storage, DIBUFS ... slave flip-flop, DIBUFM ... master flip-flop, OS ...
Output storage, DOBUFS ... Slave flip-flop,
DOBUFM …… Master flip-flop.

Claims (1)

(57) [Claims] An internal bus connected to at least a register, an arithmetic logic unit, and a data input buffer; an output buffer connected to an external data bus; an instruction input buffer connected to an external data bus; A data control device comprising: a data input buffer configured to selectively output data to the internal bus; and an external data bus connected to an external data bus. A circuit that statically holds an input signal from the bus, wherein the data output buffer is connected to an output storage configured by a register that can be selectively connected to the internal bus, and outputs an output signal from the output storage. A data processing device having a circuit for statically holding data. 2. 2. The data processing apparatus according to claim 1, wherein said input storage stores part or all of prefetched instructions. 3. 2. The data processing apparatus according to claim 1, wherein the output storage stores an address of an instruction next to an instruction being executed.