JP2636074B2 - Microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a microprocessor employing a pipeline system.

[Conventional technology]

Microprocessors have remarkably improved in performance and speed, and the operating frequency has been increasing to 16 MHz, 25 MHz, and 33 MHz. However, peripheral devices have a long recovery time (inactive time of read / write pulse) of about 200 nsec.
Therefore, when performing continuous I / O access, another instruction such as a nop (no operation) is inserted between I / O instructions to ensure the recovery time. Was. However, in recent microprocessors, most of the microprocessors adopt a pipeline system for speeding up. Instruction fetch, instruction decode, operand address calculation,
Operand access, instruction execution, etc. are performed simultaneously.

FIG. 2 shows a block diagram of a conventional pipeline type microprocessor.

In FIG. 2, a bus control unit 101, a prefetch unit 102,
The instruction decoding unit 103 and the instruction execution unit 104 are shown. An external data bus 105 and an external address bus 106 are controlled by a bus control unit 101. The prefetch unit 102 receives an instruction sequence fetched from the external data bus 105 by the bus control unit 101 via the internal data bus 107. Prefetch unit 1
02 stores instructions in a prefetch queue and sequentially transfers them to the instruction decoding unit 103. When "empty" occurs in the prefetch queue, a request is made to the bus control unit 101 by the instruction fetch request signal 108, and the bus control unit 101 starts a bus cycle and fetches an instruction sequence. The instruction decode unit 103 decodes the received instruction, passes an operand address to the bus control unit 101 via the internal address bus 110, and passes instruction decode information 111 to the instruction execution unit 104. Instruction execution unit 104
Executes an instruction according to the instruction decode information 111 received from the instruction decode unit 103. At this time, if there is an operand write, the request signal 114 is activated when the write data is completed, whereby the bus control unit 101 starts a bus cycle.

Similarly, in the case of an I / O instruction, in the case of an IN instruction, the request signal 114 is activated when the instruction is executed, and the O
In the case of the UT instruction, the request signal 114 is activated when the write data is completed.

In the pipeline type microprocessor as shown here, as shown in FIG. 8, since the instruction is executed regardless of the bus cycle, the recovery time is guaranteed for the nop instruction between the out instructions. Cannot be executed, and more nop instructions need to be inserted.

In FIG. 8, an instruction for a clock signal (CLK),
, Are shown, but in the out instruction, fetch,
Decode, address calculation, instruction execution, and I / O write operation instructions are sequentially performed. The order of the nop instruction and the out instruction is the same.

[Problems to be solved by the invention]

As described above, in the microprocessor having the prefetch unit 102 as shown in FIG. 2, the instruction supply to the instruction decode unit does not take a long time, and the execution of the instruction is performed asynchronously with the bus cycle. Will be for that reason,
As shown in FIG. 9, when there is an instruction (mov) operand and memory write accompanied by a memory write before the out instruction, depending on the state of the bus, even if there are two instructions consisting of the nop instruction and the nop instruction, / O access may continue, and in order to guarantee I / O recovery time,
It was necessary to insert as many nop instructions as needed to fill the prefetch queue so that a fetch bus cycle was inserted between the I / O instruction and the next I / O instruction to be executed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor which solves the above-mentioned problem and can guarantee a recovery time by inserting a small number of nop instructions.

[Means for solving the problem]

The configuration of the microprocessor according to the present invention includes an instruction decoding unit, a bus control unit, and an instruction execution unit, and includes an I / O instruction and n
a first signal for notifying the instruction execution unit that the op instruction has continued to the instruction execution unit, and a second signal for notifying that the bus cycle has been stopped from the bus control unit to the instruction execution unit. When the first signal is active by the nop instruction, the execution of the nop instruction is delayed until the second signal becomes active.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a microprocessor according to one embodiment of the present invention. 1, the present embodiment includes a bus control unit 101, a prefetch unit 102, an instruction decoding unit 103, and an instruction execution unit 104. Here, the signal 112 is I / O
The instruction decode unit 103 reports that the instruction and the nop instruction have continued.
Is a first signal to be notified to the instruction execution unit 104 from. Signal 1
Reference numeral 13 denotes a second signal notifying that the bus cycle has been stopped from the bus control unit 101 to the instruction execution unit 104.

An external data bus 105 and an external address bus 106 are controlled by a bus control unit 101. The instruction sequence fetched from the external data bus 105 by the bus control unit 101 is transferred to the internal data bus 1
The prefetch unit 102 receives the data via 07. The prefetch unit 102 stores instructions in a prefetch queue and sequentially passes the instructions to the instruction decode unit 103. When "empty" occurs in the prefetch queue, a request is made to the bus control unit 101 by the instruction fetch request signal 108, and the bus control unit 101 starts a bus cycle and fetches an instruction sequence.

The instruction decode unit 103 decodes the received instruction, passes an operand address to the bus control unit 101 via the internal address bus 110, and passes instruction decode information 111 to the instruction execution unit 104. The instruction execution unit 104 includes an instruction decoding unit 103
The instruction is executed according to the instruction decode information 111 received from. At that time, if there is an operand light,
When the write data is completed, the request signal 114 is activated, whereby the bus control unit 101 starts a bus cycle. Similarly, in the case of an I / O instruction, in the case of an IN instruction, the request signal 114 is activated when the instruction is executed, and in the case of an OUT instruction, the request signal 114 is activated when the write data is completed. . The request signal 114 changes in synchronization with the fall of the clock.

The instruction decode unit reports that the I / O instruction and the nop instruction have continued.
When the signal 103 is detected, the instruction execution unit 104 is notified by the I / O and the nop detection signal 112.

The operation of the instruction execution unit 104 in the case of the nop instruction in FIG. 1 will be described with reference to FIG. In FIG. 5, the instruction decode information 11 is transmitted by the select signal 511 of the selector 501.
1, control signal extracted from latch 504, incrementer 506
Of the microprogram ROM 503 corresponding to the selected microaddress is read and held in the latch 504, and the microinstruction decoder 5
05 decodes the contents of latch 504 and outputs a control signal, thereby executing the instruction.

The instruction decode information 111 of the latch output signal 508 is a plurality of signal lines for designating a micro address. One of the signal lines, the I / O and the nop detection signal 112 are passed through an AND gate, and the normal nop instruction Then, in the nop instruction after the I / O instruction, a different micro address is set in the micro address register 502, and a different micro program is latched and decoded from the micro program ROM 503. In the case of a normal nop instruction, the select signal 511 is generated regardless of the bus cycle stop signal 113, and the next instruction decode information 111 is selected. In the case of the nop instruction after the I / O instruction, the bus cycle stop signal 113 and the control information 510 are combined, a signal 508 extracted from the control signal stored in the latch is selected, and the same micro address is repeated. Suspends execution of the nop instruction. When the bus cycle stop signal 113 becomes active, the output signal of the incrementer is selected, and the execution of the nop instruction is started.

Next, FIG. 3 shows an example of a control configuration for operand access in the bus control unit 101.

In FIG. 3, the operand addresses sent via the internal address bus 110 are taken into three address registers 3011, 3012, 3013, and at the same time, the additional information is stored in the additional information flags 3021, 3022, 3023. The address registers 3011, 3012, 3013 are FIFO (First In / First Out), and have three stages in this configuration example. Combination circuits 3031, 3032, and 303 are generated by additional information flags 3021, 3022, and 3023 and request signal 114 sent from the instruction execution unit.
In step 3, an access request signal 301 is generated. Additional information flag 30
21, 3022, 3023 are composed of 3 bits of valid, R /, mem / ▲ ▼, and immediately go to an access request in the case of memory read, and request signal 114 in the case of write or I / O. When it comes, it goes to the access request. The combination circuit 304 includes an access request signal 301, a reset signal 310, a ready signal 311, a TI state signal 314, a T1 state signal 313,
A T2 state signal 312 is input, and state preparation signals TOTI305, TOT1306, and TOT2307 for controlling a bus cycle are output. FIG. 6 shows an input / output combination of the combination circuit 304.

In FIG. 6, the active levels are all "1", and "-" indicates that no reference is made. The external access bus cycle ends with two clocks of the T1 state and the T2 state. After the T1 state, the T2 state always comes. However, when the ready is inactive, the T2 state is followed by a wait state. The T2 state is repeated, and the access request makes a transition to the TI state or the T1 state. The transition from the T2 state to the TI state is regarded as a bus cycle stop, and the bus cycle stop signal 11
Activate 3 and notify the instruction execution unit. The flip-flop 308 is a D flip-flop for switching between TI, T1, and T2 with a clock.

FIG. 4 shows a configuration example in which the instruction decoding unit 103 detects the nop instruction next to the I / O instruction.

In FIG. 4, when an I / O instruction is detected, a D flip-flop 404 is set by an I / O instruction detection signal 402 which becomes active only in the case of an I / O instruction. Of the detection signal 403 and the I / O instruction holding signal 405
By taking the AND, an I / O and a nop detection signal 112 is generated and notified to the instruction execution unit.

In FIG. 7, there is a nop instruction after the nop instruction, and then ou
This shows the pipeline operation when there is a t instruction. This microprocessor has a five-stage pipeline of instruction fetch, instruction decode, address calculation, operand access, and instruction execution. Each stage ends with one clock, and external access ends with two clocks when there is no wait. Shall be. The instruction execution unit executes I / O instructions,
The request signal is activated in synchronization with the falling edge of the clock, and the execution of the I / O instruction ends. Because it is a nop instruction after the I / O instruction, the instruction decode unit uses I / O & no
The p detection signal is activated, whereby the instruction execution unit that has attempted to execute the nop instruction suspends execution of the nop instruction until the bus cycle stop signal becomes active. When the I / O write cycle of the out instruction ends, T2
When the state changes from the idle state to the idle state, the bus cycle stop signal becomes active, and the nop instruction is executed.

As described above, it is possible to realize a margin of several clocks between the previous I / O access and the subsequent I / O access by one nop instruction.

With traditional pipelined microprocessors,
In order to obtain the I / O recovery time, it was necessary to insert a number of nop instructions between I / O instructions. In contrast, in this embodiment, two signals were required. I with minimal nop instructions
/ O recovery time can be guaranteed.

〔The invention's effect〕

As described above, in the conventional pipelined microprocessor, the nop instruction inserted to obtain the I / O recovery time has no meaning, and many nop instructions are needed. The processor only needs to insert one to several nop instructions in accordance with the I / O recovery time of the peripheral device, and when the I / O recovery time is not necessary due to different ports even in continuous I / O access In this method, the I / O access can be continuously performed by not inserting the nop instruction, so that the program size can be reduced and the performance of the computer system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional microprocessor, FIG. 3 is a block diagram of a bus control unit shown in FIG. 4 is a block diagram of the instruction decoding unit shown in FIG. 1, FIG. 5 is a block diagram of the instruction execution unit shown in FIG. 1, and FIG. 6 is a truth table of the combinational circuit in FIG. FIG. 7 is a diagram of the pipeline operation in FIG. 1, and FIGS. 8 and 9 are diagrams of the pipeline operation in the prior art. 101: Bus control unit, 102: Prefetch unit, 103:
Instruction decode unit, 104 Instruction execution unit, 105 External data bus, 106 External address bus, 107 Internal data bus, 108 Instruction fetch request signal, 109 Internal data bus 2, 110 … Internal address bus, 111… instruction decode information, 112… I / O and nop detection signal, 113… bus cycle stop signal, 114… request signal, 301… access request signal, 302… selection signal, 303 ... pointer circuit,
304,507 …… Combination circuit, 305 …… State preparation signal TO
TI, 306 State preparation signal TOT1, 307 State preparation signal TOT2, 308, 404 D flip-flop, 309
Clear signal, 310 reset signal, 311 ready signal, 312 T2 state signal, 313 T1 state signal,
314: TI state signal, 315: Address latch, 3011
... Address registers 0, 3012 ... Address registers 1, 3013 ... Address registers 2, 3021 ... Additional information flags 0, 3022 ... Additional information flags 1, 3023 ... Additional information flags 2, 3031 ... Combination circuit 0 , 3032 combination circuit 1, 3033 combination circuit 2, 401 instruction coder, 402 I / O instruction detection signal, 403 nop instruction detection signal, 405 I / O instruction holding signal, 406 …… AND gate, 501
...... Selector, 502 ... Micro address register, 5
03: Micro program ROM, 504: Micro instruction latch, 505: Micro instruction decoder, 506: Incrementer, 508: Signal extracted from control information stored in the latch, 509: Output signal of incrementer , 510 ……
Control signal, 511 ... Select signal.

Claims (1)

(57) [Claims] A first signal for notifying that the I / O instruction and the nop instruction have continued from the instruction decode unit to the instruction execution unit, comprising: an instruction decode unit; a bus control unit; and an instruction execution unit. When the bus control unit instructs the instruction execution unit to deactivate the bus cycle execution of the I / O instruction, the bus control unit becomes inactive when the bus cycle execution of the I / O instruction ends. And a second signal for notifying that the execution of the nop instruction is delayed until the second signal becomes active if the first signal is active in the nop instruction. .