JPH04171534A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the program size and to improve the performance of a computer system by using a 1st signal which informs an instruction executing part of a fact that an I/O instruction is continuous to an nop (no operation) instruction from an instruction decoding part and a 2nd signal which informs the instruction executing part of a fact that a bus cycle is stopped from a bus control part respectively. CONSTITUTION:A bus control part 101 is provided together with a prefetching part 102, an instruction decoding part 103, and an instruction executing part 104. Then a 1st signal 112 informs the part 104 of a fact an I/O instruction is continuous to an nop instruction from the part 103. Meanwhile a 2nd signal 113 informs the part 104 of a fact that a bus cycle is stopped from the part 101. When the signal 112 is active, the execution of the nop instruction is delayed until the signal 113 becomes active. Thus the recovery time is assured just with input of a small number of nop instructions that can fill a prefetch queue and without using many nop instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and particularly to a microprocessor incorporating a pipeline system.

[Conventional technology]

Microprocessors have significantly improved performance and speed, and their operating frequencies have increased to 16MHz, 25MHz, and 33MHz, but the recovery time (inactive time of read/write pulses) of their peripheral devices is only 200n.
It is large, around sec. Therefore, when performing continuous I/O access, no
The recovery time was guaranteed by inserting other instructions such as p (no operation). However,
Most modern microprocessors adopt a pipeline system to increase speed, and perform instruction fetch, instruction decoding, operand address calculation, operand access, instruction execution, etc. at the same time.

FIG. 2 shows a block diagram of a conventional pipeline microprocessor.

In Figure 2, the bus control section/O-work, the briefetch section/
O2. Instruction decoding section/O3. An instruction execution unit/O4 is shown. The bus controller/O1 controls the external data bus/
O5. It also controls the external address bus /O6. The instruction string taken in by the bus control unit /O1 from the external data bus /O5 is received by the brief fetch unit /O2 via the internal data bus /O7. The brifetch unit /O2 stores instructions in a brifetch queue and sequentially passes them to the instruction decode unit /O3. When there is "empty" in the brief fetch queue, the instruction fetch request signal /O8 causes the bus control unit /O
1, the bus control unit /O1 starts a bus cycle and takes in the instruction string.

The instruction decode unit /O3 decodes the received instruction, passes the operand address to the bus control unit /O1 via the internal address bus 1/O, and passes the instruction defood information 111 to the instruction execution unit /O4. The instruction execution unit/O4 receives instruction decode information 111 from the instruction decode unit/O3.
Execute the command according to the instructions. At this time, if there is an operand write, the request signal 114 is made active when the write data is complete, and thereby the bus control unit /O1 starts a bus cycle.

Similarly, in the case of an I/O instruction, in the case of an IN instruction, the request signal 114 is activated when the instruction is executed, and in the case of an OUT instruction, the request signal 114 is activated when the write data is complete. .

In the pipelined microprocessor shown here, as shown in Figure 8, instructions are executed regardless of the bus cycle, so the nop instruction ■ between the Out instruction ■ and the out instruction ■ cannot be recovered. The time cannot be guaranteed, and it is necessary to insert a large number of nop instructions.

In Fig. 8, instructions ■, ■ for the clock signal (CLK)
, ■ is shown, but in the out instruction ■, fetch,
Each operation instruction of decoding, address calculation, instruction execution, and I/O write is executed in order.

The order of the nop instruction (■) and the out instruction (■) is the same.

[Problem to be solved by the invention]

As explained above, in a microprocessor equipped with a briefetch unit/O2 as shown in FIG. It will be done. Therefore,
As shown in Figure 9, if there is an instruction ■ (mov) operand and write that involves a memory write before the Out instruction ■, depending on the bus status, n Op instruction ■, n
I/O access may continue even with two instructions consisting of Op instructions■, so in order to ensure I/O recovery time, it is necessary to insert as many nop instructions as are necessary to fill the brieffetch queue. , after an I/O instruction, a fetch bus cycle had to be inserted between the next I/O instruction to be executed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a microprocessor that can guarantee recovery time by simply inserting a small number of nop instructions.

[Means to solve the problem]

The configuration of the microprocessor of the present invention includes an instruction decoding section, a bus control section, and an instruction execution section, and the instruction decoding section notifies the instruction execution section that an I/O instruction and a nop instruction are consecutive. and a second signal that notifies the instruction execution unit from the bus control unit that the bus cycle has stopped, and when the first signal is active in the nop instruction, the and a control circuit that delays execution of the nop instruction until the second signal becomes active.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a microprocessor according to an embodiment of the present invention. In FIG. 1, in this embodiment, bus control unit/O1. Brief fetch unit/O2, instruction decode unit/O3. It also includes an instruction execution unit/O4. Here, the signal 112 is a first signal that notifies the instruction execution unit /O4 from the instruction defoding unit /O3 that the I/O command and the nop command are consecutive. The signal 113 is the bus control unit/O
This is the second signal that notifies that the instruction execution 1/O4 bus cycle has stopped.

A bus control unit /O1 controls an external data bus /O5 and an external address bus /O6.

The prefetch unit /O2 receives the instruction string that the bus control unit /O1 fetches from the external data bus /O5 via the internal data bus /O7. The prefetch unit/O2 stores instructions in a prefetch queue and sequentially sends instructions to the instruction decoding unit/O2.
Pass it to 3. When the prefetch queue becomes “empty”, the instruction fetch request signal /O8 causes the bus control unit /
Upon requesting O1, the bus control unit/O1 starts a bus cycle and takes in the instruction string.

The instruction decode unit /O3 decodes the received instruction, passes the operand address to the bus control unit /O1 via the internal address bus 1/O, and passes the instruction decode information 111 to the instruction execution unit /O4.

The instruction execution unit /O4 executes the instruction according to the instruction decode information 111 received from the instruction decode unit /O3. At this time, if there is an operand write, the request signal 114 is activated when the write data is complete, and thereby the bus control unit /O1 starts a bus cycle. Similarly, in the case of an I/O instruction, in the case of an IN instruction, the request signal 114 is activated when the instruction is executed, and in the case of an OUT instruction, the request signal 114 is activated when the write data is complete. . It is assumed that the request signal 114 changes in synchronization with the falling edge of the clock.

When the instruction decode unit /O3 detects that an I/O instruction and a nop instruction are consecutive, it notifies the instruction execution unit /O4 using Ilo and a nop detection signal 112.

The operation of the instruction execution unit /O4 in the case of the nop instruction in FIG. 1 will be explained using FIG. 5. In FIG. 5, instruction decode information 111 . Either the control signal extracted from the latch 504 or the incremented microaddress output from the incrementer 50Ef is selected, and the contents of the microprogram ROM 503 corresponding to the selected microaddress are read out and stored in the latch 504. The microinstruction decoder 505 decodes the contents of the latch 504 and outputs a control signal.
The command is executed.

The instruction decode information 111 of the latch output signal 508 is a plurality of signal lines for specifying micro addresses,
One of them, Ilo and nop detection signal 112 are A
Passed through the ND gate, different microaddresses are set in the microaddress register 502 for a normal nop instruction and a nop instruction after an I/O instruction, and different microprograms are latched and decoded from the microprogram ROM 503. It happens. normal n
In the case of an op instruction, the select signal 511 is generated regardless of the bus cycle stop signal 113, and the next instruction decode information 111 is selected.

In the case of a nop instruction after an I/O instruction, the bus cycle stop signal 113 and control information 5/O are combined, the signal 508 extracted from the control signals stored in the latch is selected, and the same microaddress is repeated. by no
Suspends execution of the p instruction. Bus cycle stop signal 113
When becomes active, it selects the incrementer's output signal and starts executing the nop instruction.

Next, FIG. 3 shows an example of a control configuration for operand access in the bus control unit /O1.

In FIG. 3, the operand address sent via the internal address bus 1/O is taken into three address registers 3011, 3012, and 3013, and at the same time, additional information is stored in additional information flags 3021, 3022, and 3023.
Store in. These address registers 3011, 3012.
3013 is F I F O (First In/Fl
rst 0ut), and there are three stages in this configuration example. Additional information flags 3021, 3022, 30
23 and request signal 1 sent from the instruction execution unit
14, combinational circuits 3031, 3032, 303
3, an access request signal 301 is generated. Additional information flags 3021, 3022, and 3023 are valid.

It is composed of 3 bits: R/W+mem/I0, and in the case of a memory read, it immediately goes to an access request, and in the case of a write or Ilo, it goes to an access request when the request signal 114 arrives. The combinational circuit 304 is
Access request signal 301° Reset signal 3/O. Ready signal 311. TI new state signal 314 TI new state signal 313 A state preparation signal TOTI30 for inputting the T2 state signal 312 and controlling the bus cycle.
5, TOT1306. Output TOT2307. A combination of input and output of this combinational circuit 304 is shown in FIG.

In FIG. 6, the active level is "1" in all cases, and "-" indicates not to refer to.

The external access bus cycle ends with two clocks of the TI state and T2 state. The T2 state always comes after the T1 state, but after the T2 state, if the ready is inactive, it enters a wait state, repeats the T2 state, and transitions to the T2 state or the T1 state in response to an access request. A transition from the T2 state to the TI state is regarded as a stop of the bus cycle, and the bus cycle stop signal 113 is activated to notify the instruction execution unit. flip flop 30
8 is a D flip-flop for switching TI, Tl, and T2 with a clock.

In the instruction decoding unit/O3, the next nop of the I/O instruction
FIG. 4 shows an example of a configuration for detecting commands.

In FIG. 4, when an I/O command is detected, an I/O command detection signal 40 becomes active only in the case of an /O command.
2 sets D flip-flop 404 and no
When an instruction is detected, Ilo and a nop detection signal 112 are generated by ANDing the nop instruction detection signal 403 and the I/O instruction holding signal 405, and the generated nop detection signal 112 is notified to the instruction execution unit.

In Figure 7, there is a nop instruction after the N no p instruction,
The pipeline operation when there is an out instruction after it is shown. This microprocessor has a five-stage pipeline of instruction fetch, instruction decode, address calculation, operand access, and instruction execution, and each stage is completed in one clock, and external access is completed in two clocks if there is no wait. shall be taken as a thing. The instruction execution unit executes the I/O instruction (2), activates the request signal in synchronization with the falling edge of the clock, and ends the execution of the (2)/O instruction (2). Since this is the nop instruction (2) after the I/O instruction (2), the instruction decoding section makes the I/O&nop detection signal active, thereby causing n.

The instruction execution unit that was about to execute the p instruction ■ suspends execution of the nOp instruction ■ until the bus cycle stop signal becomes active. When the I/O write cycle of the out instruction (2) is completed and the T2 state changes to the idle state TI state, the bus cycle stop signal becomes active and the nop instruction (2) is executed.

In this way, with one nop instruction, it is possible to provide a margin of several clocks between the previous I/O access and the subsequent I/O access.

In conventional pipelined microprocessors, ■
In order to obtain /O recovery time, the /O instruction and I/O
It was necessary to insert many nop instructions between instructions, but in this embodiment, only two signals and the minimum number of nop instructions are required.
The recovery time of Ilo can be guaranteed with the op instruction.

〔Effect of the invention〕

As explained above, in conventional pipelined microprocessors, the nop instructions inserted to obtain the 1/O recovery time have no meaning, and many nop
However, in the microprocessor of the present invention, no instructions are required in accordance with the I/O recovery time of peripheral devices.
If you only need to insert a few p instructions from the beginning, and you do not need I/O recovery time because the ports are different for consecutive I/O accesses, you can perform consecutive I/O accesses by not inserting nop instructions. /O access is possible, so the program size φ can be reduced, and the performance of the computer system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional microprocessor, and FIG. 3 is a block diagram of the bus control section shown in FIG. Figure 4 is a block diagram of the instruction decoding unit shown in Figure 1, Figure 5 is a block diagram of the instruction execution unit shown in Figure 1, and Figure 6 is a truth table of the combinational circuit in Figure 2. 7 is a diagram of the pipeline operation in FIG. 1, and FIGS. 8 and 9 are diagrams of the pipeline operation in the conventional technology. /O1...Bus control unit, /O2...Briefetch unit, /O3...Instruction decoding unit, /O4...Instruction execution unit, /O5...External data bus, /O6...External Address bus, /O7...Internal data bus, /O8...
・Instruction fetch request signal, /O9...internal data bus 2.1/O...internal address bus, 111...instruction decode information, 112...Ilo and nop@ output signal,
113...Bus cycle stop signal, 114...Request signal, 301...Access request signal, 302...
...Selection signal, 303...Pointer circuit, 304.5
07...Combination circuit, 305...State preparation signal TOT11306...State preparation signal TOT 1
．． 307...State preparation signal TOT2.308,4
04...D flip-flop, 309...clear signal, 3/O...reset signal, 311...ready signal, 312...T2 state signal, 313...T
1 state signal, 314...TI state signal, 31
5... Address latch, 3011... Address register 013012... Address register 1.3013
... Address register 2.3021 ... Additional information flag 013022 ... Additional information flag 1.3023.
...Additional information flag 2.3031...Combination circuit 0
．． 3032...Combination circuit 1.3033...Combination circuit 2.401...Instruction Korg, 402...I
/O command detection signal, 403... nop command detection signal,
405...I/O command holding signal, 406...AND
Gate, 501... Selector, 502... Micro address register, 503... Micro program ROM 1504... Micro instruction latch, 505...
- Microinstruction decoder, 506... Incrementer, 508... Signal extracted from control information stored in latch, 509... Output signal of incrementer, 5/
O...Control signal, 511...Select signal.

Claims (1)

[Claims] 1. An instruction decoding unit, a bus control unit, and an instruction execution unit are provided, and the instruction decoding unit notifies the instruction execution unit that an I/O instruction and a nop instruction are consecutive. A microprocessor comprising: a first signal; and a second signal that notifies the instruction execution unit from the bus control unit that a bus cycle has stopped. 2. The microprocessor according to claim 1, wherein when a first signal in a nop instruction is active, execution of the nop instruction is delayed until a second signal becomes active.