JPS6049337B2 - Pipeline control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pipeline control system, and more particularly to a pipeline control system that requires synchronization between an instruction fetch section and an instruction execution section.

A conventional data processing device using a pipeline control method will be explained using FIGS. 1 to 6.

FIG. 1 is a block diagram of a pipeline control type data processing apparatus, and this pipeline control type is particularly used in large office machines. Its structure consists of an instruction unit 11 that reads instructions, an arithmetic unit 12 that executes the read instructions, a storage control unit 13, a main memory 14, and an input/output bus (I/O-BUS) address bus A-BUS) data 5. (D-BUS) and an inter-unit interface UINT. The instruction unit 11 has the logical structure shown in FIG. 2, and includes a program counter for storing the main memory address where the instruction word is stored, a base register for creating operand addresses, an index register, etc. It consists of a register group 21 for storage, an address adder 22 that adds one of the register groups 21 and a part of the instruction word and outputs the result via an address bus A-BUS, and an instruction control unit 23 that controls these. . Therefore, this instruction unit 11
The operation is as follows: (1) Send the contents of the program counter to the address bus A-BUS and read the instruction word.

Furthermore, the program counter is incremented (up).
do. (2) In accordance with the read instruction word, the address of the operand is calculated by the address adder 22 in the specified method and sent to the address bus A-BUS.

(3) Notify the operation unit 12 of the completion of the operation of the instruction unit through the inter-unit interface UINT, and start the unit 12.

It is divided into three functions, which are executed sequentially.

FIG. 3 shows the logical structure of the arithmetic unit 12, which includes register groups 31 and 3 that store various arithmetic registers.
2, an arithmetic unit 33, and an instruction execution control unit 34 that controls these. Upon receiving notification from the instruction unit that the operation of the instruction unit 11 has finished via a signal from the inter-unit interface UINT, the execution operation is started. Next, the relationship between the instruction unit 11 and the arithmetic unit 12 will be explained as follows.
This will be explained using Figures 6 to 6.

FIG. 4 is a flowchart mainly showing the status execution of the instruction unit 11, which operates while communicating with the arithmetic unit 12 in the following steps.
3(1) Instruction unit 1
Determination of start of state size in step 1.

The point in time when the static size can be started is determined by the instruction execution (processing) of the arithmetic unit 12. For example, the program counter in the register group 21 in the instruction unit 11; For instructions that change the base register, index register, etc. (conditional branch, unconditional branch, subroutine branch, register rewrite, etc.), the study size can be started after the contents of the register are changed. (Ii)
Determine whether or not there is an interrupt, and if there is an interrupt, do not execute the state size and update the program counter.

S(iii) Execution of state size.

The command unit 11 is capable of starting the state size,
State size is executed only when there is no interrupt.
The details of the operation have been described above and will therefore be omitted. (Iv) Determining whether the arithmetic unit 12 is being executed.

O Depending on whether the arithmetic unit 12 is executing the previous instruction,
It is determined whether the execution result of the instruction unit 11 is transferred to the arithmetic unit 12 to execute the instruction. Arithmetic unit 12
When the previous instruction finishes executing, the current instruction continues to be executed, and the instruction unit 11 prepares to fetch the next instruction.In this way, the instruction unit 11 and the arithmetic unit 12 are always It communicates and continues to operate to achieve vibration line control.

FIG. 5 is a diagram showing how the vibration line is controlled along the flow of time t. The operation of the instruction unit 11 (state size) is the operation of the arithmetic unit 12 (execution of previous instruction)
If it is slower than (
If the completion of the operation of the instruction unit 11 is earlier than the completion of the operation of the arithmetic unit 12, the start of the next operation of the instruction unit 11 is awaited (section T2 in the figure). That is, the completion of the state size of the process N coincides with the completion of the execution of the previous instruction N-1 of the arithmetic unit 12, and the case where the process of the arithmetic unit 12 is seamlessly performed indicates time t1, and the state size of the process N
+1 indicates the hold time when a hold occurs between the processing unit 12 and the previous instruction processing N. At this time, process N+2 cannot start state size until the previous instruction N+1 ends. Furthermore, if the state size N+3 of the next instruction unit is completed early, the duration of section T2 is reached. As described above, the instruction unit 11 and the arithmetic unit 12
In each case, a hold occurs in various cases depending on the command, and in many cases, this hold is synchronized in terms of timing by an inter-unit interface signal.

FIG. 6 shows the basic signals of the interface between the two units, including a signal (EUSTAR) that notifies the operation unit 12 of the end of the state size of the instruction unit 11
T), and a signal (IUSTART) that notifies the instruction unit 11 of the completion of instruction execution by the arithmetic unit 12.
These two signals provide synchronization between both units. On the other hand, as mentioned above, many large office machines are equipped with vibration line control, and they make full use of advanced technologies such as instruction word stacking and main memory interleaving. The internal logic of the arithmetic unit 12 is quite complex, and the number of interface signals between the two units is also quite large.

As a result, when each of the two units is configured with one LSI chip, the number of interface signals between the two chips increases. However, it is difficult to realize this because of restrictions on the number of package pins. The present invention has been made in view of the drawbacks of the prior art described above, and its purpose is to provide an instruction unit,
It is an object of the present invention to provide a vibe line control system which reduces interface signals between two chips when each arithmetic unit is constructed of a single circuit such as one LSI chip, and further corrects a deviation 5 in their respective operations.

In order to achieve the above object, the present invention provides that the instruction unit of an instruction unit of a microprogram-controlled data processing device that is capable of vibrating is completed only when the instruction execution of the arithmetic unit of the data processing device is completed before the state size of the instruction unit. It is characterized in that it modifies the generated microprogram branch address, converts it to a fixed address, and stores a non-executable microinstruction at the fixed address, thereby bringing the arithmetic unit into a holding state.

Preferred embodiments of the present invention will be described in detail below with reference to the drawings.

Note that in the following explanation, the expression "chip" is used, but this is because it is based on the premise of LSL. The internal functionality of the chip is almost identical to the previously mentioned units. Of course, since the unique technology of the present invention is added, they are not substantially the same. FIG. 7 is a block diagram of a data processing device capable of controlling the vibe line and incorporating a microcycle synchronization device according to the present invention.

This data processing device is composed of an instruction fetch chip 71, an instruction execution chip 72, a microinstruction address register 73, and a microprogram memory 74 that is accessed by an address sent from the register 73 through an address bus ADDR-BUS. Part 1 for controlling the instruction fetch chip 71 uses a microprogram branch address generated from within the instruction fetch chip 71 in a time-sharing manner, and supplies the microprogram branch address to the microinstruction address register 73 through the microinstruction bus MI-BUS1. In addition, the instruction execution chip 72
is always controlled by part E of the microprogram memory 74 through the microinstruction bus MI-BUS2, and outputs the mode (count/load) control signal e1 of the microinstruction address register 73 and the instruction execution end signal 0; It is supplied to the fetish tip 71. Although not directly related to the present invention, the instruction fetish chip 71
The address output of the instruction execution chip 72 and the data input/output of the instruction execution chip 72 are connected by a common data◆address bus DA-BUS, so that data can be exchanged between the chips.
It is assumed that the instruction fetch chip 71 and the instruction execution chip 72 are independently controlled by the I and E sections of the microprogram memory 74, respectively, and the state size control in the instruction fetch chip 71 is controlled by hardware rather than by microinstructions. Since the hardware has no direct influence on the present invention, it will be omitted. Next, the microprogram branch control section of the instruction fetch chip 71 will be explained using FIG.

This control unit uses the microinstruction bus MI-BU for time-sharing control.
Microinstruction input buffer 8) 1 from Sl, output buffer 82 for sending microprogram branch address,
It consists of a microinstruction register 83 and its decoder 84, a microcycle synchronization device 85, which is the core of the present invention, and a (macro) instruction register 86. Normally, the microinstruction bus 5MI-BUSl operates in the input direction, and the microinstruction read from the microprogram memory 74 is placed in the microinstruction register 83 via the input buffer 81, and the microinstruction decoder 84 outputs the instruction fetch chip. However, when the instruction fetch chip 71 wants to start the state size, it sends a microinstruction to start the state size through the input buffer 81, the microinstruction register 83, and the microinstruction decoder 84. A start signal s is generated and communicated to the microcycle synchronization device 85. If there is no interrupt due to the interrupt signal 1, a signal n that prohibits the execution of the following microinstructions is returned to the decoder 84, and the microcycle synchronization device 85 The synchronizer 85 creates the starting address of the microprogram according to each instruction from the instruction code of the instruction register 86 of the macro, and outputs the start address of the microprogram to the output buffer 82 according to the previous instruction execution end signal 0 of the instruction execution chip 72. is released (at this time, the I part of the microprogram memory 74 is prohibited) and the microinstruction register 7 is opened.
Set the number to 3. However, when the state size operation of the instruction fetch chip 71 is not completed, the branch address output of the microcycle synchronizer 85 is a fixed address, and until the state size is completed, the instruction execution chip 72 executes the microinstruction (invalid) at that fixed address. The execution command) is continued to be executed and synchronized with the command fetch chip 71. FIG. 9 is a detailed diagram of a microcycle synchronizer 85 according to the present invention.

The device 85 includes an inverter 91 for interrupt signal 1, a NAND gate 92 for obtaining a state size start signal, a flip-flop 93 for displaying the state size start, and a NAND gate 9 for obtaining an interrupt acceptance signal. Flip-flop 95, AND gate 9 with 3 inputs and 5 for changing the instruction code of the instruction register 86
Consisting of 6a-h. 9-bit branch address B-ADD
The most significant bit of R is formed by the signal of the Q output terminal of the flip-flop 95, and the second and subsequent bits are formed by the signal of the Q output terminal of the flip-flop 95.
It is formed with an output of ~96h.

When the microinstruction instructs to start the state size, the set signal s is input, and at this time, if the interrupt signal 1 is "0" (no interrupt), the flip-flop 93 is set via the NAND gate 92, and the flip-flop 95 is set. Not done. Therefore, the 5 instruction codes (operand codes) in the instruction register 86 are, for example, (11101000
), the Q terminal is "0" until the end signal e generated by the hardware upon completion of the state size is input to the flip-flop 93, so the AND gate groups 96a to 4h are in the off state. , and since the Q terminal of the flip-flop 95 is 40°, the microprogram branch address is (a) 00000000) and 0.
Pointing to the address. When the end signal e is input, the flip-flop 93 is reset, and as a result, the AND gates 96a to 96h are turned on, and the branch address becomes (0111
01000) and an address corresponding to the instruction code (note that the first bit of this address is determined by the signal at the Q terminal of the flip-flop 95, so it is "0"). If 66F3 (with an interrupt), only the flip-flop 95 is set, and as a result, the gate group 96a-h remains off, so the branch address is independent of the contents of the instruction register 86 (
100000000).

Then, the flip-flop 95 is reset by the reset signal r in response to the next microinstruction, and returns to the initial state.
Further, the Q terminal output of the flip-flop 93 serves as a microinstruction decoding prohibition signal n, and as a result, the prohibition signal n is generated only when there is a start signal s and only an interrupt signal. Next, the instruction execution chip 7
The details of the second side will be explained using FIG.

According to the present invention, the chip 72 has a microinstruction bus MI.
- Input buffer 1 that takes in micro instructions from BUS
01, microinstruction register 102, branch control circuit 10
It is 3. The mode (count/load, increment/jump) control signal ' of the microinstruction address register 73 placed in the microinstruction register 102 via the input buffer 101 and the instruction execution end signal 0 are output, and the determining factor of the signal ' One of the test codes t inside the instruction execution chip 72 is taken in as follows. Before entering into a detailed explanation of the branch control circuit 103, a microinstruction consisting of 12 bits that controls the instruction execution chip 72 will be explained first.
Shown in Figure 1. There are four types (operations, conditional branches, literals, and others), but normally if the first bit position is 660'', the microinstruction address register 73 is in the increment mode, and if it is ``1'', it is jump mode;
, when the content of the second bit position is (01), the 11th,
The end of instruction execution is indicated only when the E field at the 12th bit position is "°1". The operation of the branch control circuit 103 based on this microinstruction will be explained using FIG. 12.
The circuit is an inverter 12 at the first bit position (BitO).
1, the output, 1st bit position (Bitl) 11th, 1st
It consists of a NAND gate (decoder) 122 for 2 bit positions (Bitll), a gate 123 for determining whether or not to change the mode, and an exclusive OR gate 124 for changing the mode. BltO is supplied to one input of the exclusive OR gate 124, and as long as the output of the gate 123 is ゜゜0゛, the information of BitO is sent out as the mode control signal' of the microinstruction address register 73 without being changed. The mode is changed at the end of instruction execution (Bit
When the increment mode is changed to jump mode when O = "0゛, Bitl, Bitll = "R5), and when conditional branching (BitO = 66r', Bitl = 4'0)
0, when the test bit TB is "0", that is, when t=0, that is, when the condition is not satisfied), the jump mode is changed to the increment mode. It goes without saying that when the signal e is 0, it indicates the increment mode, and when it is 1, it indicates the load mode.The instruction fetch chip 71 and the instruction execution chip 72 have been explained above, but the relationship between these two will be explained below. The time chart shown in FIG. 13 is for the case where there is no interrupt (1 = “゜0゛)” and when the instruction execution chip 72 outputs the instruction end signal 0 while the instruction fetch chip 71 is executing the state size. Address O becomes the branch address (Example, Case)
, indicates that after the state size is completed, the branch address will be in accordance with the instruction code (Example, Case 2).

FIG. 14 shows this expressed on the microprogram memory 74. The part indicated by the arrow on the right side shows the code content of the corresponding address. Now, if the microinstruction at address β issues an instruction execution end, if the state size is completed, it jumps directly to the instruction processing start address α as shown in g,
If the state size is not completed, first jump to address O,
The microinstruction continues to issue no execution and execution completion, waits for the state size to complete, and jumps to address α. On the other hand, if there is an interrupt, the state size does not start, so when the instruction execution ends, it jumps to addresses 10 to 0 and starts the interrupt processing microprogram. As described above, according to the illustrated embodiment, the interface signal between the instruction fetch chip and the instruction execution chip is minimized;
Moreover, smooth microcycle synchronization is possible.

Although the present invention has been described above as an example of an LSI implementation, it is also applicable to a general circuit configuration having two functions: an instruction fetch section and an instruction execution section.

In some cases, a circuit configuration in which the synchronization device is taken out independently may also be applicable. As described in detail above, according to the present invention, it is possible to minimize the interface signal between the two units controlling the vibe line and to achieve smooth microcycle synchronization.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a general vibe line control data processing device, Fig. 2 is a block diagram of the instruction unit, Fig. 3 is a block diagram of the arithmetic unit, and Fig. 4 is a state size flow diagram of the instruction unit. , FIG. 5 is a diagram showing an actual example of vibration line control, FIG. 6 is a diagram showing basic interface signals between two units, FIG. 7 is a diagram showing a vibration line control data processing device according to an embodiment of the present invention, and FIG. 8 is a diagram showing the microprogram branch control section of the instruction fetch chip, FIG. 9 is a detailed explanatory diagram of the microcycle synchronization device according to the present invention, and FIG. 10 is a diagram showing the periphery of the branch control circuit of the instruction execution chip. Fig. 11 is a diagram showing the microinstruction format of the instruction execution chip, Fig. 12 is a detailed explanatory diagram of its branch control circuit, Fig. 13 is a time chart of branch address generation,
FIG. 4 is a diagram showing the movement of microinstructions on a microprogram. 91,121...Inverter, 92,94,1
22...Nand Gate, 93,95...
Flip 5 flop, 96a-h...AND gate, 123...gate, 124...exclusive OR gate.

Claims (1)

[Scope of Claims] 1. A pipeline control system that includes an instruction fetch section and an instruction execution section that independently perform instruction fetch and instruction execution in a microprogram area, and that control both while maintaining synchronization through pipeline control. In this case, the instruction execution section is always controlled by a microprogram,
If the instruction execution process of the instruction execution unit is completed first during the execution of the state size of the instruction fetch unit, the state size is stored in advance at a specific address in the microprogram memory according to the address specification from the instruction fetch unit. A pipeline control system in which a non-executable microinstruction is given to the instruction execution unit to cause the instruction execution unit to perform non-execution processing, and the instruction fetch unit is synchronized with the instruction execution unit when the state size ends. 2. In the pipeline control method, which is equipped with an instruction fetch unit and an instruction execution unit that independently perform instruction fetch and instruction execution in the microprogram area, and in which both are controlled while being synchronized by pipeline control, the above-mentioned instruction The execution unit is equipped with a function that detects the end of instruction execution and generates an instruction flag to change the flow of the microprogram; A microinstruction for processing an interrupt request for an address is accessed and fetched under the control of the instruction flag, and the instruction execution unit executes the instruction execution process while the instruction fetch unit itself is executing the state size. When detected, a function is provided to access and fetch a non-executable microinstruction at a specific address different from the specific address above under the control of the instruction flag; When the instruction execution unit executes the execution process and the state size being executed ends, the end of the instruction execution process of the instruction execution unit is detected while the instruction fetch unit is executing the state size. A pipeline control method that synchronizes the instruction fetch section and instruction execution section of the system.