JPH0317135B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a programmable controller used for plant process control, and in particular, to a programmable controller suitable for use in control requiring high speed and high functionality. Regarding control method.

[Background of the invention]

Our programmable controller started with simple sequence control. However, in recent years, as the field of application has expanded and the need to process numerical operations at high speed has led to the adoption of parallel processing methods for prefetching instructions and data and executing instructions, including increasing the speed of the used elements themselves. There is. However, due to the increasing complexity of objects to be controlled, there is a demand for more fine-grained control of parallel processing and control methods of high-performance processing such as processing multiple data with one command.

Here, FIG. 1 shows an example of a conventional programmable controller. First, I will give an overview. This controller employs a control system that pre-reads commands and data. Pre-reading means reading in advance the instructions and data that will be needed next in the currently executing operation.

FIG. 2 shows the format of instructions used in this controller, which are stored in the program memory 1 shown in FIG.

FIG. 3 shows the format of microinstructions when the instructions in FIG. 2 are further executed by a microprogram.
It is stored in memory 8. The contents of the control code of this microinstruction are shown in Table 1 below.

Table 1 102...Program counter update (+1) 103...Memory address register update (+1) 104...D register write 105...Set data in write data register 106...Data read start 107...Data write start 108...JMAP (next) (execution of the command) Next, FIG. 4 shows an operation time chart of each part of the controller described above.

The major feature of this control method is that it has a data prefetch permission bit (hereinafter abbreviated as POF bit) in the instruction, and that the program
A memory 1 and a data memory 2 exist independently, and two stages of a first instruction register 3 and a second instruction register 4 are provided as instruction registers, and the address part of the first instruction register 3 is used as a memory address.
This is the point where it is connected to the register 5.

The operational characteristics will be explained below. The instructions stored in the second instruction register 4 in FIG.
The command is applied to an arithmetic circuit 9 via a counter 7 and a microprogram memory 8, and an arithmetic operation is executed according to the instruction. At this time, the next instruction to be executed has already been stored in the first instruction register 3,
When the POF bit 101 (FIG. 2) is "1", data reading for this instruction (that is, pre-reading of data) is performed. On the other hand, the program counter 6 is
The next instruction following the currently executed instruction is being read. Then, when the currently executed instruction ends and the execution of the next instruction begins, the instruction data enters the read data register 18, and the next instruction that was being read is stored in the first instruction register 3. There is.

A time chart of the above operation is shown in FIG. In FIG. 4, A, B, C, . . . indicate instructions, and it can be seen that they are processed in parallel.

In the above system, the operations of each part of the program memory interface circuit 10, data memory interface circuit 11, first instruction register 3, second instruction register 4, and arithmetic circuit 9 are as follows.
Since everything proceeds in synchronization with the JMAP signal 108 that indicates the break between each instruction, there is an advantage that the circuit and concept are simple. Here, the JMAP signal is JUMP/
This is an abbreviation for MAP signal, which is used to convert specific bits of an instruction into a microprogram address, and is a signal that specifies the start address and executes the next instruction.

Now, in the above method, it is necessary that the number of data processed by one instruction is 1 or a fixed number, and any number of data can be processed by one instruction, for example, when double-length operations are mixed, etc. In this case, speeding up is hindered by the inability to process it.

Next, details of the configuration of the controller shown in FIG. 1 will be shown below. As mentioned above, the program memory 1 stores program instructions as shown in FIG. Data to be operated on is written to and read from the data memory 2.

Instructions read from program memory 1 are stored in first instruction register 3 and then transferred to second instruction register 4. The format of this instruction is as shown in FIG. 2, and is composed of an instruction code section 112 indicating the type of instruction, a POF 101, and a data address 113. POF10
1 is "1" for an instruction to read and process data, "0" for an instruction to output data,
Regarding the “1” instruction, before executing the operation,
Data can be read ahead.

The address for reading an instruction from the program memory 1 is given by a program counter 6, and is counted up using a program counter update signal 102 every time one instruction is completed. Also, when reading instructions, program memory 1
The program memory that interfaces with
The interface circuit 10 generates the read timing shown in FIG. The arrows in FIG. 4 indicate the order of signal changes. A PFE (instruction prefetch start) signal 114 activates the program memory interface circuit 10 to start reading.

The instruction decoder 5 decodes the instruction code entered into the second stage of the instruction register, and sets in the microprogram counter 7 the starting address where the microprogram for processing the instruction is stored.

The microprogram counter 7 provides the address of the microprogram to be executed to the microprogram memory 8 in order to execute the microprograms sequentially.

Each time a microinstruction (FIG. 3) is called, the microprogram memory 8 stores the contents defined in Table 1, that is, the operation code, the microprogram address to be executed next, and 102 to 1
The hardware is operated as shown in 08.

Next, the arithmetic circuit 9 performs various operations including addition and subtraction according to the operation code of the microinstruction. The inside of the arithmetic circuit 9 includes accumulators A91 and AL92, a T register 93 used for temporary purposes for arithmetic operations, an arithmetic unit 94, and a carry for the arithmetic result, which is used to temporarily store the carry of the arithmetic operation, etc. It consists of a carry flag 95 to be used. Outside the arithmetic circuit 9, there is a D register 12 between the read data register 18 and the arithmetic circuit 9, which is used for data exchange. The internal data bus 115 is used as a path for exchanging data between the arithmetic circuit 9 and its peripheral registers. data·
Addresses for reading and writing from memory 2 are given from memory address register 21. memory·
There are two ways to set an address in the address register 21. First, there is a data lookahead method in which the address field of the first instruction register 3 is directly set, and the second method is to provide it from the arithmetic circuit 9. . The above switching is performed by the switch 13, and the data prefetch condition, that is, the POF signal 1 of the instruction set in the first stage 3 of the instruction register when the instruction prefetch signal (PFE) 114 is applied.
When 01 is "1", the address part of the first stage 3 of the instruction register is directly set in the memory address register 21.

The read data register 18 contains data.
Data read from memory is set.
The timing to be set is when the response signal 116 of the data memory 2 is returned.

Data to be written to the data memory 2 is set in the write data register 14, and the data memory interface circuit 11 is activated to execute data writing.

Data memory interface circuit 11
also works when reading data and generates the timing shown in FIG.

Clock circuit 15 generates a clock signal 117 for executing the microprogram.

In addition, JP-A-50-24044, JP-A-55-
Although Japanese Patent Publication No. 43604 also describes techniques related to prefetching of instructions, none of them allows prefetching of instructions and internal operations to be performed in parallel.

[Purpose of the invention]

An object of the present invention is to provide a programmable controller that can perform prefetching of instructions and data and internal arithmetic processing in parallel.

[Summary of the invention]

In order to achieve the above object, the present invention prefetches instructions stored in a program memory and data necessary for operations stored in a data memory, and executes operations in an arithmetic circuit from a microprogram based on the instructions. In a programmable controller that executes a programmable controller, a first timing signal generating means generates a timing signal specifying the time required to read the prefetched instruction after executing the prefetch of the instruction; a second timing signal generation means for generating a timing signal specifying the time required to read data; an internal processing command means for instructing internal processing to the arithmetic circuit when each of the timing signals is generated; and an internal processing command means for receiving each of the timing signals. , a programmable controller characterized in that it comprises a control means for stopping the progress of the microprogram for a time specified by each timing signal.

According to the present invention, even in a process that handles multiple pieces of data with one instruction such as a double word length instruction,
Even during prefetching of instructions, prefetching of data, and reading of multiple data, internal calculations can be performed in parallel, and therefore processing speed can be improved.

[Embodiments of the invention]

Next, one embodiment of the programmable controller according to the present invention will be described based on the drawings. Examples of the present invention are shown in FIGS. 5 to 10, and FIGS.
Parts that overlap with those in FIG. 4 are given the same reference numerals, and detailed explanation thereof will be omitted.

In Fig. 5, the conventional controller (first
The main differences from the figure) are indicated by thick lines. That is, in this embodiment, in addition to the configuration of the conventional controller (FIG. 1), after the prefetching of an instruction is executed, a timing signal (set signal 111) specifying the time required to read the prefetched instruction is generated and immediately started. a second timing signal generating means for generating a timing signal (set signal 110) that defines the time required to read the prefetched data after prefetching the data; and a second timing signal generating means for generating each of the timing signals. The microprogram 8 is provided with an internal processing command means for instructing the internal processing to the time calculation circuit 9, and further includes a timing for starting prefetching of instructions from the program memory 1, a timing for waiting for instruction readout, and a timing for prefetching data from the data memory 2. The start timing and the data read wait timing are each independently controlled by a microinstruction from the microprogram memory 8 (specifically, the set signal 110,
111) is provided.

This control means includes an instruction synchronization flip-flop 16 and a data synchronization flip-flop 17 for synchronizing the program memory 1 or data memory 2 and the arithmetic circuit 9, and a NOR circuit for NORing the outputs of these flip-flops. 19 and this NOR
The circuit 19 includes a switch 20 which inhibits the output of the clock signal 117 from the clock circuit 15 to the microprogram counter 7 based on the output of the circuit 19.

In this embodiment (FIG. 5), the program memory 1 stores programs as shown in FIG. 8, for example. An example of the instruction specification is shown in Table 2 below.

Table 2 Instruction specifications (1) LDD (load double) Set the data at address D100 to the AL register.

Set the data at address D101 to the AU register.

(2) ×2D (double double) Double the contents of the AL and AU registers to create AL and AU
Set to .

However, the data in the AU register is treated as the upper digits of AL.

(3) SUBD (subtraction double) Subtracts the data at addresses D300 and D301 from the contents of the AL and AU registers and sets them in the AL and AU registers.

However, the data in the AU register, address D301, is treated as the upper digit.

Further, the read timing of the program memory interface circuit 10 when reading an instruction is shown in FIG. 7a, and the write timing is shown in FIG.
Shown in Figure b. The arrows in FIG. 7 indicate the order of signal changes.

Furthermore, in the microprogram memory 8,
A microinstruction in the format shown in Figure 6 is stored, and each time a microinstruction is called, the contents defined in Table 3 below are stored, including the operation code, the microprogram address to be executed next, and (1) - Operate the hardware as shown in (11).

Table 3 102...Program counter update (+1) [(PC)+1→PC] 103...Memory address register update (+1) [(MAR)+1→MAR] 104...D register write [(RDR)→D] 105... Set data in the write data register 109...DFE (start reading data ahead) [DFE] 106...Start reading data [Read] 107...Start writing data 110...Set data synchronous flip-flop
[DWRQ] 111...Set instruction synchronous flip-flop [PWRQ] 108...JMAP (Execute next instruction) [JMAP] 114...PFE (Start prefetching of instruction) [PFE] RDR: Read data register The operation will be explained next. . Instruction synchronous flip-flop 16 operates as follows. First, in a state where the instruction prefetch start signal (PFE) 114 is applied from the microprogram memory 8 to the program memory interface circuit 10 to execute prefetching, the set signal (PWRQ) is sent from the microprogram memory 8. 111 is applied to the instruction synchronous flip-flop 16, the instruction synchronous flip-flop 16 is set;
The switch 20 is opened through the NOR circuit 19, and the clock signal 117 from the clock circuit 15 is inhibited until reading of the instructions from the program memory 1 is completed, and the microprogram is placed in a waiting state. The operation of the data synchronous flip-flop 17 is similar to that in which the data memory interface circuit 11 receives the data prefetch start signal (DFE) 1.
09, or if the data synchronous flip-flop set signal (DWRQ) 110 is applied while activated by the data read start signal 106,
Clock signal 117 until data reading is completed.
is prohibited and the microprogram enters a wait state.

Next, the operation will be explained using the example program shown in FIG. The specifications of the instructions LDD, 2D, and SUBD described in this program (FIG. 8) are as shown in Table 2, and an example of a microprogram for executing each instruction is shown in FIG. The mnemonic in FIG. 9 is shown in parentheses along with the operation definition of the microprogram in FIG. 6.

Here, the content of ( ), for example, (D) is "D
"Register contents" is indicated, and "→" indicates the direction of data transfer. In Figure 9, the microprogram addresses are discrete for each instruction because each instruction is microprogrammed and stored at a fixed address, and the connection from one instruction to another during execution is teeth
This is done using the instruction decoder 5 and microprogram counter 7 in JMAP. In addition, in Fig. 9,
The part surrounded by a dotted line indicates that prefetching is performed and processing is performed in parallel with the calculation. Figure 10 shows a time chart when this example program is executed.

In FIG. 10, times T ₅ to _{T 13} indicate the time period during which the LDD instruction is executed, and the reading of the second word data starts at T ₆ and waits until the reading ends at T ₇ to _{T 9} . This indicates the state in which the In this case, parallel processing is not performed, but T ₁₀ ~ _{T 13}
It can be seen that the reading of the next instruction, the SUBD instruction, and the internal processing of setting data to the AU are being processed in parallel. That is, SUBD
The process of (RDR)→D is performed as an internal process of the arithmetic circuit 9 until the prefetching of the instruction is completed. Furthermore, from T ₁₄ to _{T 17} , a 2D instruction is executed, and in this case, the instruction prefetch and data prefetch timing can be performed as early as T ₁₄ , so
After performing the calculations from T ₁₄ to _{T 16} , synchronization is achieved at T ₁₇ , so it can be seen that the waiting time for the memory is short and efficient parallel processing is performed.

In this way, by finely controlling the parallel processing of instructions and data prefetching and instruction execution,
It is possible to perform parallel processing of instructions that process multiple data.

〔Effect of the invention〕

According to the present invention, the prefetch processing of instructions and data and the internal processing of the arithmetic circuit can be executed in parallel, thereby contributing to an improvement in processing speed.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional programmable controller, Figure 2 is an explanatory diagram showing an example of an instruction format output from a program memory, and Figure 3 is an example of a conventionally used microinstruction format. 4 is a time chart showing the operation of a conventional programmable controller, FIG. 5 is a block diagram showing an embodiment of the programmable controller according to the present invention, and FIG. 6 is a diagram showing the microinstructions used in the present invention. FIG. 7 is an explanatory diagram showing the format, FIG. 7 is a time chart showing the operation of the interface, FIG. 8 is an explanatory diagram showing an example of the program stored in the program memory, and FIG. 9 is the contents of the microprogram in the present invention. FIG. 10 is a time chart showing the operation when the program shown in FIG. 8 is executed. 1...Program memory, 2...Data memory, 3...First instruction register, 4...Second instruction register, 5...Instruction decoder, 6...Program counter, 7...Microprogram counter, 8...Microprogram memory , 9... Arithmetic circuit, 10
...program memory interface circuit,
11...Data memory interface circuit,
14...Write data register, 15...Clock circuit, 16...Instruction synchronous flip-flop, 17...
Data synchronous flip-flop, 18...read data register, 19...NOR circuit, 20...switch.

Claims (1)

[Claims] 1 In a programmable controller that executes an operation in an arithmetic circuit from a microprogram based on the instructions while prefetching the instructions stored in the program memory and the data necessary for the operation stored in the data memory, a first timing signal generating means that generates a timing signal that specifies the time required to read the prefetched instruction after execution of the prefetched instruction; and a timing signal that specifies the time required to read the prefetched data after the data prefetch is executed. second timing signal generating means for generating a second timing signal; internal processing command means for instructing the arithmetic circuit to perform internal processing when each of the timing signals is generated; A programmable controller characterized by comprising a control means for stopping the progress of a microprogram.