JPS595354A - Data processing device - Google Patents

Abstract

PURPOSE:To make an apparent executing speed of a machine language instruction variable, by using an instruction group consisting of plural microinstructions as one processing unit, and inserting a dummy time in accordance with whether a set condition exists or not, or proceeding to the following processing without inserting it. CONSTITUTION:Plural M instruction groups are stored in a control storage CS 1, and a CS control part 2 controls updating and readout of a CS address. A processor controlling part 3 controls each part of a computer by a mu-instruction read out of the CS 1, and an arithmetic part 4 operates the number of calculations in a work register 5 in accordance with a command of the processor controlling part 3. Data of a dummy time setting part 6, a PSW register 7, a general register 8 and a main storage 9 are set to the work register 5. The dummy time setting part 6 stores information indicating whether a dummy time is inserted or not, at the time of loading a mu program. In this way, an apparent executing speed of a machine language instruction can be made variable by inserting the dummy time as necessary.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a data processing device using a microprogram control method, in which the time required to execute machine language instructions or input/output commands can be made variable. It is something.

[Prior art and problems]

When a program is created, it has conventionally been done to verify the program by running the program on a computer. However, a program is not necessarily executed only by a computer of the same type as the computer used during verification, but the program is also executed by a computer of a different type, but in such cases, Internal operation may differ. FIGS. 1 and 2 show an example of operation when the same software is run on different central processing units and the same channel/input/output device. CPU in FIG. 1 and FIG.

and OPU indicate a central processing unit, OH indicates a channel 6, an input/output device, and A and B indicate machine language instructions, respectively. S
When the IC+ command is issued, the input/output device side executes input/output chaos. After issuing the SI command, the central processing unit executes the next machine language commands A, B, and so on. When the input/output operation lane 1 is completed, the input/output device side notifies the central processing unit of the completion of the input/output operation lane y using an interrupt. In FIG. 1, an input/output interrupt is performed at the end of machine language instruction B, and in FIG. 2, an input/output interrupt is performed at the end of machine language instruction A.

Note that the execution speed of the machine language instructions of opu is the same as that of CPU,
It is assumed to be slower. Therefore, when the same program is executed on computers with different machine language instruction execution speeds, it is necessary to check whether the program operates normally in different operating environments. However, testing the normality of a program by executing it on a variety of different actual hardware significantly increases the burden of testing.

[Purpose of the invention]

The present invention is based on the above considerations, and aims to provide a 5K data processing device that can vary the apparent execution speed of machine language instructions using the same hardware. .

[Structure of the Invention] Therefore, the data processing device of the present invention is a data processing device using a microprogram control method, in which a microinstruction group consisting of a plurality of microinstructions is treated as one processing unit, and setting conditions are set for each core processing unit. If there is a dummy hour setting, the dummy hour is inserted, and the execution of the next processing unit is started after the processing for which the dummy hour has been inserted is completed. be.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 3 is a diagram explaining the present invention in detail, FIG. 4 is a diagram showing one embodiment of the hardware of the central processing unit for implementing the present invention,
FIG. 5 is a diagram illustrating the LH (Load Halfwora instruction) and the SH (Torθ Halfword) instruction. FIG. 6 shows an example of a microinstruction sequence for carrying out the present invention.

FIG. 1 is a diagram showing an overview of the present invention. In FIG. 1, CPU1' indicates a central processing unit.

In the embodiment shown in FIG. 1, a dummy time is inserted after the execution of one machine language instruction, and execution of the next machine language instruction B can be started after the dummy one hour has elapsed. By inserting or not inserting a dummy time, the apparent execution speed of machine language instructions can be varied.

FIG. 4 shows one of the hardware configurations of the central processing unit of the present invention.
It is a figure which shows an example. In FIG. 4, 1 is a control memory (hereinafter referred to as C8), 2) the turtle O8 control section λ' is a processor control section, 4 is an arithmetic section, 5 is a work register, 6 is a dummy time setting section, 7 8 is a PSW register, 8 is a general-purpose register group, 9 is a main memory 10, which is a machine language instruction, and 11 is a μ (micro) instruction group.

A plurality of μ instruction groups are stored in CB1.

The aS control unit 2 controls updating and reading of CS addresses. The processor control section 3 controls each section of the subtraction machine based on microinstructions read from day 0 to day 1. The calculation unit 4 calculates the calculation number in the work register 5 according to instructions from the processor control unit 3. In the work register 5, data of a dummy time setting section 6, a PSW register 7, a general-purpose register 8, and a main memory 9 are set. dummy·
The time setting section 6 stores information indicating whether or not dummy time is inserted. This storage operation occurs during initial microprogram loading. psw register 7
Various types of control information including next instruction execution address information are stored in .

FIG. 5 explains the LH instruction and the SR instruction. These instructions are machine language instructions. The LH command is the second
This is for setting the data on the main memory 9 specified by the contents of the operand section into the general-purpose register specified by the contents of the first operand section. In this case, the upper 16 bits of the general-purpose register are all set to "o". The 8H instruction is for storing the lower 16 pits of the general-purpose register specified by the contents of the first operand section in the storage location of the main memory 9 specified by the contents of the second operand section.

FIG. 6 shows an example of a microinstruction sequence for implementing the present invention. Note that this example is based on a case where an LH instruction is executed.

■ Execute the MS READ /J instruction, fetch the opcode from the main memory 9, and set it in the work register 5.

■ Execute branch instructions for each OP code and branch according to the contents of work register 5.

(2) Execute the MS READμ instruction, read the contents of the second operand part of the LH instruction from the main memory 9, and set it in the work register 5.

■ Execute the address calculation μ instruction and calculate the second operand address.

■ Executes the MSIAD 11 instruction and transfers data from main memory 9 to the second
Read the operand data and set it in the work register 5.

■ Execute the Me RFiAD X4 instruction and read the contents of the first operand part of the I and H instructions (general-purpose register address)
is read and set in the work register 5.

■ Execute the GRWR TKμ instruction and set the second override data in the work register 5 to the general-purpose register.

■ DUMMY R1! ! The G RBAD II instruction is executed, and the dummy time setting section 6 also reads data.

■ Check whether dummy time is inserted or not, and if YO2, perform O processing, and if NO, perform ◎ processing.

0 Branch to instruction fetch section.

■ Execute the no-operation μ command.

Execute the O no-operation μ command, then process 0 at 5゜ Note that ■
, ■ are processes commonly executed when all machine language instructions are executed, and processes ■ to O are processes specific to LH instructions.

In the embodiment shown in FIG. 6, the μ instruction reads whether or not there is a dummy time insertion instruction at the end of a machine language instruction, and if there is an insertion instruction, a no-operation instruction is executed. The hardware may be configured so that a dedicated μ instruction is executed, and if there is a dummy setting, the next μ instruction is fetched after a certain time delay. If you insert a dummy time check at 5 in Figure 6, you can change the execution time for each machine language instruction, and if you insert the processing of ■, @, and O immediately before the processing of ■, The overall execution time can be changed. Executing the dummy determination part of the processing in ■, ■, and O every time will degrade performance during normal operation, so check whether there is a need to insert a dummy when storing the initial microprogram, and if there is a need, , 08. Stores the microinstructions for performing the processing in ■, and does not store the microinstructions for performing the processing in ■ if there is no need. A microinstruction for performing the 00 processing next to the microinstruction (2) above may be located.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the apparent execution speed of machine language instructions can be made variable.

[Brief explanation of drawings]

1 and 2 are diagrams showing an example of operation when the same software is run on different central processing units and the same channel/input/output device, and FIG. 3 is a diagram illustrating the present invention in detail. FIG. 4 is a diagram showing one embodiment of the hardware of the central processing unit for implementing the present invention, and FIG.
Load Halfwor+i) command and BH (
Figure 6 is a diagram explaining the instructions (Japanese tore Halfword), one of the microinstruction sequences for implementing the present invention
This is an example. -Register, 6... Daξ- Time setting section, 7.
...PSW register, 8...General-purpose register group, 9...
- Main memory, 10...machine language instructions, 11...μ (micro) instruction group. Patent applicant: Fujitsu Ltd. Representative patent attorney: Yobu Kyotani CPLJ I CH/io C
pL12 CM/i.

Claims (1)

[Claims] In a microprogram control type data processing device, a microinstruction group consisting of multiple microinstructions is treated as one processing unit, and setting conditions are referred to for each processing unit, and if there is a dummy time setting, the dummy one hour is set. A data processing apparatus characterized in that the data processing apparatus is configured to start execution of the next processing unit after the processing unit in which the dummy time has been inserted is completed.