JPH0623953B2 - Arithmetic control method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a control method for an arithmetic unit by microprogram control, and particularly when a bit error (microphone error) is detected in control information at a step in the middle of a microprogram. The present invention relates to a method for controlling the progress / stop of an arithmetic cycle according to the characteristics of the arithmetic processing to be executed so that unnecessary delay does not occur.

[Conventional technology and problems]

FIG. 1 shows a schematic structure of a general micro-program control arithmetic unit. 1 is a micro program control unit, 2 is an arithmetic control unit, 3 is an arithmetic unit, and 4 is a control memory. The microprogram control unit is activated by an arithmetic instruction and executes a microprogram consisting of a series of microinstruction steps necessary for arithmetic processing in accordance with an arithmetic cycle. In order to advance the step in the microprogram, it is necessary to confirm the end of execution of the microinstruction of the previous step and the execution of the next step of microinstruction without ending the execution of the microinstruction of the previous step. There are operation cycles that can be entered. The former is a synchronous operation cycle, and the latter is an asynchronous operation cycle, which is determined by the characteristics of microinstructions. That synchronization operation cycle, for example when a user tries to execute a microinstruction X of the microprogram in the calculation cycle C _N, to proceed to the next cycle C _{N + 1} of C _N are microinstruction X is run correctly on C _N And then the next step microinstruction X
This is used when a shift to +1 needs to be made and erroneous processing occurs if this is not observed. On the other hand, in the asynchronous operation cycle, there is no processing relationship between the execution of the microinstruction in the previous step and the execution of the microinstruction in the next step in the operation cycle. It is adopted when it is not processed.

The arithmetic control unit sets an arithmetic cycle according to the microinstruction, controls the arithmetic unit according to the microinstruction and the arithmetic cycle, controls the transfer gate of the bus, sets the register,
Performs arithmetic processing operations such as memory read / write and data check. When all the arithmetic processing is completed, the micro program controller is notified and the arithmetic is completed.

The arithmetic control unit is provided with an arithmetic cycle counter for controlling the arithmetic cycle during execution of the microprogram, and each step of the microprogram is cycle-synchronized check so as to step in synchronization with the arithmetic cycle. Is being carried out. Therefore, the micro program control unit reads
For example, when a bit error is detected by the ECC check and execution becomes impossible, in order to secure the error correction time, the operation cycle is unconditionally stopped, that is,
The arithmetic operation was stopped and restarted, for example, one cycle after the error correction was completed.

FIG. 2A shows an example of a normal operation sequence of a microprogram of operation instructions. The illustrated microprogram is composed of 6 steps of A, B, C, D, E, and F, and C _{1 to} C ₈ cycles are used as the entire operation cycle. In this case, the microinstruction in each step of the microprogram is completed in one cycle when it is executed normally. By the way, in the operation instruction of the operation sequence illustrated in FIG. 2 (a), since the microprogram is composed of 6 steps A to F, the operation cycle has two extra cycles. However, the operation of the arithmetic unit requires 8 cycles. Therefore wait for end of the operation of the arithmetic unit of the three cycles of C ₈ in the last F step of the microprogram, and ends the operation to set the exit code when this is detected. Therefore, the arithmetic control unit notifies the microprogram control unit of the end of the arithmetic when the arithmetic cycle counter counts C ₈ .

By the way, as shown in FIG. 2 (b), the C step C ₃
In the cycle, when the micro program controller detects an error in the micro instruction read from the control memory, the operation cycle is stopped for one cycle and the next C ₄ cycle is delayed, as described above. Therefore, the C ₈ cycle occurs at the 9th cycle counting from the C ₁ cycle. And since the calculation end in C ₈ cycles is notified, as compared with the case of FIG. 2 (a), by one cycle operation end there has been a problem of delay.

[Object and Structure of Invention]

An object of the present invention is to reduce the delay of the operation cycle as much as possible when an error is detected in the microinstruction read from the control memory in the operation device under microprogram control.

Therefore, according to the present invention, during a series of operation cycles, it is necessary to confirm the operation cycle of the microprogram, that is, the operation end of the operation cycle of the previous step, and start the operation cycle of the next step. , There is a cycle that operates asynchronously, that is, the execution of the next step may be started without ending the operation of the previous operation cycle. Only when it happens in
The object is achieved by delaying the operation cycle, and when the operation cycle is asynchronous, the operation cycle is started without delay.

The configuration of the present invention is to execute a microprogram and an arithmetic unit in an arithmetic device by microprogram control including a control memory storing a microprogram, a microprogram controller, an arithmetic controller, and an arithmetic unit. For a series of operation cycles for, the operation cycle in which the operation unit operates in synchronization with the microprogram,
Means for identifying an operation cycle in which the arithmetic unit operates asynchronously regardless of the microprogram is provided by a decoder output of an instruction defining the microprogram, and the microprogram control unit executes each step of the microprogram when executing the microprogram. When a micro-instruction is sequentially read from the control memory and a bit error is detected in the information of the micro-instruction, it is identified by the above means that the operation cycle is an operation cycle synchronized with the above-mentioned micro program. Only when the operation cycle is temporarily stopped, the operation cycle is restarted after the bit error is corrected, and the operation cycle is identified by the above means as an operation cycle which operates asynchronously with the above microprogram. If the Without stopping the Le, in parallel with the execution of the computation unit, it is characterized in that so as to correct the bit errors.

Example of Invention

 Hereinafter, the present invention will be described according to examples.

FIG. 3 is a block diagram of the system of the embodiment of the present invention. In the figure, reference numerals 1 to 4 are common to those shown in FIG. Then, 5 is an instruction register, 6 is a decoder, 7 is an ECC circuit, 8 is a micro instruction decoder, 9 is an operation cycle counter, 10 is a synchronous / asynchronous cycle type register, 11 is a logic circuit, C _n is the number of operation cycles,
X / Y represents a synchronous / asynchronous cycle type.

The operation instruction of the instruction register 5 is decoded by the decoder 6, and the micro instruction address is given to the control memory 4 via the micro program control unit 1.

The control information such as microinstructions read from the control memory 4 is error-checked by the ECC circuit 7 and is automatically corrected if a 1-bit error is detected. Micro instructions are
It is applied to the micro instruction decoder 8. The output of the micro instruction decoder 8 is used to control the operation of the arithmetic unit 3 via the arithmetic control unit 2.

The number of operation cycles C _n is predetermined for each operation instruction and is updated by the control information of the decoder 6 and the microdecoder 8.

The synchronous / asynchronous cycle type information X / Y is predetermined for each operation instruction in association with each operation cycle, is set in the register 10 by the output of the operation cycle counter 9, and is applied to the logic circuit 11.

When the ECC circuit 7 detects an error in the data by the ECCC check, it sends an operation cycle stop signal to the logic circuit 11, and if the operation cycle is a synchronous cycle (X
/ Y = "1"), the clock supply to the operation cycle counter 9 and the operation control circuit is prohibited. In addition, ECC
When the circuit 7 finishes the error correction, the operation cycle stop signal is released and the subsequent clock is supplied.

In the logic circuit 11, the operation cycle is an asynchronous cycle (X /
If Y = “0”), the clock supply is not prohibited even if the operation cycle stop signal is applied, and the operation cycle is advanced in a predetermined order.

FIG. 4 is a sequence diagram according to the embodiment of the present invention in which the steps A and F of the microprogram are defined as a synchronous cycle and the other steps are asynchronous cycles. As in the case of FIG. 2 (b), when the one error is detected by the C ₃ cycle, for C ₃ -C ₇ cycles in this case is an asynchronous cycle (Y), operation cycle stops made Instead, the steps of the microprogram are directly executed from the C ₃ cycle to the C ₇ cycle, and in the cycle cycle (X) of C ₈ , the normal end of the operation up to C ₇ is confirmed and the operation is completed, so that the entire operation is completed. The processing can be completed in a cycle as specified, and the processing time can be shortened by one cycle as compared with the case of FIG. 2 (b). That is C ₃
Even if errors are detected in the execution of the C step of the microprogram in the cycle, C ₃ -C since ₇ cycles are asynchronous cycle, completion of execution of C step of the microprogram by the error correction detected by the C ₃ cycle Is delayed, the operation cycle is C without waiting for it.
₄ , C ₅ ... This is the same as the case of FIG. 2B in that the C step requires two operation cycles of C ₃ and C ₄ , but as described above, the execution of each microinstruction is normally performed. In this case, since one cycle is completed, the extra waiting time in the F step can be shortened by the cycle, so that the entire processing time is not delayed.

FIG. 5 is a block diagram of the arithmetic unit 3, in which A and B are operands OP1, C, and D of 4 bytes each and 4 bytes each.
Operands OP2, ADD are adders, Carry is carry X, Y is operand 4 of operation result of each 4 bytes
Represents 1.

FIG. 6 is an explanatory diagram of a specific example of the arithmetic operation of the arithmetic unit 3 shown in FIG. This specific example relates to an arithmetic instruction for adding operands OP1 and OP2 of 8 bytes and storing the result at the address of OP1.

OP1 (A + B) + OP2 (C, D) → OP1 (A, B) The right column in FIG. 6 shows the structure of the microprogram, and S
It is composed of 6 steps of _{1 to} S ₆ . In step S ₁ , control for activating the arithmetic unit is performed, and in step S ₂ ,
The data of the operand OP1 is fetched from the memory.
Step S ₃ performs data exception check in examining the health of the range of data values OP1 fetched, fetching step S ₄ the operand OP2. Step S
₅ performs OP2 data exception checking fetched in monitors operation completion of the operation unit in step S _6, the operation result when successful, sets the overflow, the exit code states such as data exception.

The left column of FIG. 6 shows the contents of the arithmetic cycle of the arithmetic unit activated by the microprogram in the right column. The operation cycle consists of ₈ cycles of C _{1 to} C ₈ , and OP ₁ at C ₁
Set the upper 4Byte to A, to set the lower 4Byte of _{C 2} in OP1 to B, the upper 4 of _{C 3} in the OP2
Set Byte to C, and in C ₄ , lower _{4 By} of OP2
Set te to D. In C ₅ , the lower 4 Bytes of OP1 and OP2 set in B and D are added, the sum and carry are set in Y and Carry, and in C ₆ , A
Upper 4 bytes of OP1 and OP2 set to C and C
And the contents of Carry are added, and the sum and carry are set to X and Carry. For C ₇ and C ₈ , X
The upper 4 bits of Y and Y transfer the lower 4 bytes of data as the upper lower data of OP 1.

In this operation cycle, C ₁ and C ₈ are synchronous cycles, and the other C _{2 to} C ₇ are asynchronous cycles. That is, C ₁
In step ₈ , synchronization is performed by activating the operation unit by the microprogram, and in C ₈ , the microprogram waits for the end of the operation of the operation unit and sets the end code. And in the middle of it, the microprogram is OP of S _{2 to} S ₅ regardless of the operation of the arithmetic unit.
1 performs OP2 fetch data exception Chetchi sequentially executes each cycle of _C 2 -C ₇ without confirmation of completion of each step of _S 2 to S ₅ in the arithmetic unit. Where S ₂
Even bit errors are detected by the reading of the microinstruction steps to S _8, operation cycles of the C ₂ -C ₇ can not be stopped, operation of the arithmetic unit is advanced.

[Effects of the Invention] As described above, according to the present invention, an arithmetic unit under program control does not unconditionally delay the arithmetic cycle when an error in control information is detected, but an asynchronous cycle. With respect to, the calculation time is shortened because the calculation operation is allowed to proceed as it is.

[Brief description of drawings]

FIG. 1 is a block diagram of an arithmetic unit under general microprogram control, FIGS. 2A and 2B are diagrams showing an example of a control sequence, FIG. 3 is a block diagram of an embodiment system, and FIG. FIG. 5 is a diagram showing an example of a control sequence in the embodiment system, FIG. 5 is a block diagram of an arithmetic unit of the embodiment system, and FIG. 6 is an explanatory diagram of a concrete example of the arithmetic operation. In the figure, 1 is a micro program control unit, 2 is an arithmetic control unit, 3 is an arithmetic unit, 4 is a control memory, 7 is an ECC circuit, 8
Is a microdecoder, 9 is an operation cycle counter, 10
Represents a synchronous / asynchronous cycle type register, and 11 represents a logic gate.

Claims (1)

[Claims] 1. A control memory in which a microprogram is stored, a microprogram control section, an arithmetic control section,
In an arithmetic unit controlled by a micro program including an arithmetic unit, regarding a series of arithmetic cycles for executing the micro program and the arithmetic unit, the arithmetic cycle in which the arithmetic unit operates in synchronization with the micro program is independent of the micro program. Is provided with means for identifying the operation cycle in which the arithmetic unit operates asynchronously by the decoder output of the instruction defining the microprogram, and the microprogram control unit controls the microinstruction at each step of the microprogram when executing the microprogram. When a bit error is detected in the information of the microinstruction when sequentially read from the memory, and only when the operation cycle is identified by the above means as the operation cycle synchronized with the above microprogram. ，
If the above-mentioned means identifies that the operation cycle is an operation cycle that operates asynchronously with the above microprogram, the operation cycle is restarted after the operation cycle is temporarily stopped and the bit error is corrected. An arithmetic control method characterized in that bit errors are corrected in parallel with the execution of the arithmetic unit without stopping the cycle.