JPH0797326B2 - Information processing equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that operates in parallel by a plurality of microprogram control circuits.

2. Description of the Related Art Conventionally, in a micro program control device having an error correction function, when an error is detected in a micro instruction word read from a control storage device, a micro program controller based on an error correction code included in the micro instruction word is used. Correct the error of the command word and execute the control.

Actually, when an error is detected, the microprogram control circuit is put in a HOLD state, and the microinstruction word in which an error is detected in this state is corrected based on the error correction code. After that, the hold state is released and the process is re-executed to recover the error.

In the microprogram control circuit, the number of microinstruction words can be reduced by controlling with a plurality of microprograms, or the control range can be reduced to simplify control.

In such a case, when an error is detected in one of the microprograms, the microprogram control circuit executing the microprogram may perform the error correction alone. However, the microprogram control circuit performs the error correction. Since the hold state occurs because of the execution, a time lag occurs between the micro program control circuit and another micro program control circuit.

In the case where there are cases where multiple microprogram control circuits must operate in synchronization,
In some cases, a synchronization circuit or the like is provided to prevent the time lag described above, but in many devices, a plurality of microprogram control circuits operate in perfect synchronization in order to prevent the circuit from becoming complicated. . In this case, when an error is detected in a certain microprogram, all microprogram control circuits must be put in a hold state to ensure complete synchronization among these plurality of microprogram control circuits.

In such a conventional information processing apparatus, when a plurality of micro program control circuits are operated in perfect synchronization, when an error is detected in the micro program control circuit in an idle state in which no micro instruction is executed. However, since the error correction is performed, there is a disadvantage that the micro instruction is being executed by this error correction and another normal micro program control circuit is brought into a hold state, resulting in deterioration of performance.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones. Even if an error is detected in the idle microprogram control circuit, another normal microprogram control during execution of microinstructions is performed. An object of the present invention is to provide an information processing device that can directly execute a micro instruction without bringing a circuit into a hold state and can improve performance.

The information processing apparatus according to the present invention is an information processing apparatus that operates in parallel and in perfect synchronization by a plurality of microprogram control circuits each having a control memory in which microinstructions are stored. For each control circuit, a flag indicating that the microinstruction is being executed and the flag indicating that the microinstruction is being executed when an error is detected in the microinstruction read from the control memory Only in this case, an error correction means for holding each of the plurality of microprogram control circuits to correct the error is provided.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the control memory devices 1 and 2 store micro-instructions for controlling the arithmetic units A and B (not shown), and the operation code for activating these control memory devices 1 and 2 is stored in the instruction register 3. Is stored.

The opcode stored in the instruction register 3 is decoded by the microprogram activation device 4 and given as a start address for each instruction to each microprogram control device (not shown). At the same time, the start flag 7, depending on the decoding result of the microprogram starting device 4,
8 is set.

The address registers 5 and 6 store the addresses from the microprogram activation device 4 or the control storage devices 1 and 2, and supply these addresses to the control storage devices 1 and 2.

The error check circuits 9 and 10 detect the error of the micro instruction word read from the control storage devices 1 and 2 by the address supplied from the address registers 5 and 6, and when the error is detected, the start flags 7 and 8 are set. The error detection flags 11 and 12 are set only in the status.

The control data registers 13 and 14 store the microinstruction words read from the control storage devices 1 and 2 by the addresses supplied from the address registers 5 and 6, or the microinstruction words corrected by the error correction circuits 15 and 16. It

When the error detection flags 11 and 12 are in the set state, the error correction circuits 15 and 16 put the micro program controller in the hold state and correct the error of the micro instruction word from the control data registers 13 and 14. When this error correction is completed, the error correction circuits 15 and 16 reset the error detection flags 11 and 12 and re-execute the microprogram controller.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.

For example, when the operation code stored in the instruction register 3 is decoded by the microprogram activation device 4 and it is determined that the operation code is an instruction to be calculated using the arithmetic unit A,
The start address corresponding to the instruction is stored in the address register 5. At the same time, the activation flag 7 is set to activate the control storage device 1, and the control register 2 stores a specific start address in the address register 6.

Microinstruction words designated by the addresses stored in address registers 5 and 6, respectively, are read from control storage devices 1 and 2, and the read microinstruction words are stored in control data registers 13 and 14.

The error check circuits 9 and 10 detect errors in the microinstruction words stored in the control data registers 13 and 14, respectively.

At this time, when the error check circuit 9 detects an error in the micro instruction word stored in the control data register 13, the error check circuit 9 sets the error detection flag 11 because the start flag 7 is set. At the same time, a hold signal is output to each register (not shown) of the micro program controller to put the micro program controller in the hold state.

When the error detection flag 11 is set, the error correction circuit 15 performs error correction on the microinstruction word stored in the control data register 13, and outputs the error-corrected microinstruction word to the control data register 13 for storage. To do.
At this time, the error correction circuit 15 simultaneously detects the error detection flag.
Reset 11 and re-run the microprogram controller.

However, even if the error check circuit 10 detects an error in the microinstruction word stored in the control data register 14, since the start flag 8 is not set,
The error detection flag 12 is not set, and the error correction circuit 16
No error correction is performed by.

Therefore, at this time, if the error check circuit 9 does not detect an error in the microinstruction word stored in the control data register 13, the microprogram controller continues to execute.

As described above, when an error is detected in the error check circuits 9 and 10, the error detection flags 11 and 12 are set only when the start flags 7 and 8 indicating that the microprogram controller is started are set. The error correction circuit 15 is set according to the contents of the error detection flags 11 and 12.
By enabling error correction in 16, even if an error is detected in the idle microprogram controller, other normal microprogram controller during microinstruction execution will not be put in the hold state and will be left as it is. Micro-instructions can be executed and performance can be improved.

In the embodiment of the present invention, when an error is detected by the error check circuits 9 and 10, the error detection flags 11 and 12 are set according to the contents of the start flags 7 and 8. When detected, the error correction circuits 15 and 16 may perform error correction according to the contents of the activation flags 7 and 8, but the invention is not limited to this.

As described above, according to the present invention, when an error is detected in the microinstruction read from the control memory, the microprogram control circuit responds to the content of the flag indicating that the microinstruction is being executed. By performing the error correction, even if an error is detected in the micro program control circuit in the idle state, the micro program control circuit in the normal state does not hold the other normal micro program control circuit during execution of the micro instruction, and the micro program control circuit does not change the micro state. It is possible to execute the instruction and improve the performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1,2 ...... Control storage device 7,8 …… Start flag 9,10 …… Error check circuit 11,12 …… Error detection flag 15,16 …… Error correction circuit

Continuation of the front page (56) Reference JP 62-93734 (JP, A) JP 59-121540 (JP, A) JP 55-39972 (JP, A) JP 54-146548 (JP , A)

Claims (1)

[Claims] 1. An information processing apparatus which operates in parallel and in full synchronization by a plurality of micro program control circuits each having a control memory storing micro instructions, wherein each of the plurality of micro program control circuits includes: The flag indicating that the microinstruction is being executed, and the plurality of flags are provided only when the flag indicates that the microinstruction is being executed when an error is detected in the microinstruction read from the control memory. An information processing device, comprising: an error correction means for holding each microprogram control circuit to correct the error.