JPS6218057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that performs pipeline processing.

Pipeline processing divides the instruction execution process into three partial processes: reading and decoding the instruction, reading operands, and executing the instruction, and executes each partial process in an overlapping manner between instructions to process information. This is a processing method that aims to speed up the process.

Conventionally, this type of information processing device has, as shown in FIG. 1, an instruction fetch section 1 that reads and decodes instructions, and a buffer that has a copy of a portion of the contents of the main memory and can be accessed at high speed. Storage part 2
, an instruction execution unit 3 that executes the operation specified by the instruction, stores a group of registers used in the operation, supplies register operands used for instruction execution (to the instruction execution unit 3), and executes the operation by executing the instruction. It is provided with a register stack 4 (register group storage device) for storing results (according to the output of the instruction execution section 3). For the first instruction _I1 , instruction reading and decoding processing is performed in the first machine cycle _T1 . The instruction reading and decoding process will be referred to as A phase. In the second machine cycle T ₂ ,
Upon access from the instruction fetch unit 1, memory operands are read from the buffer storage unit 2 and register operands are read from the register stack 4 and supplied to the instruction execution unit 3. This operand read processing will be referred to as B phase. In the machine cycle T ₂ above, A for the second instruction I ₂
Phase processing is performed in parallel by the instruction fetch section 1. In the third machine cycle T ₃ ,
The instruction _I1 is executed by the instruction execution unit 3 (E phase), and the arithmetic result of the instruction execution is written to the register stack 4 (W phase). That is, the E phase and the W phase are processed within the same machine cycle _T3 . On the other hand, B phase processing is performed for instruction I ₂ and A phase processing is performed for instruction I ₃ in parallel. In this way, high-speed processing becomes possible by overlappingly performing each phase process for a plurality of instructions.

FIG. 2 is a time chart showing an example of processing phases in each machine cycle T ₁ to _{T 8} for instructions I ₁ to _{I 5} . In the figure, up to instruction _I3 , each phase process for each instruction is performed in an overlapping manner with a delay of one machine cycle. The fourth instruction _I4 is an instruction that uses the operation result of instruction _I3 as an operand, so
The operand read process must wait until the W phase is completed in machine cycle _T5 . That is, for instruction _I4 , a register confirmation wait occurs in the B phase of machine cycle _T5 . Then, in machine cycle _T5 , the operation result of the execution of instruction _I3 is written to register stack 4, and in machine cycle _T6 , B phase processing is performed for instruction _I4 .

In the conventional device described above, even if a failure occurs during arithmetic processing in the instruction execution unit 3 and the result of the calculation is incorrect, the erroneous calculation result is stored in the register stack 4 within the same machine cycle. . Therefore, in the case of an instruction that performs an operation based on the contents of the specified register and updates the contents of the register with the result, if the operation is incorrect, the incorrect result will be stored in the register. The contents of the register before the operation have already disappeared. For this reason, the instruction cannot be retried, and there is a drawback that in the event of a temporary failure (intermittent failure), it is impossible to continue processing by retrying a valid instruction.

In order to solve the above-mentioned drawbacks, there is an apparatus in which the W phase process is performed in the machine cycle following the E phase. In this case, writing can be stopped when a failure such as an error in calculation is discovered, and processing can be continued by retrying the instruction. FIG. 3 is a time chart showing the processing phases in each machine cycle for each instruction of such a device, and one instruction requires a minimum of four machine cycles. That is, A, B, E,
Each phase of W requires one machine cycle, with each instruction phase typically occurring one machine cycle later than the previous instruction phase. However, since instruction I ₄ is an instruction that uses the operation result obtained by executing instruction I ₃ as an operand,
In machine cycles T ₅ and T ₆ , still the instruction I ₃
Since the operation result of is not stored in the register,
Unable to read operand. i.e. command
In the B phase of _I4 , two machine cycles worth of waiting for register confirmation occurs in machine cycles _T5 and _T6 . Then, the operand is read in machine cycle _T7 , the instruction is executed in machine cycle _T8 (E phase), and the operation result is written to register stack ₄ in machine cycle T9 (W phase). The next instruction _I5 processes each phase in machine cycles _T7 to _T10 . Therefore, in such a device, it is possible to retry instructions in the event of a failure, but the performance is degraded (it takes two machine cycles more than the device shown in Figure 2). ). In particular, if register confirmation waiting occurs frequently in the B phase, the entire processing time will be significantly delayed.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
The time required to wait for register confirmation is minimized (by operating as shown in Fig. 2), and furthermore, it is possible to retry instructions as much as possible in the event of a failure, increasing the possibility of continuing processing in the event of an intermittent failure. The purpose of the present invention is to provide an information processing device with high speed performance and high reliability.

The information processing device of the present invention includes an instruction fetch unit that reads and decodes instructions, an instruction execution unit that executes instructions, and a register operand that stores registers necessary for instruction execution. and a register group storage device for storing the operation results of instruction execution, and performs pipeline processing by overlapping instruction reading and decoding, operand reading, and instruction execution for multiple instructions. In the information processing device, the register group storage device includes a first register stack that supplies register operands used in instruction execution and stores arithmetic results obtained by instruction execution;
It has a built-in second register stack that writes the same data as the above calculation result at a timing delayed from the register stack, and monitors the occurrence of a failure in the device and writes the data to the second register stack when a failure occurs. The present invention is characterized in that it includes a failure processing circuit that prohibits writing of the second register stack and writes the contents of the second register stack to a corresponding area of the first register stack, thereby making it possible to retry instructions when a failure occurs. shall be.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention. That is, the instruction fetch section 1 reads and decodes instructions, that is, executes the A phase. The buffer storage section 2 is accessed together with the operand address by the instruction fetch section 1 when the instruction is decoded, and the memory operand is read out at high speed in the B phase and supplied to the instruction execution section 3. The instruction execution section 3 receives the memory operand 200 output from the buffer storage section 2 and the register operand 500 sent from the register group storage device 5 and executes the instruction (E phase). That is,
The instruction execution unit 3 includes selection circuits 30 and 31 that input a memory operand 200 and a register operand 500 and selectively output them, a first operand register 32 that temporarily holds the output of the selection circuit 30, and a selection circuit. A second operand register 33 holding the output of 31 and a first operand 320 and a second operand 330 outputted from these are input, and an operation specified by the instruction is executed,
It has a built-in arithmetic circuit 34 that outputs arithmetic result data 340. The above is almost the same as the conventional example shown in FIG.
and a write data register 52 that delays write data to the first register stack 50 by one machine cycle and writes it to the second register stack 51, and has the same configuration as the first register stack 50. A second register stack 51 to which the output of the write data register 52 is written, and a read data 510 of the second register stack 51.
and a selection circuit 53 which inputs the calculation result data 340 outputted from the calculation circuit 34, selectively outputs it and supplies it to the first register stack 50 and the write data register 52. . The first register stack 50 is
In the B phase, the register operands necessary for executing the instruction are read and the register operands 50 are read out.
0 to the instruction execution unit 4, and the calculation result data 3 output from the calculation circuit 34 in the _W1 phase.
Write 40. Further, the second register stack 51 writes the same operation result data as above in the _W2 phase, which is one machine cycle later than the _W1 phase. The fault processing circuit 6 manages whether or not a fault has occurred in each part within the apparatus, and when detecting the occurrence of a fault, performs command retry processing. That is, when the occurrence of a failure is detected, an instruction retry instruction 603 is given to the instruction fetch unit 1. However, in particular, the first
If a failure occurs up to the second register stack 50, writing to the second register stack 51 is inhibited by a write inhibit signal 600, the contents of the register are read as read data 510, and the selection circuit 53 The read data 510 is selectively output by the selection signal 601. Then, the output data of the selection circuit 53 is written into the area corresponding to the register in the first register stack 50 by a write instruction signal 602. That is, the register in the first register stack 50 is restored to the state before execution of the failed instruction. After this recovery process is completed, an instruction retry instruction 603 is output to the instruction fetch unit 1. This series of operations makes it possible to retry the command in the majority of failures, and in the case of intermittent failures, which are said to occur at a frequency of more than half of all failures, it is possible to bring down the device. Processing can be continued without any problems.

FIG. 5 is a time chart showing the relationship between the phases of instruction processing and machine cycles according to this embodiment. In the figure, phase W ₁ indicates a phase in which the calculation result is stored in the first register stack 50, and phase W ₂ indicates a phase in which the same calculation result as above is written into the second register stack 51. That is, in the processing of instruction I ₁ , A phase processing is performed in machine cycle T ₁ , B phase processing is performed in machine cycle T ₂ , and instruction execution ( _E
phase) and writing processing of the operation result to the first register stack 50 ( _W1 phase) is performed. In machine cycle _T4 , the same data as above is written to the second register stack 51 ( _W2 phase). Therefore, the instruction _I2 is processed in the A, B, E/ _W1 , and _W2 phases in machine cycles _T2 to _T5 , respectively. Similar processing is performed for instruction _I3 with a delay of one machine cycle. Instruction I ₄ is an instruction that uses the operation result of instruction I ₃ , so the machine cycle
At T ₅ , the B phase waits for register confirmation, but since the operation result of instruction I ₃ completes the processing of W ₁ phase within machine cycle T ₅ , the operand of instruction I ₄ is read in machine cycle T ₆ . be able to. That is, instructions can be processed at the same pace as the conventional example shown in FIG. Thereafter, in machine cycle _T7 , the instruction is executed (E phase) and the operation result is written to the first register stack ( _W1 phase), and in machine cycle _T8 , the same data is written to the second register stack 51. is written to. Similarly, for instruction _I5 , each phase process is performed in machine cycles _T6 to _T9 . essentially a machine cycle
Processing up to instruction _I5 is completed at _T8 . That is, it is possible to perform pipeline processing at the same high speed as in the conventional example shown in FIG. However, in this embodiment, since the same operation result data is written to the second register stack in the _W2 phase, the second register stack 51 is written under the control of the failure processing circuit 6 when a failure occurs. This prevents erroneous data from being written to the register, and allows the instruction to be retried based on the correct register contents before the instruction is executed. Moreover, unlike the conventional example shown in FIG. 3, it does not require much processing time. That is,
The time required to wait for register confirmation is minimized, and instruction retries are maximized in the event of a failure, making it possible to continue processing even in the event of an intermittent failure, achieving high-speed performance and highly reliable information processing. There is an effect that can be achieved.

In the above embodiment, the second register stack 51
Although the writing of operation result data to the first register stack 50 is delayed by one machine cycle, the writing can be delayed by n machine cycles by providing n stages of write data registers 52. In this case, when a failure occurs, after all the contents of the second register stack 51 are transferred to the first register stack 50, it is possible to go back by a plurality of instructions and retry the instruction. Therefore, it is effective even for a failure in which the cause of the failure occurred several instructions ago, for example, and it is possible to further improve reliability. The above-mentioned n-stage write data register can be easily realized by, for example, adopting an n-word memory that can be read and written simultaneously, and storing the operation result of each instruction cyclically in the word direction together with its register number.

Furthermore, in a computer system to which the present invention is applied, program processing is performed in units of processes, one set of registers is defined for each process, and the contents of the registers corresponding to processes that are not running are A system that saves the contents of a corresponding register group to a save area provided in a main storage device, and transfers the contents of a corresponding register group from the save area to a register group storage device when switching processes, and executes the process after recovery. In order to save and restore the contents of the register group at high speed, the first register is used to store the register group corresponding to the running process.
In addition to the first register stack, the second register storage device has a second register stack that stores a plurality of sets of registers corresponding to the currently executing process, the previously executed process, the next process to be executed, etc. (Refer to Japanese Patent Application No. 56-190516), this information processing device is equipped with the first
In addition to this register stack, it already has a second register stack with several times the capacity.
It is possible to add a write data register for delaying writing to the second register stack, and to perform a retry in the event of a failure under the control of the failure handling circuit. In other words, the present invention can be applied to improve retry performance without substantially increasing the amount of metal objects.

As described above, in the present invention, the first register stack is used to write operation result data resulting from instruction execution in the same machine cycle as the instruction execution machine cycle, and the second register stack is written to with a delay. Because of this configuration, even for instructions that use the operation result data of the previous instruction as an operand, it is possible to minimize the period of waiting for register confirmation in the operand read phase, and moreover, it is possible to minimize the period of waiting for register confirmation in the operand read phase. There is a high possibility of retrying. That is, since it has the possibility of retrying instructions without extending processing time, it has the great effect of enabling high-speed performance and highly reliable information processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an information processing device that performs conventional pipeline processing, and FIG. 2 is a time chart for explaining the operation of the conventional example.
FIG. 3 is a time chart showing the operation of another conventional example, FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation of the above embodiment. In the figure, 1...instruction fetch section, 2...buffer storage section, 3...instruction execution section, 4...register stack, 5...register group storage device, 6...
Failure processing circuit, 30, 31...Selection circuit, 32...
...First operand register, 33... Second operand register, 34... Arithmetic circuit, 50...
First register stack, 51...Second register stack, 52...Write data register, 5
3... Selection circuit, A... Instruction reading and decoding phase, B... Operand reading phase, E...
Instruction execution phase, W, W ₁ , W ₂ ... operation result storage phase.

Claims (1)

[Claims] 1. Instruction fetch unit 1 that reads and decodes instructions.
, an instruction execution unit 3 that executes instructions, and a register group storage device that stores register groups necessary for instruction execution, supplies register operands used for instruction execution to the instruction execution unit, and stores arithmetic results by instruction execution. 5, the information processing device performs pipeline processing by overlapping instruction reading/decoding, operand reading, and instruction execution for multiple instructions, wherein the register group storage device is used for instruction execution. a first register stack 50 for supplying register operands to be executed and storing arithmetic results from instruction execution;
and a second register stack 51 that writes the same data as the arithmetic result at a timing later than that of the first register stack, and monitors the occurrence of a failure within the device, and when a failure occurs, the second register stack 51 An information processing device comprising: a failure processing circuit that prohibits writing to a second register stack and causes the contents of the second register stack to be written to a corresponding area of the first register stack. .