JPH0368034A - Checkpoint retesting system - Google Patents

Abstract

PURPOSE:To retest a check point easily at a multiple processor system by providing a hardware which guarantees the stored result of another system processor against the self-system processor. CONSTITUTION:An instruction is fetched to an instruction register 5 and decoded. As a result of the decode, a virtual operand address and the instruction length are calculated. The virtual operand address is converted to a physical address by an address conversion buffer 6, and the instruction length is stored at an instruction length latch (IL) 114. An operand data is read out from a cache 7 by the converted physical address, and at the same time, the contents of the IL 114 are transferred to an IL 215. The operand data is sent to an execution part 8 for the execution of the instruction, and is also sent to a cache buffer 11 when storing is executed to the address of the cache 7. At the same time, the contents of the IL 215 are transferred to an IL 316, and is held during the instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a checkpoint retry scheme in a multiprocessor system.

[Prior Art] FIG. 4 shows an example of the configuration of a multiprocessor system. In the figure, processors PO and Pl (1) and (2) are composed of the same hardware structure and communicate with each other via a system bus 4. (3) is a main storage device (abbreviated as MS), which is a main storage device (abbreviated as MS), which includes a processor P O (1) and a processor P
112+ processing results are stored.

FIG. 5 shows the main components of the processor P O (11). In the figure, (5) is an instruction register (abbreviated as IR) for storing instructions fetched from M
6) is an address translation buffer (combined with TLB) that converts the address of the operand determined from the result of decoding the output of IR (51), and (7) is TLB. Cache for retrieving copies of contents (abbreviated as CAC), +81 is CA C+
an execution unit (abbreviated as EX, U) that processes the output of 71;
(9) is local storage (abbreviated as LS) that constitutes a work register such as a general-purpose register, and (10) is LS.
(Local storage sofa (abbreviated as LSB) that saves the value before change of 91, (11) is CA C (7
Cache buffer (CA
(abbreviated as CB), (],, 2) is an instruction counter (abbreviated as IC) that holds the address for sequentially fetching instructions from M S (3+), (13) is the value of IC (12) every time a checkpoint is established. Instruction counter buffer (abbreviated as ICB) to save, (19) is E X U +8
When executing a store from 1, a lock array (abbreviated as LK) is used to lock the contents of the store operand until the next checkpoint is established.
Checkpoint establishment request signal line (CKP
(abbreviated as T line).

Next, the operation will be explained. The instruction is fetched from the address of M S +31, indicated by IC(12), into IR[5] and decoded. The virtual operand address obtained as a result of decoding is converted into a physical address by T L B f6+. According to the converted physical address, operand data is read from CA C(71) and sent to EXU(81) for instruction execution. , it is also sent to CACB (11,). On the other hand, the operand stored in the general-purpose register is read from L S (91) and is sent to E X U (
81 and when loading is performed to the address of L S +91, L S B (1,0
) is also sent to. The execution result at E X U +81 is
CAc +71 and L S (written to 91. C
When writing to A C (71), a lock is placed on the entry of L K (19) corresponding to the store address in order to prevent the write data from being changed by other processors until the next checkpoint is established. set.

This locking method is shown in Japanese Patent Publication No. 61-2975.

When a failure occurs, this processor restores the hardware state to the most recently established checkpoint and tries again. Has a checkpoint retry function. If a failure occurs, L S B (10) to L S f9+
Restore the changes in CACB (11) to CA, C
(Restore the changes in 71 and change I CB (13) to I
By returning C(12) to the instruction address at the time the checkpoint was established, a retry is made from the previous checkpoint.

Next, the function of L K (19) will be explained using FIG. 6. When a checkpoint is retried, the store instruction that was executed before the failure occurs is re-executed. For this reason,
When a foreign processor PL executes a store on the store result of the own processor PO, the store result of the foreign processor P1 may be lost as a result of the checkpoint retry. LK (19) is provided to avoid this problem, and as shown in FIG. 6, is set when a store is executed and reset when a checkpoint is established. The store of the other system processor PL is made to wait while the target entry of LK (19) is set, and is controlled to be executed after the checkpoint of the own system processor PO is established. As a result, even if the own processor PO fails after executing the store and before establishing the secondary checkpoint, and the same store is executed again by retrying from the previous checkpoint, the store result of the other processor P1 will not be the same. Guaranteed. The period from the time when the first checkpoint is established to the time when the next checkpoint is established is called a checkpoint frame.

Next, the operation when establishing a checkpoint will be explained using FIG. 5. When establishing a checkpoint, first wait for the processing of the preceding store to complete (referred to as synchronization). Thereafter, a checkpoint establishment request is sent from EXU (8) via the CKPT line (20). This results in
The contents of LSB (10) and CACB (11) are invalidated, all contents of L K (19) are reset, and I
The contents of C(12) are saved to ICB(13).

[Problem to be Solved by the Invention] In the conventional checkpoint retry method, the storage of the checkpoint result in the checkpoint frame of the own processor in the other processor waits until the next checkpoint is established in the own processor. There was a problem in that the detection circuits and exclusion circuits required for this purpose were enormous and complex. In addition, system performance was adversely affected because requests from other processors were forced to wait.

The present invention was made to solve the above-mentioned problems, and aims to provide a multiprocessor system that can easily perform retrials by adding a small number of circuits.

[Means for Solving the Problems] The checkpoint retry method according to the present invention is an asynchronous method that includes a counter that counts the number of pending store requests and establishes a checkpoint without waiting for the completion of pending stores. In addition to issuing an asynchronous checkpoint establishment request, the instruction length retaining means retains the instruction length of the instruction that issued the checkpoint establishment request, and a failure occurs after the store by the store instruction that established the asynchronous checkpoint is completed. If this occurs, a retry is made from the instruction following the store instruction.

[Operation] The checkpoint retry method in this invention establishes an asynchronous checkpoint every time a store instruction is executed,
Increment the pending store request counter by 1, save the instruction length of the store instruction in the instruction length holding unit (buffer or register), and retry from the checkpoint by decrementing the pending store request counter by 1 when the store is completed. At this time, if the pending store request counter is LI_Olj, a retry is made from the instruction following the store instruction, and if it is not u_O+y, a retry is made from the store instruction.

That is, if the store has been completed, the next store instruction is retried to ensure that the store result of the other system processor is the same as the store result of the own system processor. Furthermore, if the store is not completed, the program is retried from the store instruction to ensure the program execution sequence.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main components of the processor P Of1+ shown in FIG. 4 according to this embodiment. In the figure, (5) is an instruction register (abbreviated as IR') that stores the instruction fetched from M S [31, (61
is an address translation buffer (T
(abbreviated as LB), (7) is a cache (abbreviated as CAC) for extracting a copy of the contents of M S +31 from the conversion result of T LB (61), and +81 is CAC (abbreviated as CAC).
Execution unit (abbreviated as EXU) that processes the output of 71, +9
1 is local storage (abbreviated as LS) that constitutes a work register such as a general-purpose register, (10) is LS +
A local storage buffer (abbreviated as LSB) that saves the value before change of 91, (11) is a cache buffer (abbreviated as CACB) that saves the value before change of 71, (12) is from M S +31 An instruction counter (abbreviated as IC) that holds addresses for fetching instructions sequentially, (13) is
(14) is an instruction counter buffer (abbreviated as CB) that saves the value of C (12), and an instruction length latch 1 (abbreviated as ILL) that stores the instruction length of the decoded instruction during address conversion by TLB (81). , (15) is C A C
(Instruction length latch 2 that holds the instruction length during access to 71)
(abbreviated as IL2), (16) is an instruction length latch 3 (abbreviated as IL3), (17) that holds the instruction length during instruction execution.
) is IL3 (1B) when an asynchronous checkpoint is established.
instruction length buffer (abbreviated as ILCB) that stores the contents of
, (18) is a pending store request counter (abbreviated as spc) that counts up at the store request of EXU (8) and counts down when the store is completed in CA Cfi+, (20) is the pending store request counter (abbreviated as spc)
Synchronous checkpoint establishment request signal line from 81, (21) is EXU (asynchronous checkpoint establishment request signal line from 81, (22) is the logical sum of the above signal lines (20) and (21) The output of the OR gate (23) is a checkpoint establishment request signal line that becomes valid when either the synchronous checkpoint establishment request or the asynchronous checkpoint establishment request is valid.

Next, the operation will be explained. The instruction is fetched from the address of M S (31) indicated by I C (12) to IR (5) and decoded. As a result of decoding, the virtual operand address and instruction length are found, and the virtual operand address is T L B (61) converts it into a physical address, and the instruction length is stored in I L 1 (14).

According to the converted physical address, operand data is read from CA C (71) and at the same time, ILL (14
) is moved to I L 2 (15). C.A.C.
The operand data read from +7) is sent to E X tJ +8) for instruction execution, and is also sent to CACB (11) when a store is performed to the address of CA C+7) by instruction execution. At the same time, the content of I L, 2 (15) becomes I L 3
(16) and is held during instruction execution. On the other hand, the operand stored in the general-purpose register is L S +9
1 and sent to E
The execution result on U +81 is CA C+71 and L
Written to S+91.

This processor also has a checkpoint retry function,
If a failure occurs, L S B (10) to L
Restore the changes of S +91, restore the changes of CA C (71) from CACB (11), and restore the changes of I CB (1
, 3), the I C (12) is returned to the instruction address at the time the checkpoint was established, thereby retrying from the previous checkpoint.

Here, a case of failure after execution of a store instruction will be described. EXU (8) is an asynchronous checkpoint establishment request signal line (21) every time a store instruction is executed.
First, a checkpoint is established, and the instruction address of the store instruction is set to I CE (13), and the instruction length is set to I CE (13).
It is stored in the LCB (17), and the contents of the LSB (10) and CA CB (11,) are invalidated so that a retry can be made from the store instruction in the event of a subsequent failure. Next, perform a store on the operand and S P C
Count up (18). When the store is completed normally, S
PC (18) counts down. FIG. 2 shows an example of processing when a failure occurs after the store is completed. E
The store request from X U (8) is temporarily put on hold due to conflict with another request, and when the conflict is resolved, it is actually written to CA C+71, and accordingly,
C(18) counts down and returns to "OF+. Therefore, SPC(18) counts down from the time the store request is issued.
It 1 hp is held until the writing to A C (71) is completed. Figure 2 shows a case where a failure occurs after sp c (18) counts down and reaches 11 Q jl. In this case, EXU+81 knows that the store is completed because the contents of SPC (18) are "0" during machine check interrupt processing, and therefore should not execute the store instruction at the previous checkpoint. , we also know that there is no need to execute it.Therefore, E
X U f8+ sets the instruction length of the store instruction to ILCB (
By storing the result obtained from step 17) and added to the value of I CB (13) in I C (12), it is possible to retry the instruction following the store instruction. Also, since the above processing is performed, when executing the store instruction, CA
The value of 0 or more that does not save data before storage in C(7) to CACB(11) prevents EXU(8) from erroneously writing back the store result and losing the store result of other system processors. In the case of Figure 2, the store of the Shiraito processor has been completed by the time the failure occurs, and the store result is visible to the processors of other systems, so when the own processor re-executes the store by retrying, the processors of both systems There is a risk that program consistency will not be maintained.

FIG. 3 shows a case where a failure occurs while a store is pending. In this case, E Therefore, E do it like this. Normally, if the pending store cannot be separated from the failure location, the status is frozen as soon as the failure occurs, and
The recovery process clears the pending store and returns CAC(7)
to wait for requests so that retries are not negatively affected.

On the other hand, if it can be separated from the failure, the storage will be completed during the recovery process of the failed part and the SPC (18) will not be frozen due to the failure. rto”.

On the other hand, when establishing a synchronous checkpoint, the checkpoint is established after all pending stores are completed. Therefore, at this point, S P C (18) is
”, and the content of I L 'CB (17) is also “O”.
shall be. As a result, if a failure occurs after the synchronous checkpoint is established but before the asynchronous checkpoint is established, E
0” to I CB (1, 3) and then IC (12
), so you can retry from the checkpoint establishment point.

[Effects of the Invention] As described above, according to the present invention, the hardware for guaranteeing the store result of the other system processor with respect to the store result of the own system processor is configured with a pending store request counter and an instruction length buffer, Now that an asynchronous checkpoint establishment request is issued,
The device can be made inexpensive and has the effect of reducing adverse effects on system performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part configuration of a processor according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram showing a processing method in the case where a failure occurs after a store is completed in this embodiment.
FIG. 3 is a conceptual diagram showing a processing method in the case where a failure occurs while a store is pending in this embodiment, FIG. 4 is a block diagram showing a multiprocessor system, and FIG. 5 shows the main part configuration of a conventional processor. The block diagram in FIG. 6 is a conceptual diagram showing a lock method and a retry method in a conventional processor. (11, +21 are processors (PO, Pl), (31 is main memory (MS), (71 is cache (CAC),
+8) is the execution unit (EXU), +9+ is the local storage (LS), (10) is the local storage buffer (LSB), (11) is the cache buffer (CACB), and (12) is the instruction counter (IC). ,
(13) is the instruction counter buffer (I CB), (1
7) is an instruction length buffer (ILCB; instruction length holding means), (18) is a pending store request counter (spc), (20) is a synchronous checkpoint establishment request signal line, (21) is an asynchronous checkpoint Establishment request signal line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] The present invention includes means for retaining intermediate results of instruction execution, and by establishing a checkpoint for each predetermined instruction, a function is provided for returning from the instruction address where a failure has occurred to the previous checkpoint and retrying. In a multiprocessor system consisting of multiple processors, the system is equipped with a counter that counts the number of pending store requests, and issues an asynchronous checkpoint establishment request to establish a checkpoint without waiting for the completion of pending stores. , an instruction length holding unit that holds the instruction length of the instruction that issued the checkpoint establishment request, and if a failure occurs after the store by the store instruction that established the asynchronous checkpoint is completed, the instruction length of the instruction that issued the checkpoint establishment request is A checkpoint retry method characterized by retrying from the next instruction.