JPH01258154A - Control system for micro instruction execution - Google Patents

Abstract

PURPOSE:To considerably reduce the execution waiting cycle of a CPU by storing several page numbers out of page numbers of pages, for which write requests newly occur, out of pages existing in a main storage in the CPU to judge whether a required page exists in the main storage or not. CONSTITUTION:A holding means 11 holds page numbers of written pages in a virtual space, and a comparing means 17 compares all effective page numbers 18, which are held in the holding means 11 and are indicated by a display means, with the page number indicated by a virtual address and informs a control means 20 of the comparison result. The control means 20 operates a micro instruction execution wait generating function only when coincidence is not detected by the comparing means 17. Thus, the occurrence of the waiting cycle of the CPU is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a microinstruction execution method for a computing system having a virtual storage mechanism.

(Prior Art) Conventionally, in this type of computer system, a virtual storage mechanism uses a relatively small-capacity main storage device and a large-capacity external storage device to store programs as if a large-capacity main storage device existed. This is an important mechanism for making each process work. A virtual storage mechanism requires an address translation mechanism that establishes a correspondence between a virtual address used by a program and a physical address indicating an actual location in main memory. This address translation mechanism generally includes a memory control unit (H
CU) 3. Both the virtual space pointed to by a virtual address and the physical space of the main storage device are divided into blocks of a fixed size called pages, and address exchange from virtual addresses to physical addresses is performed in units of pages. is common. In the process of address translation, if a page containing the necessary virtual address does not exist in the main memory, a page fault signal is sent to the CPU 1. The CPU 1 is the main storage device 2
Unlike when requesting continuous output, there is no need to wait for data to be returned from the main memory device 2 when a request is made for a write-in, so it is possible to proceed with execution of the next microinstruction. However, in this method, when a page fault occurs in response to a write request, the state of CPU1 has changed from the state when the write request occurred, so external memory 1! It becomes difficult to re-execute the 11th instruction of the page-in operation for reading the necessary page from the device 6 into the main storage device 2 via the input/output processing bag @7.

For this reason, conventionally, when a write request is made, the response from the memory control unit 3 indicates that the write has been completed normally or that a page fault has occurred.
A micro-instruction execution wait generation circuit 5 is provided inside the CPU to cause the CPU to wait so as not to move on to executing the next micro-instruction.

However, in such a system, a waiting cycle is always generated in the CPU 1 every time a write request is generated, and the processing is stopped, so there is a problem that the processing performance of the CPU 1 is degraded.

On the other hand, when a write request occurs, the state of the CPUI is saved and the next microinstruction is executed, and if a page fault occurs, the saved state of the CPUI is restored and the instruction is restarted. A method of carrying out the execution is also known.

This method does not cause CPU1 to wait, but CPU1
There are problems in that the processing for saving and restoring the state of the system is complicated and the amount of hardware increases.

(Problems to be Solved by the Invention) As described above, in a computer system having a conventional virtual memory mechanism, when a write request is made to the main memory, a response from the memory control unit 3 indicates whether the write has been completed normally or whether the page until it becomes clear that a fault has occurred.
A micro-instruction execution wait generation circuit 5 is provided inside the CPU 1 in order to cause the CPU to wait so that it does not move on to executing the next micro-instruction. For this reason, each time a write request occurs, a wait cycle occurs in the CPUI and the processing is stopped, resulting in an inconvenience that the processing capacity of the CPUI is reduced.

Therefore, the above microinstruction execution wait generation circuit is not provided, and
When a write request occurs, the CPU state is saved and the next microinstruction is executed, and if a page fault occurs, the saved CPU state is restored and the instruction is re-executed. There is also a system, but the CPU
The process of saving and restoring the state of the system is complicated, and the amount of hardware required increases.

The present invention eliminates the above-mentioned drawbacks, and aims to prevent a decrease in CPU performance by reducing the number of CPU wait cycles caused by a microinstruction execution wait generation circuit when a write request is made to main memory using a simple hardware configuration. The purpose of this project is to provide a microinstruction execution control system that can perform the following tasks.

[Structure of the Invention] (Means for Solving the Problems) The present invention has a virtual storage mechanism using a paging method,
In addition, a computer system having a microinstruction execution wait generation function that prevents the CPU from proceeding to execution of the next microinstruction until it becomes clear whether writing to main memory has completed normally or a page fault has occurred. a holding means for holding a page number of a page in the virtual space to which writing has been performed; a display means for indicating whether or not the page number held in the holding means is valid; Comparison means for comparing all valid page numbers indicated by the display means with the page number indicated by the virtual address, and a function for generating a microinstruction execution wait only when the comparison means does not detect a match. The system is equipped with a control means for operating the system.

(Operation) In the microinstruction execution control system of the present invention, the holding means holds the page number of the page in the virtual space that has been written 8 times. The comparison means compares all valid page numbers held by the holding means and indicated by the display means to see if they match the page number indicated by the virtual address, and notifies the control means of the result. The control means operates the microinstruction execution wait generating function only when the matching is not detected by the comparison means. This makes it possible to reduce the occurrence of CPU wait cycles.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CPU to which the microinstruction execution control system of the present invention is applied. Virtual addresses used by programs are generally held within 11 virtual address registers, with a page number @12 pointing to the page in the virtual space that includes the virtual address, and an intra-page relative address 13 indicating the position within the page. Consists of. , 14 are a group of page number registers for holding page numbers of pages in the virtual space that have been written in the past. Each page number register 15 of the page number register group 14 has a valid bit 16 indicating whether the page number held by that page number register is valid. 17 is page number register group 14
This is a comparator that compares all page numbers 18 held by the CPU with the page number 12 of the virtual address to which the CPU has issued a write request. The comparison output signal 19 of the comparator 17 is
The logic value "1" is taken only when the input page number is valid and the comparison results match.

The comparison output signal 19 is input to a microinstruction execution wait generation circuit 20.

In the microinstruction execution wait generation circuit 20, the comparator 17 detects a valid page number that matches the page number 12 indicated in the virtual address register 11 from among the page numbers 18 held in the page number register group 14. This is to prevent the CPU from starting execution of the next microinstruction if the microinstruction cannot be executed. Note that the circuit shown in FIG. 1 is provided inside a CPU that constitutes a computer system.

Next, the operation of this embodiment will be explained.

First, the valid bits 1B of all the page number registers 15 of the page number register group 14 are set to a value indicating that the contents of the page number registers 15 are invalid, that is, the logical value "O". When a write request to the main memory occurs in the CPU, the page number 12 of the virtual address where the write request occurred is compared by the comparator 17 with all the page numbers 18 held in the page number register group 14. If there is no match as a result of the comparison, this indicates that a page fault may occur, and in this case, the comparison output signal of the comparator 17 @19
takes the logical value "On."As a result, the microinstruction execution wait generation circuit 20 prevents the CPU from starting execution of the next microinstruction, and the memory control unit (not shown) that controls the main memory instructs the CPU to determine whether the writing has been completed normally. , or causes the CPU to wait until a response is returned indicating whether a page fault has occurred.If no match is found, the page @@12 at the virtual address is
Among the page number registers 15 of the page number register group 14, one of the page number registers 15 whose valid bit 16 is "0" is selected and held therein. At this time, the valid bit corresponding to the page number register 15 is set to 1''. If there is no page number register 15 whose valid bit 16 is ``Oee'', then
After the valid bits of all page number registers 15 are set to "0", one of the page number registers 15 is selected and a page number is written, and the valid bit of that page number register is set to "1". When performing rollout processing to drive a page from main memory to external memory, it is checked whether the page number corresponding to that page is held in the page number register 15 of the page number register group 14, and if If held, valid bit 16 of the page lt@ register holding the page number.
Set to “0”. As a result, page number register group 1
4, the page number held by the page number register 15 whose valid bit 16 is 41 is guaranteed to be the page number of a page existing in the main memory. The same page number as page number 12 of the virtual address where the write request occurred is the page number held by the page number register whose valid bit 16 of the page number register 15 of the page number register group 14 is "1'". 18, it means that the page corresponding to the page number exists in main memory. At this time, the comparison output signal 19 of the comparator 17 takes the logical value "1", and as a result, the microinstruction execution wait generating circuit 20 does not generate a hold during the execution cycle of CPtJ, and immediately executes the next microinstruction. is started. In addition,
A comparator 17 is included in the microinstruction execution generation circuit 20.
A control circuit is provided which activates this circuit when the comparison output signal 19 from the 19 is a logic value of "0" and stops the operation of this circuit when it has a logic value of "'1".

According to this embodiment, when the same page number as the page number 12 of the virtual address is not among all the page numbers held in the page number register group 14, that is, when there is a possibility that a page fault will occur. In this case, the microinstruction execution wait generation circuit 20 is activated to cause the CPU to wait for processing until there is a response from the memory control unit indicating the completion of normal writing or the occurrence of a page fault. In order to immediately execute the next microinstruction without causing a wait during the execution cycle, a microinstruction execution wait generation circuit 20 is used.
It is possible to significantly reduce the number of CPU waiting cycles caused by the CPU, thereby preventing a decrease in CPU performance. Further, the configuration for bringing about the above effects can be realized with a simple configuration by adding some hardware such as the comparator 17, and an increase in the cost of the CPU can be prevented.

FIG. 2 shows another embodiment of the invention. In FIG. 2, if the components are the same as those in FIG. 1, they are numbered the same as in FIG. 1. This embodiment differs from the previous embodiment in that there are the same number of comparators 17 for comparing page numbers as there are page number registers 15, and an OR gate 32 is provided to take the logical sum of the outputs of these comparators 17. The second point is that a priority register 33 is provided for each page number register 15 of the page number register group 14. A comparator 17 that compares page numbers outputs a comparison output when the page number held in the corresponding page number register 15 is valid and matches the page number of the virtual address where writing occurred. The signal 34 takes the logic value "1" and takes the logic value "O" in other cases. OR gate 32
By calculating the logical OR of the outputs of all the comparators 17, it is detected that any of the page number registers 15 holds a valid page number that is the same as the page number of the virtual address where writing occurred. Yes, only in that case, the output 35 of the OR gate takes a logic value of "1".The output of this OR gate is
It is input to 0. When all the page number registers 15 hold valid page numbers, the priority register 33 determines whether a request is made for a new page number that has a different page number from those page numbers. It also holds a value indicating the priority for determining which page number register's contents should be replaced with a new page number.

Next, the operation of this embodiment will be explained.

First, the valid bits 16 of all the page number registers 15 of the page number register group 14 are set to a value indicating that the contents of the page number registers 15 are invalid, that is, a logical value of "0". At this time, priority register 3
The value of 3 may be any value. When a write request to the main memory occurs in the cPu, the page number 12 of the virtual address where the write request occurred is compared by each comparator 17 with all page numbers 18 held in the page number register group 14.

If there is no match as a result of the comparison, it indicates that a page fault may occur. At this time, the comparison output signals 34 of all the comparators 17 have the logical value "O".
at, and therefore the output of the OR gate is the logical value ``0''.
Take ゛′. As a result, the micro-instruction execution wait generating circuit 20 prevents the CPIJ from starting execution of the next micro-instruction, and determines whether the writing has been completed normally from the memory control unit that controls the main memory (not shown), or whether a page fault has occurred. until a response indicating
Generates a wait in CPU processing. If no match is detected, the page number 12 of the virtual address is determined by selecting one of the page number registers whose valid bit 16 is "0" among the page number registers 15 of the page number register group 14. held inside.

At this time, the valid bit corresponding to the page number register 15 is set to "1'°," and the value of the priority register 33 is set to a value indicating the lowest priority.

The values of the priority registers corresponding to the other page number registers 15 are reset to values with higher priority by 1 than before. If there is no page number register 15 for which the valid bit 16 is "0", the page number register 15 whose corresponding priority register 33 has a value indicating the highest priority is selected. Select and keep the new page number 12 there. When performing a rollout process for expelling a page from the main memory to an external memory, it is checked whether the page number corresponding to the page is held in the page number register 15 of the page number register group 14. If the page number is held, the valid bit 1B of the page number register 15 holding the page number is set to "0". As a result, page number register 1 of page number register group 14
5, the page number held by the page number register 15 whose valid bit 16 is "1" is guaranteed to be the page number of a page existing in the main memory. The same page number as page number 12 of the virtual address where the write request occurred is the page number held by the page number register whose valid bit 1B of the page number register 15 of the page number register group 14 is "1''. 18, it means that the page corresponding to the page number exists in the main memory.In this case, page number 1
The comparison output 34 of the comparator 17 corresponding to the page number register 15 holding the same page number as 2 is the logical value "1".
'', and the output of the OR gate 32 takes a logic value of ``1''. As a result, the microinstruction execution wait generation circuit 20
To immediately start execution of the next microinstruction without causing a wait during the execution cycle of U.

In this embodiment as well, the microinstruction execution wait generating circuit 20 is operated to generate a CPU processing wait only when there is a possibility that a page fault may occur. can be significantly reduced. In particular, since a comparator 17 is provided for each page number register 15, the microinstruction execution wait generation circuit 20
It is possible to quickly decide whether to activate or not. Note that even if this configuration is applied to the previous embodiment that does not have the priority register 33, the same effect can be obtained.

[Effects of the Invention] As described above, according to the microinstruction execution control method of the present invention, in a computer system that employs a virtual memory mechanism, among pages existing in main memory, a new write request is generated. CP some of the page numbers of the pages
By storing it inside the U, the next time a write request occurs, it can be determined whether the required page exists in main memory by comparing it with the stored page number. It is something. This method is much simpler in terms of processing and hardware than the conventional method of saving and restoring the CPU state, but it also allows checking for the presence of page faults, which is always necessary at the time of a write request. The execution waiting cycles of the CPU can be significantly reduced, and the processing efficiency of the CPU can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a CPU to which the micro-instruction execution control system of the present invention is applied, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram of a conventional CPU. FIG. 1 is a block diagram showing an example of a computer system with an appropriate instruction execution control method. 11...Virtual address register 14...Page number register group 17...Comparator 20...Micro instruction execution wait generation circuit 32...O
R Gate Agent Patent Attorney Nori Chika Ken Shu Kanshu Sanno - Figure 2 Figure 3

Claims (1)

[Claims] A microcontroller that has a virtual memory function using a paging method and prevents the CPU from moving on to executing the next microinstruction until it becomes clear whether writing to main memory has completed normally or a page fault has occurred. In a computer system having an instruction execution wait generation function, a holding means for holding a page number of a page in a virtual space to which writing has been performed, and a display indicating whether the page number held in the holding means is valid or not. a comparison means for comparing whether or not all valid page numbers held by the holding means and indicated by the display means match the page number indicated by the virtual address; 1. A microinstruction execution control method, comprising: a control means for operating a microinstruction execution wait generating function only when the microinstruction is not detected.