JPS58121457A - Information processing device - Google Patents

Abstract

PURPOSE:To improve the possibility of continuing processing when intermittent troubles occur, by minimizing the time required for waiting register determination and making the instruction retrial at the time of trouble occurrence possible at its maximum. CONSTITUTION:When occurrence of a trouble is detected, an instruction retrial designation 603 is given to an instruction fetching section 1. Especially, when a trouble occurs in the section between operand registers 32 and 33 and the 1st register stack 50, and writing of the 2nd register stack 51 is inhibited by a write inhibiting signal 600, the content of the registers are read out as readout data 510, and a select circuit 53 is selected and outputted as the readout data 510 by a select signal 601. Then, the data oututted from the select circuit 53 is written in an area corresponding to the register in the 1at register stack 50 by a write indicating signal 602.

Description

[Detailed description of the invention] Regarding equipment.

Pipe fin processing is the process of executing an instruction, for example, reading and decoding the instruction, reading the operand, and executing the instruction.
This is a processing method that speeds up the information sensing layer by decomposing the command into two partial processes and executing each partial process in an overlapping manner between instructions.

Conventionally, this type of information processing device, as shown in FIG.
An instruction fetch unit 1 that reads and decodes instructions; a buffer storage unit 2 that has a copy of a portion of the contents of the main memory and can be accessed at high speed; and an instruction execution unit that executes nine operations specified by the instruction. Part 3 stores a group of registers used in operations and stores register operands used in instruction execution (
) is supplied to the instruction processing unit 3, and the calculation result of the instruction execution is sent to the instruction processing unit 3 (
It is provided with a register stack 4 (register group storage device) for storing the output of the instruction execution unit 3.

For the first instruction Iz, instruction reading and decoding processing is performed in the first machine cycle T1.

The process of decoding successive instructions will be referred to as the A phase.

Second machine cycle T! In this case, upon access from the instruction 7 processing unit 1, a memory operand is read from the buffer storage unit 2 and a register operand is read from the register stack 4 and supplied to the instruction execution unit 3. This operand read processing will be referred to as the B phase. In the machine cycle T, the A phase processing for the second instruction is performed in parallel in the instruction 7 step section l.

In the 311th machine cycle T3, the instruction execution unit 3 executes the instruction (E phase), and the operation result of the instruction execution is written to the register stack 4 (W phase). That is, the E phase and the W phase are processed within the same machine cycle T1.On the other hand, the B phase is processed for the instruction 3, and the A7 is processed for the instruction 3.
AIDS's l & ri are done in parallel. In this way,
High-speed processing is possible by overlappingly performing each of the 7 AIDS processes on a plurality of instructions.

FIG. 2 shows each machine cycle T for instructions 1 to I.
8 is a time chart showing an example of processing phases in T and K. In the figure, up to instruction I, each phase process for each instruction is performed in an overlapping manner with a delay of one machine cycle. Since the fourth instruction I4 is an instruction that uses the result of the operation by the instruction IsK as an operand, it has to wait until the W phase is completed in machine cycle T to perform successive operand processing.

That is, for an instruction machine, the machine cycle T.

Waiting for register confirmation occurs in the B phase.

Then, due to the execution of instruction Is in machine cycle T,
.

The operation result is written to the register stack 4, and B-phase processing is performed on the instruction I4 in machine cycle T-.

In the above-mentioned conventional device, if a failure occurs during the calculation processing layer of the instruction execution unit 3, one of the calculation results is also transferred to the ninth storage.
In the case of an instruction that stores the result of an operation in the register stutter 4 within the machine cycle, therefore, the operation is performed according to the contents of the specified register O, and the contents of the register are updated with the result. Then, perform the operation −
Then, the result of K11l) is stored in the register, and the contents of the register before the operation have already disappeared. This problem has the drawback that the command cannot be retried, and it is impossible to continue the II & field by retrying the valid command in the event of an intermittent failure.

In order to solve the above-mentioned drawbacks, there is an apparatus in which the W7 AIDS treatment is carried out in the Omacunnicle after the B phase. In this case, writing can be stopped due to the discovery of a fault such as an operational error, and the II& layer can be continued by retrying the instruction O. FIG. 3 is a time chart showing OJ&7A in each machine cycle for each instruction in such a device. 1) For 0 instructions, a minimum of 41 cycles are required. Namely, Mu, B, B.

Each phase of W requires 11 digits, with each instruction phase typically occurring one machine cycle later than the 7 digits of the instruction. However, instruction 4 is an instruction that uses the result of the operation obtained by executing instruction I as an operand, so it is still an instruction in machine cycles T and T@.

V% rounding and operand O reading cannot be performed unless the operation result is stored in the register. That is, in the B phase of the instruction I4, a register confirmation wait of 2Y syncycles occurs between machine cycles T and T.

Then, the operand is revealed in machine cycle T, the instruction is executed in machine cycle T (E phase), and the operation result is written into register stack 4 in machine cycle T (W phase). 1. performs each phase O island layer in machine cycles T, ~T1. Therefore, in such a device, it is possible to retry the O instruction when a failure occurs, but the performance is degraded (as shown in Fig. 712). The disadvantage is that it takes two machine cycles more time than the other machines. When the register confirmation wait in the 41KB phase is set, the entire Jl ring time is significantly delayed.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks, to minimize the time spent waiting for register confirmation (by operating as shown in Diagram 2), and to maximize instruction retries when a failure occurs. The object of the present invention is to provide a high-speed performance, high-reliability information processing device that increases the possibility of OI/layer continuation in the case of intermittent failures.

The information processing device of the present invention includes an instruction fetch unit that reads and decodes instructions, an instruction execution unit that executes instructions, and an instruction execution unit that executes instructions. a register group storage device for storing a register group, supplying register operands used for instruction execution to the instruction execution section, and storing arithmetic results from instruction execution; In an information communication device that performs pipe-twin sensing by overlapping and executing instructions for multiple instructions, the register group storage device is used for instruction execution.
It has a built-in 10th register stack that supplies the register stutter and stores the calculation results obtained by executing instructions, and a 20th register stack that writes the same data as the above calculation results with a delay of 9 times (from the first register stutter). , monitors the occurrence of IIl'llo in the device, and when a failure occurs, prohibits writing to the second register stack and transfers the contents of the second register stack to the corresponding area of the first register stutter. The system is characterized in that it is equipped with a fault processing circuit that allows instructions to be retried when a fault occurs. .

Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention.

That is, the instruction 7 processing section 1 decodes successive instructions, that is, executes the A phase. The buffer storage section 2 is accessed together with the operand address when the instruction is decoded by the instruction processing section 1, and the memory operand is read out at high speed in the B phase and supplied to the instruction execution section 3. The instruction execution section 3 inputs the memory operand 200 outputted from the buffer storage section 2 and the register operand 500 sent from the register group storage device 5, and executes the instruction (187 steps). That is, a selection circuit 30.31 inputs the instruction execution 113#i memory operation 2nd 200 and register operand 500 and selectively outputs them, and a [1 operand register 32 and , a second operand register 33 that holds the output of the selection circuit 31, and a first operand 320 and a second operand 33 that output these.
With 0 as input, perform nine operations as instructed by the command,
It has a built-in arithmetic circuit 34 that outputs arithmetic result data 340. The above is almost the same as the conventional example shown in FIG.
The first register stack has the same function as the register stack 4 in FIG.
a register stack 50 and a first register stack 5
The data written to 0 is delayed by one machine cycle and the second
a write data register 52 for writing to the register stack 51 of , a second register stack 51 having the same configuration as the register stack 50 of jlll and for writing the output of the write data register 52; a selection circuit 53 which inputs the successive data 510 of 51' and the calculation result data 340 output from the calculation circuit 34, selectively outputs the data selectively, and supplies the output to the first register stack 50 and the write data register 52; It has a built-in. The above first register stack 5
0 reads the register operands necessary for executing the instruction in the B7 aids and supplies the register operand 500 to the instruction execution unit 4, and in the W1 phase the arithmetic circuit 3
The calculation result data 340 output from 4 is written. Further, the second register stack 51 writes the same calculation result data as above at W, 7 AZ, which is one machine cycle later than the W, 7 AZ. The fault processing circuit 6 manages whether or not a fault has occurred in each part within the apparatus, and when detecting the occurrence of a fault, performs command retry processing.

That is, when the occurrence of a failure is detected, an instruction retry instruction 603 is given to the instruction fetch unit 1. However, in particular the second register 32,33 to the first register stack 50
If a failure occurs during this period, writing to the second register stack 51 is inhibited by a write inhibit signal 600, the contents of the register are exposed as exposed data 510, and selected by the selection circuit 53. A signal 601 causes the first reading data 510 to be selectively output. Then, the output data of the selection circuit 53 is written into the area corresponding to the register in the first register stack 50 using a write instruction signal 602. That is, (b) the relevant register in the first register stack 50 is restored to the state before execution of the instruction in which the failure occurred. After this recovery process is completed, an instruction retry instruction 603 is output to the instruction fetch unit 1. This series of operations results in most cases of failure occurring.

If it is an intermittent failure, which is said to occur at a frequency of more than half of all failures (the command can be retried),
Processing can be continued without bringing down the device.

,, Figure 5 shows 7 of the instruction processing according to this embodiment.
It is a time chart showing the relationship between aids and machine cycles. In the figure, phase W1 indicates a phase X in which the calculation result is stored in the first register stack 50, and phase W2 indicates a phase in which the same calculation result as above is written into the second register stack 51. . That is,
In the processing of the instruction processing, A phase processing is performed in machine cycle T8, B phase processing is performed in machine cycle T2, and instruction execution (B phase) and operation result are transferred to the first register stack 50 in machine cycle Ts. A write process (W, phase) is performed. In Machine Cital Ta, the same data as above is used in the second
is written to the register stack 51 of (W, phase), therefore, the processing of instruction I2 takes place in machine cycle T! ~
A, B, E/W, and CF in Ti, respectively.
Wt phase processing is performed. Similar processing is performed for instruction Is with a delay of one machine cycle. Instruction ■4Fi
, is an instruction that uses the operation result of instruction #3, so in machine cycle T, the B phase waits for register confirmation, but the operation result of instruction I, #i □Wl phase in machine cycle T, Since the processing is completed, operands of the instruction I4 can be successively output in the machine cycle T@. That is, instructions can be processed at the same pace as the conventional example shown in FIG. After that, in machine cycle T, the instruction is executed (E phase) and the operation result is written to the first register stack (W,
7 aids) and the same data is written to the second register stack 51 in machine cycle T. Similarly K, command ■.

For K, each of the 7 Azes is performed in machine cycles T. to T.. Substantial Ka machine cycle T,
Then, the processing up to instruction I is completed. That is, it is possible to wet the pipeline at the same speed as in the conventional example shown in FIG.

However, in this example, in the W phase,
Since the same operation result data is written to the second register stack, when a fault occurs, the fault processing circuit 60 controls the fault processing circuit 60 to prevent erroneous data from being written to the second register stack 51 and write the correct register before executing the instruction. Depending on the content, the command can be retried. Moreover, unlike the conventional example shown in FIG. 3, it does not require a lot of time. In other words, the time spent waiting for register confirmation is minimal,
In addition, it is possible to retry instructions to the maximum extent possible when a failure occurs; it is possible to continue processing even in the case of an intermittent failure, and there is an effect that high-speed performance and highly reliable information processing can be achieved.

Above IJ! In the embodiment, o to the second register stack 51
Although the storage of result data is delayed by one machine cycle after writing to the first register, it is also possible to provide two stages of write data registers 52 and to delay by one machine cycle. can. In this case, when a failure occurs, after all the contents of the second register stack 51 are transferred to the first register stack 50, it is possible to return to # for a plurality of instructions and retry the instructions.

Therefore, it is effective even for a failure in which the cause of the failure occurred several instructions ago, for example, and it is possible to further improve reliability. The above-mentioned penetrating write data register can be easily realized by using, for example, a Ruward memory capable of simultaneous writing and storing the operation result of each instruction cyclically in the word direction along with its register number. .

In addition, a computer system to which the present invention is applied performs program II & weir on a process-by-process basis, and one set of register groups is defined for each process, and one set of register groups is defined for each process that is not running. The contents are saved in an area KR for saving in the main memory, and when a process is switched, the contents of the corresponding register group are transferred from the empty area to the register group storage device and the depth of the process is restored after recovery. Therefore, in order to save and restore the contents of the above register group at high speed, in addition to the first register stack that stores the register group corresponding to the currently executing process, there are If the system is equipped with a register group storage device (see Application No. 1856-190516) that has a second register stack that stores multiple sets of register groups corresponding to the processes to be deepened to the first level, This information processing device is the above-mentioned! In order to speed up the process switching process,
Since we already have a second register stack with several times the capacity of the first register stack, we add a write data register to delay writing to the second register stack, and It is possible to perform a retry in the event of a failure by controlling the remedial circuit. In other words, the present invention can be applied to improve retry performance without substantially increasing the amount of metal objects.

As described above, in the present invention, there is provided a first register stack in which operation result data according to an instruction depth is written in the same machine cycle as the machine cycle of the instruction depth, and a second register stack in which data is written with a delay. Because of this structure, even for instructions that use the operation result data of the previous instruction as an operand, it is possible to minimize the period of waiting for register confirmation in the operand read 7A. There is a high possibility of retrying. That is, since it has the possibility of retrying instructions without prolonging processing time, it has the great effect of enabling high-speed, highly reliable information processing.

[Brief explanation of drawings]

agt5! J is a block diagram showing an example of an information processing Jji device that performs conventional pipe 2-in processing, Fig. 2 is a time chart for explaining the operation of the above conventional example, and Fig. j13 is a time chart showing the operation of another conventional example. FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is a time chart for performing the operation of the above embodiment. Li[, 1-instruction fetch section, 2... buffer storage section, 3... instruction execution section, 4... register stack, 5... register details storage device, 6... failure sensitive layer Circuit, 30.31... Selection circuit, 32.-gi operand register, 33.-second operand register, 3
4... Arithmetic circuit, 50... first register stack,
51--Register stutter of g2, 52--Write data register, 53--Selection circuit, A--Instruction reading/decoding phase, B--Successive operand output phase, E--Instruction The execution phase of W , W, ,
Wt: Storage phase of calculation results. Agent Patent Attorney Sumi 1) Toshi Sono Figure 2 Figure 3 M-7 Machine 1 Cycle Figure 4 et al. Figure 5 M-Machine T Cycle

Claims (1)

[Claims] An instruction fetch unit that reads and decodes instructions; an instruction execution unit that executes instructions; ! a register group storage device that stores a register group, supplies register operands used for instruction execution to the instruction execution unit, and stores the operation result of instruction execution, and can perform instruction decoding, operand reading, and instruction In an information processing device that performs pipeline l&n by over-doubling and executing multiple instructions, the register group storage device supplies register operands used in instruction execution and stores the arithmetic results of instruction execution. a first register stutter for storing;
It has a built-in 20th register stack that writes the same data as the above calculation result at a delay of 9 timings to the 10th register stack, and monitors the 6 faulty OIl output in the current register and when a fault occurs. A fault processing circuit is provided that prohibits writing to the second register stutter and writes the contents of the second register stack to a corresponding area of the first register stutter, and retrying the instruction when a fault occurs. An information processing device characterized by being capable of.