CN100367213C - System and method with automatically backing up and recovering data in register - Google Patents
System and method with automatically backing up and recovering data in register Download PDFInfo
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Abstract
The present invention relates to a system with capabilities of automatic backup and recovery of data in registers. The system comprises an ordinary register pile, a backup register pile, at least one backup mode signal and at least one input selection controller, wherein the ordinary register pile is provided with a plurality of ordinary registers; the backup register pile is provided with a plurality of backup registers. By using the system, when an abnormal interruption event arises, a backup mode is determine according to the abnormal interruption event; the content of at least one ordinary register is copied to at least one corresponding backup register according to the backup mode; when the abnormal interruption event is ended, at least one controller is utilized to recover the content of the corresponding ordinary register from the backup register according to the backup mode. Therefore, when the abnormal interruption event arises, the system of the present invention has the effect of reducing data moving action between a memory and registers; besides, the system of the present invention is operated in a single mode, so the present invention does not need to utilize selection mode bits like the conventional technology to determine the registers which can be accessed in different operation modes. Therefore, the system of the present invention does not need to select mode bits; the time of accessing the registers can be reduced.
Description
Technical field
The present invention relates to a kind of system and method, in detail, relate to the system and method that is applied to microprocessor architecture with automated back-up and recovering data in register with automated back-up and recovering data in register.
Background technology
, all quite similar in idea in the structure of general microprocessor for the hardware mechanism practice of handling the aborted incident.When the aborted incident of generation, microprocessor can enter the operator scheme of a processing aborted incident, and before the secondary program that jumps to this aborted incident of processing, must store away by first state some microprocessors, so that when returning after the aborted event handling, original program can continue to carry out.
Therefore, in the enforcement of hardware, a register must be arranged at least, and (PC ProgramCounter), also must have some registers in order to store the state of this microprocessor in order to the stored programme count value.If segmentation may also have some background registers again, as: record is that the register of which kind of aborted incident etc. takes place, and these background registers generally all are called the specific use register.And processor is after entering aborted event handling pattern, no matter be which kind of aborted incident, except the secondary program difference of handling exception, for can access register (general register or specific use register) all be identical, not not respectively, just because no matter in any exception operator scheme, can access register be the same, therefore before the relevant action of underway disconnected secondary program, we just must content stored in memory with these registers in, and before interrupting that secondary program behavior finishes and interruption returns, also must return and deposit to former register by the register value that will before deposit in the storer, wait to interrupt returning, original program just can continue normal execution.Yet these secondary call programs or interrupt handling routine must be spent more extra instruction and finish data-moving between storer and the register, in order to reduce the data-moving action between this kind storer and the register, improve mechanism so developed some.
With reference to United States Patent (USP) the 5th, 159, No. 680, its patent name is " RISC processing unit whichselectively isolates register windows by indicating usage of adjacent registerwindows in status register ", this patent is that Sun Microsystems company is in order to reduce microprocessor in the required added burden of spending more expense of call program, develop and register form (register windows) mechanism, and be applied on SPARC (the Scalable Processor Architecture) microprocessor, this mechanism makes the SPARC processor that very good performance can be arranged.The maximum characteristics of this mechanism of register form be exactly each register form some register of being adjacent the register form be (overlapping) that overlaps, can reach the purpose that fast message transmits between internal processes by this kind mechanism, and since each program all have some registers of oneself be other program can not access, deposit so when program is switched, just needn't move the contents value of own register to storer earlier, so also significantly reduced the data-moving action of switching between the program between required storer and register.Yet, the register form of SPARC processor is the practice of trading space for time, the increase of register form number will increase chip area greatly and be non-constant with regard to the service efficiency of register, must do different considerations according to different applied environments.
With reference to United States Patent (USP) the 5th, 701, No. 493, its patent name is " Exception handling method andapparatus in data processing systems ", this patent is that the ARM microprocessor of ARM company is for the aborted event processing mechanism, be different from United States Patent (USP) the 5th, 159, No. 680, its topmost difference just can utilize different operation modes to differentiate different aborted incident kenels at arm processor, be not only to have only a kind of aborted event handling pattern, and the register that every kind of operator scheme can be controlled (access) is also different.Arm processor is if accept interruption, and then processor will switch under the different patterns according to different interruptions and carry out, and has six kinds of different patterns.With reference to figure 1, it shows that a register file 10 has the configuration of six kinds of registers 11,12,13,14,15 and 16.Wherein, five positions in the register CPSR are in order to judge six kinds of different operation modes.
In addition, please refer to United States Patent (USP) the 5th, 386, No. 563, its patent name is " Register substitutionduring exception processing ", and this patent also is the patent of ARM company.Under different patterns, its exclusive stock's register (banked registers) is arranged, be can not access under other patterns, purpose is exactly to switch the data-moving action that promptly reduces between storer and the register in order to reach quick mode, and this is the great advantage of this patent design stock register.
With reference to No. the 494644th, Republic of China's patent announcement, its patent name is " select the method for access function resister ", this patent is that the former scientific ﹠ technical corporation of intelligence has done a little change at stock's register of ARM company, six kinds of patterns are transformed into two kinds of patterns, be called translative mode 0 and translative mode 1, its purpose is to reduce the required figure place and the time of the pattern of choosing.
Yet above-mentioned patent is not the switching that needs form, needs the switching of different mode exactly, to select the register of the final access of being wanted, therefore needs the position that control is switched, and can increase the time of access function resister.Therefore, be necessary to provide the system and method for a kind of innovation and tool progressive, to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of system with automated back-up and recovering data in register, it comprises: general register heap, back-up registers heap, a backup mode signal and at least one input selection control.This general register heap has a plurality of general registers, in order to the storage data.This back-up registers heap has a plurality of back-up registers, in order to the data of storage from these general registers, this back-up registers heap is divided into a plurality of backup modes, each backup mode has at least one back-up registers, determines the annexation of these back-up registers and these general registers according to these backup modes.This backup mode signal determines the backup mode of this back-up registers heap in order to according to a plurality of aborted incidents.This input selection control will be in order to inputing to corresponding general register from the reduction of data of backup register.Determine the annexation of this input selection control and these general registers and these back-up registers according to these backup modes.
Utilize system of the present invention, when an aborted incident takes place,, determine a backup mode according to this aborted incident.According to this backup mode, store the interior data of at least one general register automatically again to corresponding at least one back-up registers.When this aborted incident finishes,,, the reduction of data in this back-up registers is inputed to corresponding general register via at least one input selection control according to this backup mode.
Therefore, system of the present invention, when the aborted incident takes place, except that the effect that can have the data-moving action that reduces between storer and the register, because system of the present invention is the single operation pattern, so do not need to utilize the preference pattern position with the accessible register under the decision different operation modes as conventional technology.Therefore system of the present invention does not need the preference pattern position, can reduce the access function resister time.
Description of drawings
Fig. 1 is the synoptic diagram of conventional register file configuration;
Fig. 2 has the structural drawing of the system of automated back-up and recovering data in register for first embodiment of the invention;
Fig. 3 has the structural drawing of the system of automated back-up and recovering data in register for second embodiment of the invention;
Fig. 4 is the synoptic diagram of a plurality of aborted incidents of the system handles of second embodiment of the invention;
Fig. 5 A is the time of its back-up storage of explanation system of the present invention and instruction overlapping synoptic diagram retrieval time of aborted incident;
Fig. 5 B is the time of its back-up storage of explanation system of the present invention and the overlapping synoptic diagram of instruction decode time of aborted incident;
Fig. 5 C is the time of its back-up storage of explanation system of the present invention and overlapping synoptic diagram instruction time of aborted incident; And
Fig. 6 is the synoptic diagram of time before the time of aborted incident instruction of its back-up storage of explanation system of the present invention.
Embodiment
See also Fig. 2, it shows the one-piece construction figure that first embodiment of the invention has the system 20 of automated back-up and recovering data in register.The system 20 of first embodiment of the invention comprises: general register heap 201, one back-up registers heap 202, one backup mode signal 203, seven input selection controls 204 to 210, a multiplexer 211, a logical operation processing unit 212 and an external memory storage 213.
This general register heap 201 has 16 general registers (R0 to R15), in order to the storage data.Under normal procedure operation, this general register heap from this external memory storage 213 and the data selected through this multiplexer 211, and is sent in addition calculation process of this logical operation processing unit 212 with the data of being stored in order to storage.This multiplexer 211, logical operation processing unit 212 and this external memory storage 213 are called an external device (ED) at this.This multiplexer 211 can be in order to select the input as general register in this general register heap 201 of this logical operation processing unit 212 or this external memory storage 213.
This back-up registers heap 202 has 15 back-up registers (BR0_BM5, BR1_BM5, BR2_BM5, BR3_BM5, BR4_BM5, BR5_BM1, BR6_BM2, BR7_BM3, BR8_BM4, BR9_BM5, BR10_BM1, BR11_BM2, BR12_BM3, BR13_BM4 and BR14_BM5), when being used to the generation of aborted incident, storage is from the data of these general registers.This back-up registers heap 202 is divided into five backup modes (BM1 to BM5), each backup mode has at least one back-up registers, and for example the first backup mode BM1 has two back-up registers BR5_BM1 and BR10_BM1, the second backup mode BM2 has two back-up registers BR6_BM2 and BR11_BM2, the 3rd backup mode BM3 has two back-up registers BR7_BM3 and BR12_BM3, the 4th backup mode BM4 has two back-up registers BR8_BM4 and BR13_BM4 and the 5th backup mode BM5 and has seven back-up registers BR0_BM5, BR1_BM5, BR2_BM5, BR3_BM5, BR4_BM5, BR9_BM5 and BR14_BM5.
This backup mode signal 203 is in order to determine the backup mode of this back-up registers heap 202 according to a plurality of aborted incidents, owing to have five kinds of backup modes in the present embodiment, therefore, this backup mode signal 203 must have three positions.If hardware structural design person has defined five kinds of aborted incident occurrence causes (for example: SVC, ABT, IRQ, UNDEF, FIQ etc.), then backup mode just can be divided into corresponding five kinds of backup modes, every kind of backup mode all can optionally be stipulated specific backup rules, and determines the annexation of these general registers and these back-up registers.Also be, the data that this backup rules defines the general register in these general registers heap 201 must store the corresponding back-up registers in the back-up registers heap 202 into, and for example: the two back-up registers BR5_BM1 of the first backup mode BM1 and BR10_BM1 are connected to two general register R13 and R14 of general register heap 201 respectively.
Therefore, when the aborted incident takes place, then according to its corresponding backup mode, for example: first backup mode is stored to the general register R13 in the general register heap 201 and the data in the R14 respectively in the back-up registers BR5_BM1 and BR10_BM1 in this back-up registers heap 202.
These input selection controls 204 to 210 input to corresponding general register in order to the reduction of data with back-up registers.Determine the annexation of this input selection control and these general registers and these back-up registers according to these backup modes.
Each input selection control all has at least two input ports and an output port, an input port wherein is connected to the multiplexer of this external device (ED), another input port is connected to corresponding back-up registers, and this output port is connected to corresponding general register.For example: an input port of the first input selection control 204 is connected to the output of this multiplexer 211, and another input port is connected to back-up registers BR0_BM5, and its output port is connected to general register R8.One input port of the 7th input selection control 210 is connected to the output of multiplexer 211, other input ports are connected to back-up registers BR10_BM1, BR11_BM2, BR12_BM3, BR13_BM4, BR14_BM5, and its output port is connected to general register R14.Therefore the input that can control this general register of this input selection control is from back-up registers, or from this multiplexer.
Therefore, after the aborted incident finishes, then according to its previous corresponding backup mode, for example: first backup mode, will be when the aborted incident takes place, be stored in back-up registers BR5_BM1 and the interior data of BR10_BM1 in this back-up registers heap 202, be stored in the general register R13 and R14 in the general register heap 201, via the 6th input selection control 209 and the 7th input selection control 210 reduction again so that microprocessor continues the program before the execute exception interrupt event takes place.
See also Fig. 3, it shows the one-piece construction figure that second embodiment of the invention has the system 30 of automated back-up and recovering data in register.System 30 of the present invention comprises: general register heap 301, one back-up registers heap 302, one backup mode signal 303, a reduction-mode signal 304, seven input selection controls 305 to 311, a multiplexer 312, a logical operation processing unit 313 and an external memory storage 314.
This general register heap 301 has 16 general registers (R0 to R15), in order to the storage data.Under the normal procedure operation, this general register heap from this external memory storage 314 and the data selected through this multiplexer 312, and is sent in addition calculation process of this logical operation processing unit 313 with the data of being stored in order to storage. and this multiplexer 312, logical operation processing unit 313 and this external memory storage 314 are called an external device (ED) at this.This multiplexer 312 can be in order to select the input as general register in this general register heap 301 of this logical operation processing unit 313 or this external memory storage 314.
This back-up registers heap 302 has 22 back-up registers (BR0_M5, BR1_M6, BR2_M5, BR3_M6, BR4_M5, BR5_M6, BR6_M5, BR7_M6, BR8_M5, BR9_M6, BR10_M1, BR11_M2, BR12_M3, BR13_M4, BR14_M5, BR15_M6, BR16_M1, BR17_M2, BR18_M3, BR19_M4, BR20_M5 and BR21_M6), when being used to the generation of aborted incident, storage is from the data of these general registers.This back-up registers heap 302 is divided into six patterns (M-1M6), each pattern is divided into backup mode and reduction-mode again, each pattern has at least one back-up registers, and for example first pattern (comprising first backup mode and first reduction-mode) has two back-up registers BR10_M1 and BR16_M1, second pattern (comprising second backup mode and second reduction-mode) has two back-up registers BR11_M2 and BR17_M2, three-mode (comprising the 3rd backup mode and the 3rd reduction-mode) has two back-up registers BR12_M3 and BR18_M3, four-mode (comprising the 4th backup mode and the 4th reduction-mode) has two back-up registers BR13_M4 and BR19_M4, the 5th pattern (comprising the 5th backup mode and the 5th reduction-mode) has seven back-up registers BR1_M5, BR2_M5, BR4_M5, BR6_M5, BR8_M5, BR14_M5 and BR20_M5 and the 6th pattern (comprising the 6th backup mode and the 6th reduction-mode) have seven back-up registers BR1_M6, BR3_M6, BR5_M6, BR7_M6, BR9_M6, BR15_M6 and BR21_M6.
This backup mode signal 303 is in order to determine the backup mode of this back-up registers heap 302 according to a plurality of aborted incidents, this reduction-mode signal 304 is in order to determine the reduction-mode of this back-up registers heap 302 according to a plurality of aborted incidents.If hardware structural design person has defined five kinds of aborted incident occurrence causes (for example: SVC, ABT, IRQ, UNDEF, FIQ etc.), then back-up registers can be divided into six kinds of patterns (five aborted incidents add a sharing model), and each pattern includes a backup mode and a reduction-mode.Every kind of backup mode and reduction-mode all can optionally be stipulated specific backup rules and meta-rule also.The data that backup rules defines the general register in these general registers heap 301 must store the corresponding back-up registers in the back-up registers heap 302 into, and for example: two back-up registers BR10_M1 of first backup mode and BR16_M1 are connected to two general register R13 and R14 of general register heap 301 respectively.
These input selection controls 305 to 311 will input to corresponding general register from the reduction of data of backup register in order to control.The data of back-up registers must be reduced and be stored corresponding general register in the general register heap 301 in these back-up registers heaps 302 of reduction rule definition.
Each input selection control all has at least three input ports and an output port, an input port wherein is connected to the multiplexer of this external device (ED), two input ports are connected to corresponding back-up registers in addition, and this output port is connected to corresponding general register.For example: an input port of the first input selection control 305 is connected to the output of this multiplexer 312, one input port is connected to back-up registers BR0_M5, another input port is connected to back-up registers BR1_M6, and its output port is connected to general register R8.One input port of the 7th input selection control 311 is connected to the output of multiplexer 312, other input ports are connected to back-up registers BR16_M1, BR17_M2, BR18_M3, BR19_M4, BR20_BM5 and BR21_M6, and its output port is connected to general register R14.Therefore the input that can control this general register of this input selection control is from back-up registers, or from this multiplexer.
The automatic storage of the system 30 of second embodiment of the invention and the method for recovering data in register, different with the system 20 of first embodiment.The system 30 of second embodiment of the invention has backup mode signal 303 and reduction-mode signal 304 simultaneously, no matter take place or aborted incident when returning in the aborted incident, all corresponding backup mode of foundation and reduction-mode be done the action of backup-and-restore simultaneously.Also promptly, when an aborted incident takes place, must do once backup and the once action of reduction simultaneously according to corresponding backup mode and reduction-mode; When returning an aborted incident, must do once backup and the once action of reduction simultaneously according to corresponding backup mode and reduction-mode.
When the system 20 of first embodiment of the invention takes place in the aborted incident, carry out the register data backup; When the aborted incident is returned, carry out the register data reduction, the backup-and-restore of data is to take place separately.The system 30 of second embodiment of the invention when the aborted incident takes place, carries out the register data backup-and-restore; When the aborted incident is returned, carry out the register data backup-and-restore, the backup-and-restore of data is to take place simultaneously.
See also shown in Figure 4ly, occur as the actual operation of the system 30 of example explanation second embodiment of the invention with a plurality of aborted incidents of reality.In when, under the USR state IRQ aborted incident (being defined as four-mode M4 in the present embodiment) taking place when, state (USR state) and backup mode (the 6th backup mode) when then interrupt taking place according to this are stored to this back-up registers respectively with the general register R13 in the general register heap 301 and the data A13 in the R14 and A14 and pile in the back-up registers BR15_M6 and BR21_M6 in 302; Comply with state (USR state) and reduction-mode (the 4th reduction-mode) when wherein broken hair is given birth to simultaneously, with back-up registers BR13_M4 and data B13 in the BR19_M4 and the B14 in the back-up registers heap 302, reduction is stored in the general register R13 and R14 in the general register heap 301.
When system when handling IRQ aborted incident, one FIQ aborted incident (being defined as the 5th pattern M5 in the present embodiment) takes place again, state (IRQ aborted state) and backup mode (the 4th backup mode) when then interrupting taking place according to this, data C8 to C12 in the general register R8 to R12 in the general register heap 301 is stored to respectively in the back-up registers BR1_M6 to BR9_M6 in this back-up registers heap 302, and the general register R13 in the general register heap 301 and the data C13 in the R14 and C14 are stored to respectively in the back-up registers BR13_M4 and BR19_M4 in this back-up registers heap 302; Comply with state (IRQ aborted state) and reduction-mode (the 5th reduction-mode) when wherein broken hair is given birth to simultaneously, with the data D8 to D14 in the back-up registers BR0_M5 to BR20_M5 in the back-up registers heap 302, reduction is stored in the general register R8 to R14 in the general register heap 301.
After the intact FIQ aborted incident of system handles, in the time of must returning this IRQ aborted incident, then according to state (FIQ aborted state) and the backup mode (five backup mode) of this interruption when returning, the data E8 to E14 in the general register R8 to R14 in the general register heap 301 is stored to this back-up registers respectively piles in the back-up registers BR0_M5 to BR20_M5 in 302; State (FIQ aborted state) and reduction-mode (the 4th reduction-mode) when returning according to its interruption simultaneously, with the data C8 to C12 in the back-up registers BR1_M6 to BR9_M6 in the back-up registers heap 302, reduction is stored in the general register R8 to R12 in the general register heap 301, and the back-up registers BR13_M4 in this back-up registers heap 302 and the data C13 in the BR19_M4 and C14 reduction are stored in the general register R13 and R14 in the general register heap 301.
Therefore, system can be kept at and handle when FIQ aborted incident takes place the data C8 to C14 of IRQ aborted incident.And after handling FIQ aborted incident, can reduce these data C8 to C14, so that continue to handle IRQ aborted incident to this system.
After the intact IRQ aborted incident of system handles, in the time of must returning this USR state, then according to state (IRQ aborted state) and the backup mode (four backup mode) of this interruption when returning, the general register R13 in the general register heap 301 and the data F13 in the R14 and F14 are stored to this back-up registers respectively pile in the back-up registers BR13_M4 and BR19_M4 in 302; State (IRQ aborted state) and reduction-mode (the 6th reduction-mode) when returning according to its interruption simultaneously, with back-up registers BR15_M6 and data A13 in the BR21_M6 and the A14 in the back-up registers heap 302, reduction is stored in the general register R13 and R14 in the general register heap 301.
Therefore, system can be kept at and handle when IRQ aborted incident takes place the data A13 and the A14 of normal USR state.And after handling IRQ aborted incident, can reduce these data A13 and A14, so that continue to handle normal USR state to this system.
With reference to figure 5A, its system applies that shows the present invention first and second embodiment is in the sequential synoptic diagram of the aborted event handling of a microprocessor.Fig. 5 A to Fig. 5 C only illustrates the sequential that the system of the first order second embodiment stores, and reduction point storage time of the second embodiment system also some storage time with Fig. 5 A to Fig. 5 C is identical, does not add at this and gives unnecessary details.Clock 1 among the figure, clock 2 etc. are the clock period, are first clock period and second clock cycle etc. in regular turn.Suppose that in the present embodiment present microprocessor is to have three pipelines (pipeline) structure, the execution of each instruction all needs through following three phases: instruction retrieval phase (Instruction Fetch Stage:IF), instruction decode stage (Instruction Decode Stage:ID) and the execution phase (Instruction Execution Stage:EXE).
Shown in Fig. 5 A, first instruction of supposing master routine is the LDR instruction, and second instruction is the ADD instruction, and B is the next instruction of required execution after the generation FIQ aborted, and FIQ_Handler is a tag addresses.In first clock period (clock 1), first instruction LDR carries out LDR instruction retrieval (IF) action.In second clock period (clock 2), first instruction LDR carries out LDR instruction decoding (ID) action, and second instruction ADD carries out ADD instruction retrieval (IF) action simultaneously.In the 3rd clock period (clock 3), first instruction LDR carries out the LDR instruction and carries out (EXE) action, and second instruction ADD carries out ADD instruction decoding (ID) action.Suppose to take place at this moment rapid abnormal and interrupt (FIQ), will make that second instruction ADD is invalid, program skips to the next instruction B that required execution after the aborted takes place.
In the 4th clock period (clock 4), system of the present invention is according to the FIQ backup rules of defined among the backup mode FIQ, with the content replication in the general register in the back-up registers of foundation FIQ backup rules defined.Simultaneously, in the 4th clock period (clock 4), the B of FIQ aborted incident instruction then carrying out simultaneously B instruction retrieval (IF) action.Also promptly, the time point of storage (Backup) is overlapping with instruction retrieval (IF) time point that the next instruction of required execution after the aborted takes place, and therefore, whole microprocessor system can't be spent more the time and go to carry out the backup actions of system of the present invention.
Shown in figure 5B, in this embodiment, the time point of back-up storage (Backup) is overlapping with instruction decoding (ID) time point that the next instruction of required execution after the aborted takes place.The time point of this back-up storage (Backup) is in the 5th clock period (clock 5), relatively is to delay a clock period with Fig. 5 A, and overlapping with instruction decoding (ID) stage of B instruction.Carry out back-up storage at this time point and can backup to value in the correct general register yet, and whole microprocessor system can not spent more the time yet and goes to carry out the back-up storage action of system of the present invention.
Shown in figure 5C, in this embodiment, the time point of back-up storage (Backup) is that to carry out (EXE) time point overlapping with the instruction that the next instruction of required execution after the aborted takes place.The time point of this back-up storage (Backup) is in the 6th clock period (clock 6), relatively is to prolong latter two clock period with Fig. 5 A, and overlapping with instruction execution (EXE) stage of B instruction.Carry out back-up storage at this time point and can backup to value in the correct general register yet, and whole microprocessor system can not spent more the time yet and goes to carry out the back-up storage action of system of the present invention.
As mentioned above, the time point of system of the present invention its automated back-up storage, be with this aborted incident of generation after performed next instruction instruction retrieval, instruction decoding or instruction time point overlapping.Similarly, after finishing this aborted incident, its automatic time point of reduction storage of system of the present invention, be with the instruction retrieval of finishing next instruction performed after this aborted incident, instruction decoding or instruction time point overlapping.Therefore, no matter system of the present invention all can not increase the extra time of whole microprocessor system in the automated back-up storage or the storage of reducing automatically.
Yet, the time point of system of the present invention its automated back-up storage, need not with the instruction retrieval of performed next instruction after this aborted incident of generation, instruction decoding or instruction time point overlapping.The time point of this automated back-up can be before the time point of next instruction performed after this aborted incident of generation.With reference to shown in Figure 6, the time point of its back-up storage of system of the present invention (Backup) is that the instruction of the next instruction of required execution after aborted takes place is retrieved (IF) time point (the 5th clock period clock 5) before in the 4th clock period (clock 4).Similarly, system of the present invention its automatically the time point of reduction storage can be after finishing this aborted incident before the time point of performed next instruction.
Therefore, system of the present invention, when the aborted incident takes place, except that the effect that can have the data-moving action that reduces between storer and the register, because system of the present invention is that the single operation pattern is (after the backup mode decision, directly specific general register is stored to corresponding back-up registers), so do not need to utilize the preference pattern position with the back-up registers under the decision different operation modes as conventional technology.Therefore system of the present invention does not need the preference pattern position, can reduce the access function resister time.
In addition, compare with register form and stock's register of routine, system of the present invention can reduce chip area and access time.
But the foregoing description only is explanation principle of the present invention and its effect, and unrestricted the present invention.Therefore, the person of ordinary skill in the field can make amendment to the foregoing description without prejudice to spirit of the present invention and change.Interest field of the present invention claim as described later is listed.
Claims (25)
1. system with automated back-up and recovering data in register, it comprises:
One general register heap has a plurality of general registers, in order to the storage data;
It is characterized in that also comprising:
One back-up registers heap, have a plurality of back-up registers, in order to the data of back-up storage from described general register, this back-up registers heap is divided into a plurality of backup modes, each backup mode has at least one back-up registers, the described backup mode of foundation determines the annexation of described back-up registers and described general register, and the backup mode of this back-up registers heap is by a backup mode signal deciding, according to a plurality of aborted incidents decision backup mode signals; With
At least one imports selection control, in order to control with the data in the described back-up registers, reduction inputs to corresponding described general register, determines the annexation of this input selection control and described general register and described back-up registers according to described backup mode.
2. the system as claimed in claim 1, wherein this general register heap has 16 general registers, and this back-up registers heap has 15 back-up registers.
3. the system as claimed in claim 1, according to a reduction-mode, control is with the data in the described back-up registers, and reduction inputs to corresponding described general register, reduction-mode is by a reduction-mode signal deciding, according to a plurality of aborted incident decision reduction-mode signals.
4. system as claimed in claim 3, wherein this general register heap has 16 general registers, and this back-up registers heap has 22 back-up registers.
5. as claim 1 or 3 described systems, wherein said general register and described back-up registers are 32 bit registers.
6. as claim 1 or 3 described systems, wherein this input selection control has an output port and at least two input ports, an input port wherein is connected to an external device (ED), another input port is connected to corresponding back-up registers, and this output port is connected to corresponding general register.
7. system as claimed in claim 6, wherein this external device (ED) comprises a multiplexer, a logical operation processing unit and an external memory storage.
8. the method for automated back-up and recovering data in register is characterized in that may further comprise the steps:
(a) when an aborted incident takes place,, determine a backup mode according to this aborted incident;
(b) according to this backup mode, automated back-up is stored the interior data of at least one general register to corresponding at least one back-up registers; And
(c) when this aborted incident finishes, according to this backup mode, via at least one input selection control, with the data in the described back-up registers, reduction inputs to described corresponding general register.
9. method as claimed in claim 8, other comprises the step that determines described back-up registers and described general register annexation according to this backup mode.
10. method as claimed in claim 8, other comprises the step that determines described input selection control and described general register and described back-up registers annexation according to this backup mode.
11. method as claimed in claim 8 is the aborted event handling that is applied to a microprocessor, wherein in step (b), the time point of automated back-up storage is before the time point of next instruction performed after this aborted incident of generation.
12. method as claimed in claim 8 is the aborted event handling that is applied to a microprocessor, wherein in step (c), the time point of reduction storage automatically is before the time point of next instruction performed after finishing this aborted incident.
13. method as claimed in claim 8 is the aborted event handling that is applied to a microprocessor, wherein in step (b), the time point of automated back-up storage, be with this aborted incident of generation after the time point of performed next instruction overlapping.
14. method as claimed in claim 8 is the aborted event handling that is applied to a microprocessor, wherein in step (c), the time point of reduction storage automatically is overlapping with the time point of finishing next instruction performed after this aborted incident.
15. as claim 13 or 14 described methods, wherein the time point of this automated back-up storage or reduction storage automatically is the retrieval phase that is this next instruction.
16. as claim 13 or 14 described methods, wherein the time point of this automated back-up storage or reduction storage automatically is the decode phase that is this next instruction.
17. as claim 13 or 14 described methods, wherein the time point of this automated back-up storage or reduction storage automatically is the execute phase that is this next instruction.
18. the method for automated back-up and recovering data in register is characterized in that may further comprise the steps:
(a) when an aborted incident takes place,, determine a backup mode and that interrupts taking place to interrupt the reduction-mode that takes place according to this aborted incident;
(b) backup mode that takes place according to this interruption, automated back-up is stored the interior data of at least one general register to corresponding back-up registers, and interrupt the reduction-mode of generation according to this, via at least one input selection control, with the data at least one back-up registers, reduction is stored to corresponding general register automatically;
(c) when an aborted incident finishes,, determine a backup mode and that interrupts returning to interrupt the reduction-mode that returns according to this aborted incident; And
(d) backup mode that returns according to this interruption, automated back-up is stored the interior data of at least one general register to corresponding back-up registers, and the reduction-mode that returns according to this interruption, via at least one input selection control, with the data at least one back-up registers, reduction is stored to corresponding general register automatically.
19. method as claimed in claim 18, it is the aborted event handling that is applied to a microprocessor, wherein in step (b), the automated back-up that interrupts taking place is stored the time point with automatic reduction storage, is before the time point of next instruction performed after this aborted incident of generation.
20. method as claimed in claim 18, it is the aborted event handling that is applied to a microprocessor, wherein in step (d), the storage of automated back-up that interruption is returned and the time point of reduction storage automatically are before the time point of next instruction performed after finishing this aborted incident.
21. method as claimed in claim 18, it is the aborted event handling that is applied to a microprocessor, wherein in step (b), the automated back-up storage that interrupt to take place and the time point of reduction storage automatically, be with this aborted incident of generation after the time point of performed next instruction overlapping.
22. method as claimed in claim 18, it is the aborted event handling that is applied to a microprocessor, wherein in step (d), the storage of automated back-up that interruption is returned and the time point of reduction storage automatically are overlapping with the time point of finishing next instruction performed after this aborted incident.
23. as claim 21 or 22 described methods, wherein the time point of this automated back-up storage or reduction storage automatically is the retrieval phase that is this next instruction.
24. as claim 21 or 22 described methods, wherein the time point of this automated back-up storage or reduction storage automatically is the decode phase that is this next instruction.
25. as claim 21 or 22 described methods, wherein the time point of this automated back-up storage or reduction storage automatically is the execute phase that is this next instruction.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100805223A CN100367213C (en) | 2004-09-30 | 2004-09-30 | System and method with automatically backing up and recovering data in register |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100805223A CN100367213C (en) | 2004-09-30 | 2004-09-30 | System and method with automatically backing up and recovering data in register |
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| CN1755632A CN1755632A (en) | 2006-04-05 |
| CN100367213C true CN100367213C (en) | 2008-02-06 |
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| CN110769317A (en) * | 2018-07-27 | 2020-02-07 | 晨星半导体股份有限公司 | Image processing circuit and backup/restore method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1030311A (en) * | 1987-07-01 | 1989-01-11 | 数字设备公司 | The equipment and the method for control asynchronous routine interrupt event in the data handling system |
| CN1224871A (en) * | 1998-01-30 | 1999-08-04 | 国际商业机器公司 | Method and system for handling multiple store instruction completions in processing system |
| JP2002073394A (en) * | 2000-09-01 | 2002-03-12 | Dainippon Printing Co Ltd | Data-transfering system with funtion for recovery by remote control |
| US6560719B1 (en) * | 2000-05-17 | 2003-05-06 | Unisys Corporation | Method for recovery of original registry key file data |
-
2004
- 2004-09-30 CN CNB2004100805223A patent/CN100367213C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1030311A (en) * | 1987-07-01 | 1989-01-11 | 数字设备公司 | The equipment and the method for control asynchronous routine interrupt event in the data handling system |
| CN1224871A (en) * | 1998-01-30 | 1999-08-04 | 国际商业机器公司 | Method and system for handling multiple store instruction completions in processing system |
| US6560719B1 (en) * | 2000-05-17 | 2003-05-06 | Unisys Corporation | Method for recovery of original registry key file data |
| JP2002073394A (en) * | 2000-09-01 | 2002-03-12 | Dainippon Printing Co Ltd | Data-transfering system with funtion for recovery by remote control |
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