JPH0256029A - General register switching system - Google Patents

Abstract

PURPOSE:To minimize the hardware quantity of a general register set and to change an area at a high speed by constituting only one overall general register set of a register group of the largest number of pieces, and constituting other machine instruction designating general register set of only the largest number of general registers which can be used by a machine instruction. CONSTITUTION:A first overall general register set 17 is constituted of plural areas corresponding to plural modes, and each area has the largest number of registers which can be instructed by a machine instruction. Also, a second machine instruction designating general register set 19 has an area of the number of registers of each area of the register set 17, and each register number thereof can be designated by only the machine instruction. At the time of changing a mode such as an instruction or an interruption, etc., by the machine instruction, a control means 23 changes the contents of a register group selecting register 20, and also, executes a control so that data of the register set 17 is transferred directly from the register set 17 to each general register set 19 simultaneously.

Description

[Detailed Description of the Invention] [Summary] Regarding a general-purpose register switching method instructed by a machine instruction, a general-purpose register switching method that minimizes the hardware amount of a general-purpose register set and can change areas at high speed is provided. In a central processing unit that decodes instructions read from a main memory, inputs data, performs operations, and then processes the data by setting it in a general-purpose register or transferring it to the main memory. , a first general-purpose register set means that is composed of a plurality of areas corresponding to a plurality of modes, each of which has a register that can be specified by a machine instruction, and a logic other than logical division that includes the first general-purpose register set means. a second general-purpose register set means which is located within the division and has an area corresponding to the number of registers in each area of the first general-purpose register set means, each register of which can be specified by a machine instruction; register group selection register means for specifying each area of the register set means and setting upper address bits corresponding to each mode; a register designation signal for specifying registers in each area of the first general-purpose register set means; an instruction register means capable of setting a machine instruction including a register designation signal specifying a register of each general-purpose register set of the second general-purpose register set means; Data is read from the corresponding area of the first general-purpose register setting means, and the read data is transferred to each general-purpose register set of the second general-purpose register setting means, bypassing other logic circuits in the logical division. and a control means.

[Industrial application field]

The present invention relates to a configuration of a central processing unit of an information processing device,
More specifically, the present invention relates to a general-purpose register switching method instructed by a machine instruction.

In central processing units such as general-purpose computers and minicomputers, the OP code of the instruction set in the instruction register is decoded by the instruction decoder section, and ALU (Ar
ithmetic Logic Unit),
It controls the source and destination of operands input to the ALU and the functions of the ALU. AL
The operand given to U is stored in a general-purpose register,
Addresses that refer to general-purpose registers are mainly specified by register specifications in the address section of the instruction register. A high-performance general-purpose computer has a plurality of general-purpose registers, and tasks can be switched at high speed by switching the general-purpose registers that can be specified by machine instructions depending on the mode. Furthermore, generally, a logical address set in the address field of an instruction is converted to an absolute address for directly accessing the main memory. At this time, a register ALU (RALU) consisting of a general-purpose register and an adder for conversion is used. That is, this RALU for address calculation is prepared separately from the RALU for data calculation, and the next address is generated while performing calculations in the RALU for data calculation. In this way, general-purpose registers have come to be used for multiple purposes, and for this reason, multiple sets of general-purpose registers are prepared, and at certain times, the set of general-purpose registers that can be used by machine instructions is selected and used. At this time, which set is used is determined by specifying the mode. L with one CPU
If it cannot be configured with an SI but is configured with multiple LSIs, there is a problem of how to configure and use the general-purpose registers on each LSI, and this problem is generally a matter of cost performance. It is necessary to consider ways to improve the situation.

[Conventional technology]

FIG. 6 is a block diagram of a conventional CPU. CPU is LSI
It is composed of a plurality of chips such as I, LSI2, and LSI3, and reads out instructions and data from the memory 6 of the main storage device, processes them, and then stores the results in the same memory 6. In the figure, LSll is an instruction decoder and an instruction register 7.
and a decoder 8 for decoding instructions. LSI2 is a RALU for address calculation to convert a logical address to an absolute address. Inside it is general purpose register set 1
4, 15, an adder 4, and an output register 5. The LSI 3 is a RALU that handles numerical data and is composed of a general-purpose register set 13, a register 9, a register 10, an ALU II, and a register 12. The instruction read from the memory 6 is set in the instruction register 7, and the OP code of the set instruction is decoded by the decoder 8. The resulting decoded microinstruction determines the function of the ALUII and the selection of source operands input to the ALUII and the destination for the ALUII result. The operands input to ALUII are mainly read data from the general-purpose register set 13 or read data from the memory 6, and the results calculated by ALUII are sent to the general-purpose register set 13 via the register 12.
will be stored again. Alternatively, the output data set in the register 12 is transferred to the memory 6 and written therein. Alternatively, it is input to the LSI 2 for address calculation and set in the general-purpose register set 14 or the general-purpose register set 15. RALU of LST2 is general purpose register set 14
．． 15 is calculated by adder 4, and the output is set in register 5. The output of register 5 becomes the absolute address of memory IJ 6, which is the main memory.

In such a CPU configured with a plurality of LSIs, the functions of the CPU are assigned to the divided LSIs.

In this conventional method, the general-purpose register set 14 of LSI2
．． 15 and the general-purpose register set 13 of LSI3 are completely
Same structure, logically one thing can be used for multiple LS
It is assigned to each of I. That is, the general-purpose register cell (13.14.15) performs the same operation for any task and has the maximum number of registers.

Which register in the register set is to be used is specified by a register specifying section included in the address section of the instruction register 7. Therefore, the contents of the general-purpose registers 13, 14, and 15 always contain the same data, and the numerical data output from ALUII is also written to the general-purpose register sets 14 and 15 for address calculation. In addition, address data for address calculation is general-purpose register set 14 and 15.
In addition, it will also be written to the general-purpose register set 13.

FIG. 7 is a configuration diagram of a conventional general-purpose register set. In the figure, a total of n registers from 1 to n is the maximum number of registers that constitute the general-purpose registers, and in the case of general-purpose register sets 13, 14, and 15, all registers from register numbers 1 to n are included. have The general-purpose registers that can be specified by machine instructions are switched depending on the mode. In other words, all registers 1 in the CPU
The set of registers that can be specified by machine instructions among ~n is A,
The numbers are limited to C, B, or N, and which set from A to N is used can be switched depending on the mode. In this way, tasks are switched at high speed without being transferred to the main memory.

[Problem to be Solved by the Invention] Therefore, in this conventional method, the register area corresponding to task switching can be selected at high speed by simply changing the address information input to the general-purpose register set at the same time. It is necessary to install a general-purpose register consisting of the same register group and the maximum number of registers in the LSI, resulting in a problem that the amount of hardware increases. Therefore, in the past, in order to prevent an increase in the amount of hardware, L
The method used is to provide only the maximum number of registers that can be specified by machine instructions in each general-purpose register set on the SI, store the remaining registers in local memory or main memory, and replace them when changing modes. In some cases, a problem arises in that mode conversion becomes slow.

An object of the present invention is to minimize the hardware amount of a general-purpose register set and to change areas at high speed.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention.

The central processing unit decodes instructions read from the main memory 24, inputs data, performs operations, and then processes the data by setting it in a general-purpose register or transferring it to the main memory 24. First general-purpose register setting means 17
consists of multiple areas corresponding to multiple modes,
Each area has the maximum number of registers that can be specified by a machine instruction.

The second general-purpose register set means 19 is located in a logical division other than the logical division containing the first general-purpose register set means 17, and has an area equal to the number of registers in each area of the first general-purpose register set. Register numbers can be specified using machine instructions only. The register group selection register means 20 includes a first
Specify each area of the general-purpose register set and set the upper address bits corresponding to each mode. The instruction register 21 includes a machine instruction including a register designation signal that designates a register in each area of a first general-purpose register set and a register designation signal that designates all registers in each general-purpose register set of a second general-purpose register set group. can be set. When changing the mode, the control means 23 changes the contents of the register group selection register and sequentially reads data from the corresponding area of the first general-purpose register set from the first address to the last address of the area. It is possible to simultaneously transfer data from a first general purpose register set directly to each general purpose register set of a second general purpose register set, bypassing other logic circuits in the logical partition. The present invention is characterized in that data in general-purpose registers is transferred from a specific area of the first general-purpose register setting means 17 to all other second general-purpose register setting means 19 when switching modes.

[For production]

In the present invention, only one overall general-purpose register set is made up of the maximum number of register groups, and other machine instruction-specified general-purpose register sets are made up of only the maximum number of general-purpose registers that can be used by machine instructions. When the mode is switched by a machine instruction instruction or an operation such as an interrupt, data is transferred from a part of the overall general-purpose register set to the machine instruction-specified general-purpose register set at the time of mode conversion, thereby speeding up the general-purpose registers. Optimize capacity.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the configuration of the present invention.

In this figure, the same parts as in Figure 1 are indicated by the same symbols, and 2
1 is an instruction register included in the LSI, and the OP code and 3
It consists of two register specifying sections R1, R2°R3.

LSI 18 is an address calculation section, and LS 116 is a RALU section of a numerical calculation section. In LS116, 2
6 is ALU, 17 is general purpose register set, 27,2
9, 30° 31 is a register, 28 is an incrementer, 2
5.32 is a multiplexer, and 20 is a register group selection register.

On the other hand, LSI 1 B has a RALU for address calculation.
19A and 19B are machine instruction specification general-purpose register sets, 33 is an adder, 34 and 35 are registers, and 36
and 37 are incrementers, and 38 and 39 are multiplexers. The overall general-purpose register cell (SER) 17 in the LSI 16, which is a RALU for numerical calculations, includes all the register groups necessary for the task, and is composed of the maximum number of registers.

FIG. 3 is a configuration diagram of the overall general-purpose register set.

For example, the registers consist of a maximum of 32 register groups from 0 to 31, and the area is A depending on the mode.
, B, C, and D. A, B, C.

The upper bits of the address specifying the four areas of D are set by the register group selection register 20 at the time of mode switching. The designation of the eight registers in each area is specified by the 3 bits of R1 in the address field of the instruction register 21, and the control of reading or writing to the eight consecutive registers is performed by an address curance consisting of the register 27 and the incrementer 2. , carried out by the Ri Department. The contents read from the overall general purpose register set 17 are stored in the register 29.
is set to ALU 26 as the first operand. Further, data read from the main memory 24 is set in the input register 30 and given to the ALU 26 as a second operand. The result of ALU 26 is set in output register 31. The multiplexer 25 is capable of selecting this output 39 and the output 40 read from the overall general purpose register set 17. The selected result 41 is machine instruction specification general-purpose register set 1
9A or 19B, or to any register in the overall general purpose register set 17. The modes differ depending on the task or the interrupt level, and the areas A, B, C, and D corresponding to each mode are specified by the 2-bit upper address set in the register group selection register 20. Also, the eight registers in each area are designated by the lower three bits. For example,
Either 1 depending on the 3 bits of R1 of the instruction register 21.
one register is specified.

On the other hand, in the RALU for address calculation of LSllB, the machine instruction specification general-purpose register sets 19A, 19B and the register group selection register 20 have a smaller capacity than the overall general-purpose register set 17, and the eight registers specified in the mode Contains only Therefore, R2 and R3 of the instruction register 21 are 3 bits, and R2
The three bits of R3 specify the address of the machine instruction specification general-purpose register set 19A, and the three bits of R3 specify the address of the machine instruction specification general-purpose register set 19B. In other words, if the machine instruction is a register transfer instruction, it consists of an operation code OP and a register specification part, and R1, R2, and R3 of the register specification part each consist of 3 bits, and both correspond to each mode after mode switching. 8 registers can be specified.

When a machine instruction is executed, each 3 bits of the register designation parts R2 and R3 set in the instruction register 21 designate the address of the machine command designation general-purpose registers 19A and 19B, and the read address data is sent to the adder 33. It is added and set in the address register 42. Since this is an absolute address, the main memory 24 is accessed, and if the read content is data, it is set in the data register 30.

On the other hand, the 3 bits of machine instruction R1 are sent to multiplexer 3.
2 becomes the lower address bit of the overall general purpose register set 17. The upper address bits are determined by the value of the register group selection register 20, and one of the area groups A to D corresponding to the mode specification is selected. 0 The register specified by R1 in the selected area is selected. The contents are read from the overall general purpose register set 17 and set in the register 29. Then data register 29
and 30 are calculated by the ALU 26 and set in the output data register 31. Output data register 3
Depending on the type of machine instruction OP code, the value 1 is either returned to the general purpose register set 17 via the multiplexer 25, stored in the main memory 24, or stored in the machine instruction designated general purpose register sets 19A, 19B. It is determined whether the input is made. The value of the data register 31 is the general general purpose register set 17. When transferred to the machine instruction specified general-purpose register sets 19A and 19B, the overall general-purpose register set 17. The write enable for the machine instruction designated general-purpose registers 19A and 19B is in the on state. In the process of executing this operation for a specific mode, any one of areas A, B, C, and D of the overall general-purpose register set 17 is used.

When changing the general-purpose register group to be designated with a mode change, it is necessary to change the mode designation signal of the register group selection register 20. In this case, areas A, B, and C are changed using the l/register group change command.

Alternatively, the upper bit of the address corresponding to D is set in the register group selection register 20. If the mode is changed,
It is necessary to set the contents of the general-purpose registers corresponding to the modes necessary for address calculation in the machine instruction specification general-purpose registers 19A and 19F3. That is, since the requested contents are only in the area corresponding to the mode of the overall general-purpose register set 17, it is necessary to read the contents and transfer them to the machine instruction specification general-purpose registers 19A and 19B when changing the mode. The route for this transfer is the signal line 40, and the output contents of the overall general-purpose register set 17 are selected by the multiplexer 25 at the time of this mode change.

That is, when the mode is changed, all the contents of the register group in the area corresponding to the mode are transferred to the machine instruction designated general-purpose registers 19A and 19B via the signal line 40. This transfer sequentially specifies eight registers within the area. An address counter that sequentially reads eight registers from 0th to 7th in an area corresponding to a mode is composed of an incrementer 28 and a register 27. That is, the contents read from the register 27 are incremented by 1 by the incrementer 28 and set in the register 27 again, so the incrementer 28 and the register 27 function as an address counter. The output of this address counter is applied to the three bits of the lower address of the overall general purpose register set 17 via the multiplexer 32. The sequentially read contents are stored in machine instruction designated general purpose registers 19A and 19B via signal lines 40, 41. The write address at that time needs to be incremented as well. The address counters for this are incrementers 36.37 and registers 34.35. register 27
．． 34 and 35 are set to 0 immediately after mode conversion, and multiplexers 32, 38 and 39 select the outputs of registers 27, 34 and 35, respectively. And by counting up each address counter,
The contents of eight registers in the area corresponding to the specified mode are read out in order from the overall general-purpose register set 17, and are read out from the general-purpose register set 17 for machine instruction specification.
are written respectively.

That is, the contents of the area of the comprehensive general-purpose register set 17 specified by the register 27 are read out, and the signal lines 40 and 41 are read out.
is written to the address specified by register 34 of register 19A, and simultaneously written to register 35 of machine instruction specified general-purpose register 19B.
is set to the address specified by . Next, the contents of the register 27 are incremented by 1 via the incrementer 28, and at the same time, the contents of the register 34 are incremented by 1 by the incrementer 36, and the contents of the register 35 are incremented by the incrementer 3.
+1 by 7. Then, the value of the overall general-purpose register set 17 is read out again and transferred to the machine instruction designated general-purpose register set 19A and 19B. By repeating this eight times, the values of the eight registers of the newly designated register group of the general purpose register set 17 are written into the machine instruction designated general purpose register sets 19A and 19B. This transfer is a register-to-register transfer between general-purpose registers, so it is very fast. Moreover, the machine instruction specification general-purpose registers 19A and 19B only have the size of 174 of the overall general-purpose register set 17, and the amount of hardware becomes extremely small.

That is, in the present invention, the overall general-purpose register set 17 has the maximum value of all register groups necessary to execute all tasks, that is, it holds register groups used by multiple tasks managed simultaneously. be. That is, the overall general-purpose register set 17 does not hold only the general-purpose registers used in the task, but also holds those that the machine instruction specified general-purpose register sets 19A and 19B use in one task. On the other hand, the machine instruction specified general-purpose register sets 19A and 19B are small-capacity memories corresponding to the bits specified by each register in the address part of the machine instruction, and must consist of only the maximum number of general-purpose registers that can be specified by the machine instruction. becomes possible. In other words, in the present invention, the address part of the instruction register can be configured with a very small number of bits, and it can be configured with a general-purpose register that can switch quickly in response to various task changes, requires a small amount of hardware, and has extremely high cost performance. be done.

FIG. 4 is a time chart showing the operation when rewriting the contents of a general-purpose register according to the present invention. FIG. 5 is an embodiment diagram showing the contents of each general-purpose register set corresponding to the operation when rewriting the contents of the general-purpose registers.

In FIG. 5, the overall general-purpose register set 17 is 0 to 3.
There are a total of 32 registers at address 1, and machine instruction specification register sets 19A and 19B are composed of 8 registers. The upper part of Figure 5 shows the contents of each general-purpose register set when the register group selection register group 20 includes bits corresponding to area A, and the lower part shows the contents of each general-purpose register set when the register group selection register group 20 includes bits corresponding to area B. It shows the contents of each general-purpose register set in certain cases. As shown in FIG. 3, each area of the overall general-purpose register set 17 is area A from 0 to 7, area B from 8 to 15, and area B from 8 to 15.
The 23rd address from the address C124 and the 31st address correspond to the area. When the register group selection register 20 is A, the register set is read from the eight register groups from address 0 to address 7, and the contents are transferred to the machine instruction general-purpose register sets 19A and 19B.
In this state, machine instruction specification general-purpose register set 19A
, 19B stores the contents of addresses 0 to 7 corresponding to area A.

Now, the mode changes from this state, and the contents of the register group selection register 20 point to area B in accordance with the mode. At this time, in the present invention, area B of the overall general-purpose register set 17, that is, each register from address 8 to address 15, is assigned to the machine instruction designated general-purpose register set 1.
Transferred to 9A and 19B. That is, the contents of the register group selection register 20 point to the start address of area B,
The contents of addresses 8 to 15 in area B are sequentially transferred to machine command specified general-purpose register set 1 by address count.
It will be transferred to 9A and 19B.

In the time chart of FIG. 4, clock cycles from 1 to 10 are shown, and there is a mode change in the clock cycles from ■ to ■, indicating that the contents of the register group selection register 20 change from A to B. Therefore, in clock period ■, the contents of the register group selection register 20 are A.
The contents of the overall general-purpose register set 17 are specified from addresses 0 to 7. Similarly, the same contents are machine instruction specification general-purpose register sets 19A and 19B.
is stored in. From this state, the clock cycle
, the contents of register group selection register 20 change to B, and at the same time register 2, which is a counter register, changes to B.
7, 34. The contents of 35 become 0. Since the register group selection register 20 points to B and the contents of the register 27 is O, the read data of the overall general-purpose register set 17 is the contents of B specified by the register group selection register 20, that is, the contents of address 8. become. The contents of the read address 8 are input as registered data to the machine instruction designation general-purpose register sets 19A and 19B via the signal lines 40 and 41 at the same clock cycle (3). Also in the machine instruction designation general-purpose register sets 19A and 19B, the write enable signal becomes enabled, ie, at a low level, at the end of the clock cycle. As a result, the read data at address 8 is written to address 0 of the machine instruction designated general-purpose register set 19A, 19B. Then, when the clock cycle (2) begins, the register 27 is incremented by 1 by the incrementer 28, and the read data of the overall general-purpose register cell 1-17 is counted up to become the contents of address 9. The contents of this address 9 are given to machine instruction specification general-purpose register sets 19A and 19B. At this time, registers 34 and 35 have been incremented by incrementers 36 and 37, so the contents of address 9 are stored in address 1 of both registers. The rest is the same operation, and at clock cycle ■, register 27 becomes 2,
The read data of the overall general-purpose register set 17 becomes the contents of address 10, and the machine instruction specified general-purpose register set 1
It is written to 2 addresses 9A and 19B. In the clock cycle ■, area B 3 of the overall general-purpose register set 17
The contents of the 11th address, that is, the 11th address, are written to the 3rd address of the machine instruction designation general-purpose registers 19A and 19B.

In the clock cycle ■, 12 of general-purpose register set 17
The contents of the address are machine instruction specification general-purpose registers 19A and 1.
In clock cycle ■, the contents of address 13 of general-purpose register set 17 are written to address 5 of general-purpose register set 17 (machine instruction specified general-purpose register set) 19A and 19B, and in clock cycle ■, the contents of general-purpose register set 17 are written to address 5 of general-purpose register set 17. The contents of address 14 of set 17 are written to address 6 of machine instruction specified general purpose register sets 19A and 19B. And finally, general general purpose register set 17-1
The contents of address 5 is a machine instruction specified general-purpose register cella) 19
The contents of address 7 of A and 19B are written. Therefore, when changing from mode A to mode B, the values of the registers with the general register numbers designated in mode B in the overall general register set 17 are sequentially written to the machine instruction designated general register sets 19A and 19B through the multiplexer 25.

〔Effect of the invention〕

In the present invention, one of the general-purpose register sets divided into multiple LSIs includes the maximum number of registers for all tasks, and the other general-purpose register set has only the maximum number of general-purpose registers that can be specified by machine instructions. It turns out. Therefore, with the present invention, it is possible to reduce the capacity of the general-purpose register set, and when changing modes, the contents of the general-purpose register set are copied at high speed by transferring only between registers, so it is possible to achieve highly effective use of general-purpose registers. Therefore, the register designation part of the instruction can be configured with fewer bits, and the general-purpose registers can be optimized for task switching.

FIG. 6 is a block diagram of a conventional CPU, and FIG. 7 is a block diagram of a conventional general-purpose register set.

16° l　7　・ 19・ 20・ 21・ 23・ 24・ ...logical division, first general-purpose register setting means; second general purpose register set group means; register group selection register, instruction register, control means, Main memory.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of the present invention, Figure 2 is an embodiment of the configuration of the present invention, Figure 3 is a configuration diagram of a comprehensive general-purpose register set, and Figure 4 is a diagram showing the configuration of the general-purpose register of the present invention. A time chart showing the operation, Figure 5 shows the reverse method used when rewriting the contents of a general-purpose register. Jizutahinoto, F4/3. Figure 7
figure

Claims (1)

[Scope of Claims] 1) After decoding an instruction read from the main memory (24), inputting data, and performing an operation, processing is performed by setting it in a general-purpose register or transferring it to the main memory (24). A central processing unit comprising a plurality of areas corresponding to a plurality of modes, each area having a register that can be specified by a machine instruction.
and a general-purpose register setting means (17) in a logical division (18) other than the logical division (16) including the first general-purpose register setting means (17), and the first general-purpose register setting means (17) a second general-purpose register set means (19) having an area corresponding to the number of registers in each area, and capable of specifying each register with a machine instruction;
and register group selection register means (20) for specifying each area of the first general-purpose register setting means (17) and setting upper address bits corresponding to each mode; and the first general-purpose register setting means (17). instruction register means (17) capable of setting a machine instruction including a register designation signal designating a register in each area and a register designation signal designating a register in each general-purpose register set of the second general-purpose register setting means (19); 21) At the time of mode change, the contents of the register group selection register means (20) are changed, data is read from the corresponding area of the first general-purpose register set means (17), and the read data is Said logical division (16)
and control means (23) for bypassing other logic circuits (22) in the general-purpose register setting means (22) and transferring data to each general-purpose register set of the second general-purpose register setting means (19). 2) The control means (23) is located in the address section of the first general-purpose register setting means (17), and includes an address counter that sequentially specifies registers in each area, and each of the second general-purpose register setting means ( 19) and each second general-purpose register set means (19).
), which selects the read data of the first general-purpose register set means (17) and transfers the selected read data to the second general-purpose register set means (17);
2. The general-purpose register switching system according to claim 1, further comprising selection means for transferring the data to the general-purpose register setting means (19) of the general-purpose register setting means (19). 3) The general-purpose register switching system according to claim 1, wherein the first general-purpose register setting means (17) and the second general-purpose register setting means (19) are located on different chips. 4) The first general-purpose register setting means (17) mainly stores numerical or logical data and address information, and the second general-purpose register setting means (19) stores the first general-purpose register setting means (17). 2. The general-purpose register switching system according to claim 1, wherein the general-purpose register switching system has a smaller capacity and mainly stores address information of the main memory (24).