JPH07110769A - Vliw type computer - Google Patents

Abstract

PURPOSE:To provide a high-grade parallel computation function by the hardware of a small scale. CONSTITUTION:An instruction stored in an instruction register 1 is a normal single operational instruction. Then, the form of the instruction for starting a VLIW type operation which is the same form as the normal instruction is defined corresponding to a VLIW type instruction. When the instruction of the form is read from the instruction register 1, a decoder 2 parallelly operates respective computing elements 5 through an instruction buffer 4 by an instruction buffer control part 3. That is, the instruction buffer control part 3 discriminates whether or not the VLIW type instruction is stored in the instruction butter 4 by a number or the like corresponding to the kind of the VLIW type instruction and operates the respective computing elements 5 corresponding to the VLIW type instruction when the VLIW type instruction is stored. On the other hand, when the VLIW type instruction is not stored in the instruction buffer 4, the instruction read as the string of the normal instruction from a prescribed storage area is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VLIW type computer for controlling a plurality of functional units in a long instruction format.

[0002]

2. Description of the Related Art Generally, a parallel computer has a plurality of function execution units and operates them in parallel at the same time to perform high-speed processing. A VLIW computer is one of such parallel computers. With the VLIW calculator,
A relatively long instruction can be divided into many fields, and each field can independently control many arithmetic units, registers, interconnection networks, memories, etc. (Shinji Tomita, "Parallel Computer Architecture, pages 131-133"). Shokodo (1986), John
L. Hennesy and David A. Patterson Translated by Shinji Tomita, Kazuaki Murakami, Haruo Shinzo "Computer Architecture 316-323" Nikkei BP (1992)). Figure 2
FIG. 6 is a block diagram showing an example of the configuration of a conventional VLIW type computer. The illustrated computer comprises a plurality of arithmetic units 21, an instruction register 22, a register file 23 and the like.

The arithmetic unit 21 is a unit for adding various operations such as addition and subtraction to the data stored in the register file 23, and is composed of n units of the same or different structure. These arithmetic units 21 are generally a combination of a fixed point arithmetic unit, a floating point arithmetic unit, a memory access unit, a sequence control unit and the like. The instruction register 22 stores instructions in the format shown in the figure. This command consists of a plurality of fields F0, F1, etc.
1 and the like are composed of fields corresponding to the respective arithmetic units A0 and A1 and other control fields G for performing overall control. The fields F0, F1, etc. corresponding to the arithmetic units A0, A1 etc. control the arithmetic units A0, A1 etc. and specify the registers in the register file 23 for the arithmetic units A0, A1 etc.

The register file 23 is composed of a plurality of registers. These plural registers include a mutual connection network of the arithmetic units 21. The registers that are input sources or output destinations of the arithmetic units 21 and the arithmetic units 21 themselves or each arithmetic unit 21 and each register are connected by this mutual connection network. When a computer having such a configuration is used, the maximum parallelism can be obtained with a simple hardware configuration by detecting the parallelism in the program and filling each field of the instruction. Further, since the parallelism is statically detected, the hardware for detecting the possibility of parallel operation at the time of execution is unnecessary. Therefore, it is possible to configure a high-speed and flexible computer with small-scale hardware.

[0005]

However, the above-mentioned conventional technique has the following problems. (1) Problem of instruction length The VLIW type computer has a relatively long instruction length due to the characteristics described above. Further, since a high speed operation is required, it is necessary to supply one instruction in one machine cycle. Therefore, an instruction buffer having the same width as the instruction length and an instruction bus are required. (2) Code size problem To increase the degree of parallelism, the loop part of the program must be expanded. Therefore, increasing the parallelism is a factor of increasing the code size. Further, when the multiplicity of the arithmetic unit is higher than the parallelism inherent in the program, the instruction field is not completely filled, and the unused instruction field (NOP) increases the code size.

(3) The problem of the number of register ports Since all arithmetic units are connected to any register and any register can be used at the same time,
Each register requires a number of ports proportional to the number of arithmetic units. The present invention has been made focusing on the above points,
It is an object of the present invention to provide a VLIW type computer capable of realizing an advanced parallel computing function with a small-scale hardware.

[0007]

A VLIW type computer of the present invention includes an instruction register for storing a VLIW type instruction in the same format as an ordinary instruction, and an instruction read from the instruction register is a VLIW type instruction or an ordinary instruction. A decoder that determines whether the instruction is an instruction, an instruction buffer that stores the VLIW type instruction in the form of a VLIW type instruction, and the instruction read by the decoder from the instruction register is a VLIW type instruction. It is determined whether or not the VLIW type instruction is stored in the instruction buffer, and when the VLIW type instruction is stored, an instruction buffer control unit that reads the VLIW type instruction from the instruction buffer and performs parallel processing. It is characterized by having.

[0008]

In the VLIW type computer of the present invention, the instruction stored in the instruction register is a normal single operation instruction.
Then, corresponding to the VLIW type instruction, the format of the instruction for starting the VLIW type operation is defined in the same format as the normal instruction.
When the decoder reads an instruction of this format from the instruction register, the instruction buffer control unit causes the arithmetic units to operate in parallel via the instruction buffer. That is, the instruction buffer control unit determines whether or not the VLIW type instruction in the format of the VLIW type instruction corresponding to the instruction buffer is stored by the number according to the type of the VLIW type instruction, and the VLIW type instruction is stored. If so, the arithmetic unit is operated according to the VLIW type instruction. On the other hand, if the VLIW type instruction is not stored in the instruction buffer, the VLIW type instruction is executed as a sequence of normal instructions from the predetermined storage area, and the VL is stored in the instruction buffer.
A VLIW type instruction in the form of an IW type instruction is stored. As a result, when the same instruction for starting the same VLIW type operation is read from the instruction register, the VLIW type instruction stored in the instruction buffer is read, and the respective arithmetic units are operated in parallel.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a VLIW type computer of the present invention. The illustrated computer comprises an instruction register 1, a decoder 2, an instruction buffer control unit 3, an instruction buffer 4, a plurality of arithmetic units 5, a general-purpose register file 6, a parallel processing register file 7, and the like. Instruction register 1
Is a register for storing an instruction fetched from an instruction memory (not shown). The instruction register 1 is connected to the decoder 2. The instruction fetched into the instruction register 1 is not a VLIW type instruction for performing parallel execution but an instruction used for executing a normal single instruction, and generally has a 32-bit length or a 16-bit length. It is an instruction. The decoder 2 decodes the instruction of the instruction register 1 and outputs the control signal of each arithmetic unit 5. That is, the decoder 2 determines whether the instruction is an addition instruction, a subtraction instruction, a load instruction, or the like based on the OP code, and outputs a control signal to the corresponding arithmetic unit 5.

The instruction buffer control unit 3 includes an instruction buffer 4
To control the contents stored in and the execution of the instructions in the instruction buffer 4. The instruction buffer 4 is VL
The IW type instruction is stored, and each arithmetic unit 5 is controlled by each field of the instruction. The arithmetic unit 5 is n arithmetic units including various operations such as addition, subtraction, multiplication and division, logical operations, etc., memory control such as load and store, sequence control such as branching, and the like. The general-purpose register file 6 is VLIW
It is a register used in normal instructions other than type instructions.
The parallel processing register file 7 is a register used when executing a VLIW type instruction.

FIG. 3 shows an example of the format of the instruction for starting the VLIW type operation. The VLIWOP field indicates that this instruction is an instruction to start a VLIW type operation.
The NO field is a field for designating the order of the VLIW type operation to be executed. The DST field is a field that indicates the number of the register that stores the value when the result value of the VLIW type operation needs to be returned. The SRC1 and SRC2 fields are fields indicating the number of a register that stores parameters necessary for performing the VLIW type operation. By such a VLIW type instruction, the data stored in the registers of the numbers designated in the SRC1 and SRC2 fields is subjected to the operation of the VLIW type instruction, and the result is stored in the register designated in the DST field.

FIG. 4 is a block diagram showing a detailed structure of the instruction buffer control unit 3. As illustrated, the instruction buffer control unit 3 includes an instruction format conversion unit 41, an instruction buffer address table 42, an instruction buffer address counter 4
3, VLIW type instruction sequence control unit 44. The instruction format conversion unit 41 converts the single operation type instruction fetched into the instruction register 1 so as to form one field of the VLIW type instruction. As a result, the formed VL
The IW type instruction is stored in the instruction buffer 4. The instruction buffer address table 42 stores the VL in the instruction buffer 4.
4 is a table showing the start address of an IW type instruction and the validity of that instruction. Each entry in this table is a VLIW
A field for storing the number of the type instruction, a start address of the VLIW operation in the instruction buffer 4 designated by the number, and a V (Valid) bit indicating whether or not the start address is valid.

The instruction buffer address counter 43 counts the address of the instruction buffer 4 when storing a single operation instruction in the instruction buffer 4. The instruction buffer address counter 43 always holds the address of the instruction buffer 4 to be written next, and sends the start address of the VLIW type instruction to the instruction buffer address table 42. The VLIW instruction sequence control unit 44 stores the instruction converted by the instruction format conversion unit 41 in the instruction buffer 4 and controls the sequence of the VLIW instruction stored in the instruction buffer 4.

Next, the operation of the computer configured as described above will be described. In FIG. 1, first, the instruction fetched from the instruction bus is stored in the instruction register 1. The instruction stored in the instruction register 1 is decoded by the decoder 2. As a result, the arithmetic unit 5 is designated and the general-purpose register file 6 is designated. Further, the decoder 2 determines whether the instruction decoded by the OP code is a normal instruction designating a single operation. In the case of a normal instruction, one of the arithmetic units 5 is designated, and at that time, one or two registers in the general-purpose register file 6 are designated.

On the other hand, when the instruction decoded by the decoder 2 is the VLIW type instruction shown in FIG. 3, the instruction buffer control unit 3 checks the content of the instruction buffer address table 42 by the content of the No field in the instruction.
FIG. 5 shows the operation of the instruction buffer controller. N in the order
If the V bit of the entry having the value of the o field is set, the target V is already stored in the instruction buffer 4.
This indicates that there is a LIW type instruction sequence (step S1). Therefore, control is immediately transferred to the instruction string in the instruction buffer 4 (step S2). The start address of the instruction buffer 4 in this case is the address stored in the buffer address field of the corresponding entry of the instruction buffer address table.

When executing this instruction, first, the contents of the register numbers indicated by the SRC1 and SRC2 fields in the VLIW type operation start instruction are read from the general-purpose register file 6. Then, it is stored in the register having the same number in the parallel processing register file 7. After that, one VLIW type instruction stored in the instruction buffer 4 is executed every one cycle. Then, according to the SEQ field in the instruction, the VLIW type instruction sequence control unit 44 sequentially outputs the address of the instruction buffer 4, and the instruction of that address is executed. The SEQ field in the command is VLIW
If it indicates the end of the type instruction, the VLIW type instruction ends,
Execution of the next single operation type normal instruction fetched in the instruction register 1 is started. At this time, the contents of the register designated by the DST field in the VLIW type operation start instruction are copied from the parallel processing register file 7 to the register having the same number in the general-purpose register file 6. After that, the execution of the normal instruction is repeated until the VLIW type instruction is fetched again.

If the V bit of the corresponding entry in the instruction buffer 4 is reset, it means that no VLIW type instruction is stored in the instruction buffer (step S1). In this case, a trap is generated, and the trap routine starting from the address designated by the trap instruction is fetched (step S3). This trap routine is stored in advance at that address in the main memory as shown in FIG. These trap routines are prepared only for the type of VLIW type instruction to be used. The trap routine is composed of an instruction sequence of the same format as a normal instruction, and is described in order from the instruction corresponding to the OP1 field so that each field of the instruction buffer 4 can be sequentially filled. When the corresponding field is not filled, it is necessary to insert the NOP instruction. This is VLIW
Repeat for the number of type commands. Therefore, the trap routine needs (VLIW type instruction field number) × (VLIW type instruction number) normal instructions.

The single instruction described in the trap routine is fetched into the instruction register 1 (step S4),
It is executed (step S5). The instruction format conversion unit 41 converts the VLIW-type instruction so as to match each field (step S6) and stores it in the instruction buffer 4 (step S7). The start address of the instruction buffer 4 to be stored is held by the instruction buffer address counter 43, and when the VLIW type operation start instruction is detected and is not registered in the instruction buffer address table 42, the instruction buffer address counter 43 is stored. The address held by is written in the buffer address field of the entry of the corresponding number No in the instruction buffer address table 42, and is sequentially written in the field of the instruction buffer address indicated by this address. The return instruction in the trap routine is converted by the instruction format conversion unit 41 into a code indicating the end of the VLIW type operation, and S in the instruction buffer 4 is converted.
It is stored in the EQ field. The single operation instruction in these trap routines is thus written and executed in the instruction buffer 4.

FIG. 7 is an explanatory diagram of the operation when the single operation instruction is executed. The temporary data storage register 51 is a VLIW
When the type instructions are executed as a series of normal instructions, the consistency of the registers is ensured as compared with the case of parallel operation in the VLIW type. Therefore, writing to the parallel processing register file 7 is temporarily suspended until one VLIW type instruction is completed, and writing is collectively performed when one VLIW type instruction is completed. . This temporary data storage register 51 is
It is used only when a W-type instruction is executed as a sequence of normal instructions, and depending on the contents of the instruction buffer 4, when performing a VLIW-type operation, writing is directly performed to the parallel processing register file 7.

As described above, the instruction stored in the instruction register 1 can be in the normal instruction format, the instruction length does not increase, and the number of signal lines of the instruction bus can be reduced. . In addition, since the code size is determined by the size of a normal instruction, the unused instruction field does not increase even in a program that rarely uses VLIW type instructions. In the embodiment described above, the VLI read from the predetermined storage area of the main storage device is used.
Although the W-type instructions are stored in the instruction buffer 4, the present invention is not limited to this, and also includes those in which the VLIW-type instructions of all combinations are stored in advance in the instruction buffer 4.

[0021]

As described above, the VLIW of the present invention is
According to the type computer, since the instruction buffer for storing the VLIW type instruction and the instruction buffer control unit for controlling the instruction buffer by the external instruction are provided, the following effects can be obtained. That is, since it becomes necessary to use the VLIW type instruction only in a portion having a high degree of parallelism and high speed, it is possible to reduce the overall code size, and it is not necessary to increase the instruction memory capacity. , It is possible to avoid having to take a large instruction length. Therefore, the width of the instruction bus can be reduced, and the overall hardware can be downsized. Further, the VLIW type operation start instruction can be obtained by expanding a normal instruction, and
By creating a VLIW type instruction from a normal instruction sequence, it can be configured to maintain upward compatibility with the instruction set architecture of an existing computer. Data processing can be parallelized using conventional software, It is possible to increase the speed. Further, the instruction buffer and the instruction buffer control unit as described above are provided, and the register file used for the execution of VLIW type instructions and the register used for the execution of ordinary instructions with low parallelism are separated and switched according to the type of the instruction. It is possible to optimally adjust the capacity of the multiport register file necessary for the VLIW operation. Therefore, it is possible to optimize the hardware according to the application and reduce the number of ports.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a VLIW type computer of the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional VLIW type computer.

FIG. 3 is an explanatory diagram of a format of an instruction to start a VLIW type operation.

FIG. 4 is a block diagram showing a detailed configuration of an instruction buffer control unit in FIG.

FIG. 5 is a flowchart illustrating an operation of an instruction buffer control unit.

FIG. 6 is an explanatory diagram of contents of a predetermined area of the main storage device.

FIG. 7 is an explanatory diagram of the operation of the register file of FIG.

[Explanation of symbols]

 1 instruction register 2 decoder 3 instruction buffer control unit 4 instruction buffer 5 arithmetic unit 6 general purpose register file 7 parallel processing register file

Claims (4)

[Claims] 1. An instruction register that stores a VLIW type instruction in the same format as a normal instruction, a decoder that determines whether the instruction read from the instruction register is a VLIW type instruction or a normal instruction, and the VLIW type instruction. In the form of a VLIW type instruction, and if the instruction read from the instruction register by the decoder is a VLIW type instruction, is the VLIW type instruction stored in the instruction buffer? A VLIW type computer comprising: an instruction buffer control unit for determining whether or not the VLIW type instruction is stored and reading the VLIW type instruction from the instruction buffer for parallel processing. 2. The instruction buffer control unit, when the VLIW type instruction read from the instruction register is not stored in the instruction buffer in the VLIW type instruction format,
2. The VLIW type instruction converted into the VLIW type instruction format is stored in the instruction buffer while sequentially executing the instructions read out as a sequence of normal instructions from a predetermined storage area. VLIW type calculator. 3. A parallel processing register file used when executing the VLIW type instruction and a general-purpose register file used when executing the normal instruction are separately provided, and the instruction buffer control unit is discriminated by the decoder. 3. The VLIW computer according to claim 1, wherein the parallel processing register file and the general-purpose register file are switched and used according to the type of the issued instruction. 4. When the VLIW type instruction is executed as a sequence of normal instructions, a temporary data storage register for sequentially storing the execution result is provided, and after all the normal instructions corresponding to the VLIW type instruction are executed, 4. The VLIW type computer according to claim 3, wherein the data stored in the temporary data storage register is transferred to the parallel processing register file.