JP2812610B2 - Pipeline control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline control system in an information processing apparatus, and more particularly, to high-speed pipeline processing by changing the number of cycles of an operation execution state of an instruction input to a pipeline. The present invention relates to a pipeline control method that can be realized with a universal configuration and realized with a small microprogram capacity when adopting a configuration for executing.

[0002] The pipeline processing is a processing method in which one instruction processing is divided into a plurality of processings and a plurality of instruction processings are executed in parallel. FIG. 7 shows an example of pipeline processing composed of six stages. The multiple divided processes are:
Each is distinguished by the name state.

In the example of FIG. 7, pipeline processing is performed by sequentially passing through each of the D state, A state, T state, B state, E state, and W state. In this D state, instruction decoding,
In the A state, an address is calculated, in the T state, a TLB index is read, in the B state, a cache is read, in the E state, an operation is executed, and in the W state, the operation result is stored in a register. Here, the same state is not set between a plurality of instruction processes. Also, the time during which one state is processed is called one machine cycle. If pipeline processing operates ideally, N instructions appear to end in N machine cycles.

In such pipeline processing, it is necessary to construct a configuration that can execute instructions as fast as possible.

[0005]

2. Description of the Related Art In an information processing apparatus for performing pipeline processing, there is a pipeline interlock as a factor that hinders an ideal operation of the pipeline processing. A typical example is an E-state interlock for preventing an operation from being completed in one cycle. For example, in the processing of a floating-point instruction, since the operation of the E cycle does not end in one cycle, the instruction may not be processed every cycle as shown in FIG. In the example of FIG. 8, the start of the sixth instruction is delayed by one cycle as compared with FIG.

Therefore, in an information processing apparatus that requires high speed, in order to solve such inconvenience, the instruction execution for each cycle is performed by forming the operation execution state in a pipeline configuration with a plurality of stages. Has been realized. That is, for example, as shown in FIG. 9, by adopting a configuration in which the operation execution state is further divided into an E state and a V state, pipeline processing for each cycle is realized.

However, even in such a technique, a loss time occurs when an instruction with a V state and an instruction without a V state are executed successively. FIG. 10 illustrates this example. Here, the instruction 1 is an instruction with a V state, and the instruction 2 is an instruction without a V state.

In such a case, in order to reduce the loss time, it is conceivable to adopt a configuration in which an instruction without V state immediately after an instruction with V state is executed as an instruction with V state. When this configuration is adopted, FIG.
In the case of the pipeline processing of 0 as an example, by executing instruction 2 as an instruction with a V state, an ideal pipeline operation as shown in FIG. 9 can be performed. .

Japanese Patent Application Laid-Open No. 2-69825 discloses an invention suggesting this configuration. That is, in the present invention,
It discloses that an instruction without a V-state immediately after an instruction with a V-state is executed as an instruction with a V-state by adopting a configuration in which data in a memory is passed through an arithmetic unit through. According to the present invention, whether a V state is added or not is made variable, and when an instruction without a V state is executed before the instruction, the V state variable instruction is executed as an instruction without a V state. It is stated that the loss time can be reduced.

However, in the present invention, there is a disadvantage that only an instruction that passes through an arithmetic unit through data through, that is, an instruction that does not perform an operation, can perform such V-state variable control.

Meanwhile, the invention disclosed in JP-59-2 143 discloses is prepared a shift register that holds the operation result (not provided in the invention of JP-A-2-69825 JP), the largest It discloses that an instruction that can be executed in a smaller number of execution cycles than the number of operation pipeline cycles is executed in a larger number of operation pipeline cycles, thereby performing pipeline processing while observing the principle of sequential processing of instructions.

However, the present invention employs a configuration in which all the instructions for performing the arithmetic pipeline process perform the arithmetic process with the same number of execution cycles. Therefore, if an instruction that cannot be executed by the operation pipeline is executed immediately after an instruction that can be executed by the operation pipeline and that is executed by extending the number of execution cycles more than necessary, unnecessary interlock may be caused. There is.

That is, the operation can be executed in the shortest one cycle and the operation pipeline processing can be performed, and immediately after the instruction 1 which is always executed in two cycles,
When the instruction 2 that cannot be processed by the operation pipeline continues, as shown below, the instruction 2 is interlocked in the instruction 1 DAT BEV W instruction 2 D A T B B E W B cycle, and the operation start timing is changed. Will be delayed. The present invention shows that such a decrease in performance can be reduced by making the execution start cycle of the next instruction variable by providing a plurality of instruction end declaration means.

However, making the execution start cycle of the next instruction variable by providing a plurality of instruction end declaration means as described above complicates the control mechanism for determining the operation start timing of the instruction. Usually, the control mechanism for determining the operation start timing of an instruction is likely to include a complicated control circuit such as register interference detection, and there is a demand for simplification of the circuit as much as possible.

[0015]

Next, with reference to FIG. 11, a description will be given of a conventional technique used when delaying data using a shift register.

FIG. 11 shows a circuit configuration for executing an operation execution state. Reference numerals 60 and 61 denote input data registers; 62, an operation unit for performing an operation in one cycle;
Is an arithmetic unit that performs an operation in two cycles, 64 is an arithmetic unit that performs an operation in three cycles, 65 and 66 are delay registers, and 67 is an output data register. That is, in this example, it is assumed that the maximum number of cycles in the operation execution state of an instruction that may be input to the pipeline is three.

When adopting such a circuit configuration,
If the instruction to be input to the pipeline is an instruction that performs an operation in one cycle, and the instruction is executed in one cycle, the operation result data obtained by the arithmetic unit 62 is directly stored in the output data register 67. On the other hand, when this is executed in two cycles, the operation result data obtained by the operation unit 62 is delayed by one cycle in the delay register 65 and then set in the output data register 67. In the case of execution by using
First, the operation result data obtained in step 1 is delayed by one cycle in the delay register 65, and then another
This is performed by setting in the output data register 67 after delaying by the cycle.

Also, if the instruction input to the pipeline is 2
If the instruction is an instruction that performs an operation in two cycles, and if it is to be executed in two cycles, the operation result data obtained by the arithmetic unit 63 is directly set in the output data register 67, while this is set in three cycles. In the case of executing the calculation, the operation result data obtained by the operation unit 63 is stored in the delay register 6.
6 delays one cycle and then outputs data register 6
This is done by setting it to 7. If the instruction to be input to the pipeline is an instruction that performs an operation in three cycles, the operation result data obtained by the operation unit 64 is set directly in the output data register 67.

Processing for controlling when and to which register 65, 66 the data from each of the arithmetic units 62, 63, 64 is written can be performed by a microprogram. That is, by adopting a configuration in which a microprogram for executing a desired control process is read in accordance with the operation code of the instruction, the above-described delay operation can be realized in accordance with the microprogram.

However, when variable V cycle control is realized in accordance with such a microprogram, it is possible to perform the control with a simple hardware configuration, but there is a drawback that the capacity of the microprogram is increased. Occurs. For example, as described above, when the maximum number of operation execution states of an instruction that may be input to the pipeline is three, an instruction that can output an operation result in one cycle is one. It is necessary to prepare three types of microprograms that perform cycle, two-cycle, and three-cycle operations.

Considering that most commonly used general instructions are one-cycle and two-cycle instructions, such an increase in microprogram capacity cannot be avoided. From now on, if a configuration in which the shift operation of the operation result data is performed by a microprogram according to the related art is adopted,
As a practical means, the number of variable V-cycle instructions must be significantly limited.

The present invention has been made in view of such circumstances, and has a configuration in which pipeline processing is executed at high speed by changing the number of cycles of the operation execution state of an instruction to be input to a pipeline. It is an object of the present invention to provide a new pipeline control method which can be realized with a universal configuration and realized with a small microprogram capacity.

[0023]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 denotes an information processing apparatus, and reference numeral 2 denotes a pipeline processing execution unit of the information processing apparatus 1 according to the present invention. The pipeline processing execution means 2 executes an operation execution state including a plurality of machine cycles.

Reference numeral 3 denotes a detection means provided in the pipeline processing execution means 2, which is developed at a stage preceding the operation execution state and the number of cycles input to the pipeline is smaller than that of the instruction preceding the instruction. Detecting whether or not the operation execution state is to be ended, 4
Is a calculating means provided in the pipeline processing executing means 2, which is developed before the operation execution state and calculates a difference value between the two cycle numbers when the detecting means 3 detects a small number of cycles. Numeral 5 is a generating means provided in the pipeline processing executing means 2, which is developed before the operation execution state and generates a code signal corresponding to the difference cycle value calculated by the calculating means 4.

Reference numeral 6 denotes a control storage provided in the pipeline processing executing means 2, which manages a microprogram developed before the operation execution state and uniquely prepared for an operation code of an instruction. This microprogram is used as a control signal for controlling the register means 9 described later.

Reference numeral 7 denotes an operation execution unit provided in the pipeline processing execution unit 2 for executing an operation execution state including a plurality of machine cycles.
The arithmetic means comprises a number of arithmetic units corresponding to the number of operation execution states indicated by an instruction that may be input to the pipeline, and executes arithmetic processing.

Reference numeral 9 denotes register means provided in the operation execution means 7. If the maximum number of operation execution states of an instruction that may be input to the pipeline is represented by K cycles and the minimum number of cycles is represented by L cycles, , (K−L) register means for delaying the operation result data output from the operation means 8. This (K-
L) According to the register means 9 according to the register configuration,
(KL + 1) delay modes are realized (KL +
1) Register selection modes are prepared.

Here, what is to be processed by the pipeline processing execution means 2 includes condition codes and interrupt information in addition to the operation result data.

[0029]

According to the present invention, according to the detection processing of the detection means 3,
When it is detected that the instruction to be input to the pipeline ends the operation execution state with a smaller number of cycles than the instruction preceding the instruction, the calculating means 4
Calculates the difference value of the two cycle numbers, and receives the calculation process of the difference cycle number.
-L + 1) generates a code signal for selecting one of the register selection modes.

On the other hand, the control memory 6 is indexed by the operation code of the instruction input to the pipeline, and reads out a microprogram corresponding to the operation code. Since this microprogram is uniquely prepared for the operation code of the instruction, if it is an instruction that executes an operation in one cycle, a microprogram unique to the instruction is read and the operation is executed in two cycles. If it is an instruction, a microprogram specific to that instruction will be read.

As described above, when the code signal is output from the generating means 5 and the microprogram serving as the control signal of the register means 9 is output from the control storage 6, the register means 9 outputs the code signal and the control signal. , The instruction input to the pipeline has an N-cycle operation execution state, and the instruction preceding the instruction has a longer M-cycle operation execution state. If you have
The instruction of the cycle is processed to be executed in the operation execution state of the M cycle.

As described above, the present invention employs a configuration for detecting a difference value of the number of cycles of the operation execution state between an instruction input to the pipeline and an instruction preceding the instruction, and adopting the differential cycle. According to a numerical value, a configuration is adopted in which how to delay the operation execution state of an instruction input to the pipeline is determined. From now on, by adopting a configuration that executes pipeline processing at high speed by changing the number of cycles of the operation execution state of the instruction to be input to the pipeline, this can be realized with a universal configuration. It becomes.

In the present invention, for example, when the number of execution states of an instruction to be input to the pipeline is one cycle, and when this instruction is executed by one cycle of arithmetic processing, two cycles are required. When it is executed by the arithmetic processing of, and when it is executed by the arithmetic processing of three cycles,
A common microprogram is prepared, and the common microprogram is modified by the code signal of the generating means 5 to realize a calculation process of each cycle number. From now on, when adopting a configuration in which the pipeline processing is executed at high speed by changing the number of cycles of the operation execution state of the instruction to be input to the pipeline, this can be realized with a small microprogram capacity. It becomes.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 2 shows a detailed circuit configuration of the pipeline processing execution means 2 described in FIG.

The pipeline processing execution means 2 shown in FIG.
Reads the data for address calculation from the register stack 10 (including the general-purpose register GR and the floating-point register FR) in the first D state, and reads the data for the base register 11 and the index register 12
Set to. Subsequently, in the A state, the data of the base register 11 and the data of the index register 12 are added by the address adder 13, and the result is set in the register 14 as an effective address.

Subsequently, in the T state, the real address is obtained by converting the effective address of the register 14 by the TLB 15 and the real address is set in the register 16. Subsequently, in the B state, by accessing the local buffer storage 17 with the real address of the register 16, the buffered main memory data is read and set in the register 18.

Subsequently, in the E state, the data stored in the register 18 and the data stored in the register 19 are operated by the calculator 20, and the operation result data is set in the register 21. Subsequently, in the W state, the operation result data stored in the register 21 is written to the register stack 10, and the processing is terminated. The data written in the register stack 10 is set in the register 19 by the register operand bus 22.
In the W state, the condition code and the interrupt information detected in the E state are reported.

In the pipeline processing execution means 2 configured as described above, as described with reference to FIG. 1, the number of cycles of the operation execution state between the instruction input to the pipeline and the instruction preceding the instruction. Is detected, and a code signal corresponding to the difference cycle value is generated. FIG. 3 shows an embodiment of this control mechanism.

As shown in FIG. 3, the control mechanism includes a register 30 for holding an A-state operation code, receives the output of the register 30, decodes the number of operation execution states indicated by the operation code, and executes the operation execution state. A control circuit 31 that determines the number of increase cycles of the register, a register 32 that holds the number of increase cycles of the operation execution state determined by the control circuit 31, and a register 33 that holds the number of operation execution states decoded by the control circuit 31
It is composed of The contents of this register 32 are sent to the operation execution state mechanism described later in the T state.

When the instruction 2 in the figure is input to the pipeline following the instruction 1 in the preceding figure, the control circuit 31
In the A state of the instruction 2, referencing the contents of the register 33 for displaying the number of operation execution states of the instruction 1 to determine the number of cycles to increase the operation execution state of the instruction 2 of the own instruction and writing the number into the register 32 become. When the shortest operation execution state number of the own instruction is smaller than the operation execution state number of the preceding instruction, the number of increase cycles is 2
It is determined by the difference value between the two operation execution states, and the other values are determined as zero values.
That is, the number of cycles in the operation execution state of instruction 1 is 2
In the case where the number of cycles in the shortest operation execution state of the instruction 2 is 1, the difference value 1 is determined as the number of increase cycles, and the number of cycles in the operation execution state of the instruction 1 is 2 and the instruction 2 In the case where the number of cycles in the shortest operation execution state is 2, the number of cycles is determined to be 0.

FIG. 4 shows the circuit configuration of the operation execution state mechanism. Next, the processing in the operation execution state of the present invention will be described with reference to the circuit configuration shown in FIG. Here, the figure shows a processing diagram in the case where an instruction in the operation execution state of one cycle is input to the pipeline and the instruction is executed in the operation execution state of one cycle. FIG. 9 shows a processing diagram in the case where an instruction in a cycle execution state is input to the pipeline, and the instruction is executed in a two-cycle operation execution state.

The pipeline processing executing means 2 sets the operation code sent from the T state in the register 40 in the B state preceding the E state, and controls and stores the contents of the register 40 as an address in the subsequent B state. By indexing 42, a corresponding control signal is read and set in the register 43. When the operation execution state is a one-cycle instruction, the control signal read out at this time indicates that the instruction is executed in accordance with the operation code '01A'.
It is the same whether the execution is performed in the cycle execution state or in the two cycle execution state.

On the other hand, the pipeline processing execution means 2 sets the code value of the increased cycle number sent from the register 32 shown in FIG. Then, in the following E state, this register 4
1 is set in the register 44 and decoded by the decoder 45. In accordance with this process, the decoder 45 outputs “0” when the register 32 of FIG. 3 outputs the number of increase cycles “0” as shown in FIG. When outputting, "1" is output.

On the other hand, the pipeline processing execution means 2 operates in the E state in a computing unit 4 which executes an operation in one cycle.
6, the arithmetic processing of the instruction in the operation execution state of one cycle which has flowed through the pipeline is executed. And
AND gate 4 for calculating the logical product of the control signal held by register 43 and the decoded value output from decoder 45
7, the decoder 45 outputs the decoded value “0”.
Is output, the operation result data of the operation unit 46 is written into the register 49 in the following W state by controlling the selector 48 as shown in FIG.

On the other hand, when the decoder 45 outputs the decode value "1", as shown in, Succeeding V state, writes the calculation result data of the arithmetic unit 46 to the register 50, the output signal of the AND gate 47 By writing to the register 51 and controlling the selector 48 in accordance with the contents of the register 51 in the subsequent W state, the register 5
The operation result data held by 0 is written into the register 49 .

As described above, according to the present embodiment, when the number of execution states of an instruction to be input to the pipeline is one cycle, when the instruction is executed by one cycle of operation processing, In addition, the microprogram prepared in the control storage 42 is common even when it is executed by two-cycle arithmetic processing, so that the capacity of the microprogram in the control storage 42 can be reduced.

On the other hand, if the microprogram is used alone without providing the register 32, the decoder 45, and the AND gate 47, which are the modification means of the microprogram, the instruction in the operation execution state of one cycle is executed by one instruction.
The control memory microprogram of the control signal required for execution in two cycles and the microprogram of the control signal required for execution in two cycles are separately stored in the control memory 4.
2 and, for example, '01A' is assigned as the operation code when it is executed in one cycle.
When executed in two cycles, for example, '1
1A 'is assigned.

When an instruction in the operation execution state of one cycle is to be executed in one cycle, as shown in FIG.
After reading it for microprogram, by controlling the selector 48, write No write operation result data of the arithmetic unit 46 to the register 49 at W state. On the other hand, when an instruction in the operation execution state of one cycle is executed in two cycles, as shown in FIG.
Accordance A ', and read out it for microprogram from control store 42, writes the calculation result data of the arithmetic unit 46 to the register 50 in subsequent V state, followed by W state
In, by controlling the selector 48, so that and writes the operation result data of this to the register 49.

As described above, if an attempt is made to deal with the microprogram alone, there is a disadvantage that the capacity of the microprogram becomes large. FIG. 6 shows another embodiment of the circuit configuration of the operation execution state mechanism shown in FIG. In the figure, the same components as those described in FIG. 4 are denoted by the same reference numerals. Also, as in FIG.
The figure shows a processing diagram in the case where an instruction in the operation execution state of one cycle is input to the pipeline and the instruction is executed in the operation execution state of one cycle. FIG. 9 shows a processing diagram in a case where an instruction in an execution state is input to a pipeline and the instruction is executed in a two-cycle operation execution state.

In this embodiment, the register 54, the register 55, the selector 56 for selecting the data held in the registers 54 and 55, the register 57 for controlling the latch timing of the register 54, and the latch timing for the register 55 And a register 58 for performing the operation.

In accordance with this embodiment, the pipeline processing execution means 2 uses the operation unit 46 which executes the operation in one cycle in the E state to execute the operation of one cycle flowing through the pipeline. The arithmetic processing of the instruction of the state is executed. Subsequently, the arithmetic result data of the arithmetic unit 46 is set in the register 54, and the logical product of the control signal held in the register 43 and the decode value output from the decoder 45 is calculated. When the decoder 45 outputs the decoded value "0" according to the output value of the AND gate 47, the selector 56 controls the selector 56 to read the operation result data held in the register 54, as shown by.

On the other hand, when the decoder 45 outputs the decode value "1", the operation result data held in the register 54 is set in the register 55 following the setting of the operation result data in the register 54 as shown in FIG. Then, by controlling the selector 56, the register 55
Is read out.

As described above, also in this embodiment, when the number of operation execution states of an instruction input to the pipeline is one cycle, and when this instruction is executed in one cycle of operation processing, The microprogram prepared in the control storage 42 becomes common even when the processing is executed by two cycles of arithmetic processing, so that the capacity of the microprogram in the control storage 42 can be reduced.

In the above, the operation pipeline control for the operation result data has been described. However, in order to observe the principle of sequential processing of instructions, the same pipeline control is further executed for the condition code and the interrupt information. We have to go.

[0055]

As described above, according to the present invention,
By adopting a configuration for detecting a difference value of the number of cycles in the operation execution state between an instruction to be input to the pipeline and an instruction preceding the instruction, the number of instructions to be input to the pipeline is determined in accordance with the difference cycle value. High-speed execution of pipeline processing by changing the number of cycles of the operation execution state of the instruction to be input to the pipeline because the configuration that determines how the operation execution state is delayed is adopted. When a configuration is adopted, this can be realized with a universal configuration.

According to the present invention, for example, when the number of execution states of an instruction to be input to the pipeline is one cycle, and this instruction is executed by one cycle of arithmetic processing, The microprogram to be prepared can be commonly used when executing by two cycles of arithmetic processing and by three cycles of arithmetic processing. When adopting a configuration that executes pipeline processing at high speed by changing the number of cycles,
This can be realized with a small microprogram capacity.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit configuration diagram of a pipeline processing execution unit.

FIG. 3 is an embodiment of a control mechanism provided in the present invention.

FIG. 4 is an embodiment of a circuit configuration of an operation execution state mechanism part.

FIG. 5 is an explanatory diagram of a problem in the case of following a conventional technique.

FIG. 6 shows another embodiment of the circuit configuration of the operation execution state mechanism.

FIG. 7 is an explanatory diagram of pipeline processing.

FIG. 8 is an explanatory diagram of a delay in pipeline processing.

FIG. 9 is an explanatory diagram of pipeline processing.

FIG. 10 is an explanatory diagram of a delay in pipeline processing.

FIG. 11 is a circuit configuration diagram for explaining a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 information processing device 2 pipeline processing execution means 3 detection means 4 calculation means 5 generation means 6 control storage 7 calculation execution means 8 calculation means 9 register means

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Yoshida 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. 72) inventor Hideo Yamashita Kawasaki City, Kanagawa Prefecture Nakahara-ku, Kamikodanaka 1015 address Fujitsu within Co., Ltd. (56) reference Patent Sho 63-20538 (JP, a) (58 ) investigated the field (Int.Cl. ^6, DB Name) G06F 9/38

Claims (2)

(57) [Claims] An information processing apparatus configured to provide an operation execution state including a plurality of machine cycles and to perform an operation execution by pipeline processing, wherein an operation execution state of an instruction which may be input to the pipeline is provided. When the maximum cycle number is K cycles and the minimum cycle number is L cycles, (KL) register means (9) for delaying the operation result data, and the instruction inputted to the pipeline has the shortest N cycles Detecting means for detecting whether or not N cycles are smaller than M cycles when the instruction preceding the instruction is an instruction capable of ending the operation execution state in M cycles. 3) and when the detection means (3) detects that the number is small, (M
And calculating means for calculating a -N) cycle (4), according to the difference cycle value calculated in the calculation means (4),
Register selection enabling (KL-1) delay operations
Generating a code signal for selecting one of the select modes
Means (5), and the above-mentioned register prepared according to one instruction per instruction.
A microprogram for controlling the register means (9).
For example, the above microprogram to generate the generation means (5)
Selection of the register means (9) according to the code signal
By executing the processing, the shortest input to the pipeline
Instructions that can end the operation execution state in N cycles
Delay by the difference cycle value calculated by the calculation means (4).
A pipeline control method characterized by processing . 2. An information processing apparatus comprising a plurality of machine cycles, each of which is provided with an operation execution state, and configured to execute an operation in a pipeline. When the maximum cycle number is K cycles and the minimum cycle number is L cycles, (KL) register means (9) for delaying the condition code and the interrupt information are provided. When the instruction that can complete the operation execution state in the shortest N cycles and the instruction preceding the instruction is an instruction that ends the operation execution state in M cycles, it is detected whether N cycles are less than M cycles. When detecting that the number of the detecting means (3) and the number of the detecting means (3) are small, (M
And calculating means for calculating a -N) cycle (4), according to the difference cycle value calculated in the calculation means (4),
Register selection enabling (KL-1) delay operations
Generating a code signal for selecting one of the select modes
Means (5), and the above-mentioned register prepared according to one instruction per instruction.
A microprogram for controlling the register means (9).
For example, the above microprogram to generate the generation means (5)
Selection of the register means (9) according to the code signal
By executing the processing, the shortest input to the pipeline
Instructions that can end the operation execution state in N cycles
Delay by the difference cycle value calculated by the calculation means (4).
A pipeline control method characterized by processing .