JPH0277940A - Data processor - Google Patents

Abstract

PURPOSE:To increase the branch processing speed for a scalar processor which performs such control that decodes and executes simultaneously plural instructions for each machine cycle by preparing a mask register group that holds the branch conditions. CONSTITUTION:A mask register group 103 holds the branch conditions. A mask field 201 of an instruction format includes a subfield (f) which identifies a case where an instruction is carried out based on the contents of the group 103 and a case where an invalid instruction is carried out and a subfield (a) which shows a process after execution of an instruction. Then a logical part 107 invalidates the instructions based on the value of the field (f) and the value of the group 103 and holds the instructions which are through with the value of the field (a) in plural instruction registers 100 until the value of the group 103 is through. At the same time, the part 107 takes out these instructions in the proper timing. Thus it is possible to increase the branch processing speed of a scalar processor which performs such control that decodes and executes simultaneously plural instructions for each machine cycle like a multiple instruction pipeline.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and particularly to a data processing device that speeds up branch processing in a search.

[Conventional technology]

In recent years, it has become important to speed up not only vector processing but also search processing in supercomputers. In particular, the proportion of branch processing in squash processing is 1
It is thought that this will reach 1/4 to 1/3, making it extremely important to increase the speed of one-branch processing.

On the other hand, if the pitch of the instruction pipeline in a space processing processor (hereinafter simply referred to as a space processor) is made finer, it will eventually become impossible to generate an instruction address in units of one instruction. In such an extreme instruction execution state, the instruction word length is limited to one type and control is such that a plurality of instructions are executed in units of one block. That is, instruction parallel pipeline control is performed in which a plurality of instructions are simultaneously decoded in one machine cycle.

As an example of such an instruction-only control method, a "multiple instruction pipeline method" has been proposed (Murakami, Fukuda, Sueyoshi, Tomita, Information Processing Society of Japan Research Report, 88-CA-69).
, p, p, 25-32).

This method is effective in speeding up scalar processing, but9
The effect decreases as the frequency of branch instructions increases.
A multi-instruction pipeline requires a branch processing method that matches the instruction processing method.

[Problem to be solved by the invention]

When a sequence of instructions is divided into blocks, each block is made up of multiple instructions, and control is executed so that each block is executed in one machine cycle, branch processing is divided into cases in which a branch is taken outside the block and cases in which a branch is made within the block. You will be able to do it. When branching out of a block, it can be controlled in the same way as when one instruction is processed in one machine cycle in the conventional art. However, when branching into a block, if controlled using the conventional method, only one instruction can be placed in one block, reducing the effectiveness of the multi-instruction pipeline. In order to eliminate this drawback, branch processing is not simply executed using a multi-instruction pipeline, but a cut-off control method that achieves the same result as the branch processing is implemented using a multi-instruction pipeline.

As a result of branching, (1) Skip execution of instruction sequence, (2) Re-execution of the instruction sequence may be considered.

It is sufficient to control such that these two operations can be executed within one block of instruction sequence. To simply illustrate the essence of branch control within one block, instruction rewriting by instructions within one block is prohibited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that speeds up branch processing in a scalar processor that controls the simultaneous decoding and execution of multiple instructions per machine cycle, such as a multi-instruction pipeline. be.

[Means to solve the problem]

To achieve the above object, a mask register is provided to hold branch conditions. This register is an independent register of the conventional condition code, and is now a plurality of registers.

Depending on the contents of the mask register, there are provided a field (hereinafter referred to as field /) for identifying when an instruction is to be executed or executed as an invalid instruction, and a field (hereinafter referred to as field α) indicating processing after execution of the instruction.

Use one type of instruction word length.

In addition to the above architectural ideas, Field I
The logic part invalidates the instruction according to the value of field α and the value of the mask register, holds the completed instruction in multiple instruction registers until the value of the mask register is completed according to the value of field α, and retrieves it at an appropriate timing. A logic section is provided to output the output.

[Effect]

In order to explain the above-mentioned architectural ideas and hardware operations, a specific instruction expression will be given and explained.

The format shown in FIG. 2 is a series of instruction formats that are compatible with multiple instruction pipelines.

Fields 200, 202, and 201 represent an operation, an operand, and a mask field, respectively.A mask field! , α, and y subfields. When subfield I is 1', the instruction is executed when the value of the mask register specified by the y field is 1', and when it is 0', the instruction is invalidated. When subfield I is 0', the instruction is executed regardless of the value of the mask register. When the subfield α is 11', the instruction is executed when the value of the mask register specified by the y field is 10', and when it is 1', the instruction is invalid. The values of subfield I and α are both 11
', it is a designated exception (if both are 10', it is a normal instruction that does not reference the mask register).

The instruction sequence is divided into blocks, but the breaks between blocks do not simply mean units of instruction fetch operation;
Subfield a indicates a unit for determining the completion condition such that an instruction whose a field is 1' in the block is executed until the value of the mask register designated by the y field of the instruction whose subfield a is 1' becomes 1'. It is also the unit of interrupt seen from O8. Here, in order to simplify the explanation of the operation, 1
Only one type of mask register can be specified by the α field 11/ instruction placed in the block.

Also, when there is no instruction to define the value of the mask register specified by the α field within one block.

Make it a specified exception. An example using the α field is shown.

Ward dd (a=11', MRO) FRO←FRL+A
(<71d<z=GR10) ...■Le4f(a=
ゝ1', MRO) MRO←n/ (FRO≧0)...
・■ add (a=ゝ1', MRO)ORIO11'・
・・■ Le, ρ
. . . ■■ indicates that the contents of the A area indicated by the index register GRIO are added to the contents of the register named FRI and assigned to the FRO register.

(2) checks whether the contents of FRO are 0 or more, and if they are 0 or more, sets the mask register MRO to 1'.

(2) updates the index register 0RIO.

3 is an instruction inserted to match the number of instructions included in one block (if there are three instructions in one block, it is not necessary).

The instruction strings ① to ② are repeatedly executed until the mask register MRO becomes 1', and data processing similar to the D◯ loop made up of branch instructions is performed.

As an example using the f field.

Lajr (/ = 'O') MR1←
＜/(FRO≧0)・・・・・・・■tdd (/=
'1', MRI) FRI←FR1+A (ind<χ
=GR1O)...■5ubtract (/ = '
1', MHI) FR2←FR2-A (<nd4
! z=GR1o)+*+■add (/= '1',
MRI) FR34-FR3+A (<yLd<z=FR
10) ...■.

There is. When the mask register MHI is set to 10' in the first step (2), the instructions (2) to (4) are invalidated, and when MRI is set to 1', they are executed. That is, the same processing as when a branch instruction is placed immediately after ■ is performed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram of a data processing apparatus according to the present invention. In FIG. 1, 100 is an instruction register, 101 is a decoder section, 102 is a register group, 103 is a mask register group, 104 is a switching circuit, 105 is an instruction execution determination section, and 106 is an arithmetic unit. A logic section surrounded by a dotted line 107 is a multi-column portion of a multi-instruction pipeline. The arithmetic unit 106 outputs the result on the path 170 if the write register is designated as the register on the 102 side by the instruction. On the other hand, if the write register is the mask register 103, the result is output to the path 171 side. A write register number is attached to the output result, and the respective switching circuits 110 and 111 write to the target register according to this information.

The instruction pipeline is ゛F' up to instruction register 100.
, registers 112 to 116 are ID'.

Registers 117 to 120 are 'E', register group 10
The writing up to 2. (or 103) is W', which is 4 stages in total. The number of stages may be any number.

The signal set in the instruction register 100 is sent to the decoder 10
1 is decoded. On the path 150, the order that defines the calculation operation, /field information, and the write register number of the calculation result are sent. α field information is on the path 162,
The operand data read from the register group 102 or the mask register 103 is sent onto the path 163. pass 15
The signal above 0 is processed by the instruction execution determination circuit 105 and passed to pass 1.
The arithmetic unit 106 statement on 55 is the address adder 40 in FIG.
An instruction signal to 0 is sent. The signal sent on path 163 acts on switching circuit 104 to send the operand data onto paths 157-158. Mask register 1
The data read from 03 is sent onto the path 160 and sent to the instruction execution determination circuit 105.

In order to simplify the drawings, several types of signals are sometimes represented by one signal line. Even if there is only one signal line in the schematic block diagram, when it is divided into a plurality of signal lines in the detailed block diagram, a subscript such as α+ by c . . . is added to the number indicating the signal line.

FIG. 3 is a block diagram of a logic section (instruction read logic section) for setting an instruction in the instruction register 100 of FIG. In FIG. 3, a multiple of the instruction word length is set in a register 300.

Here, 几 is the multiplicity of the multiple instruction pipeline.

First, the start address of the user program is set in the register 302 from the instruction decoder 101 in FIG. 1 via the path 154. The O8 starts the program. O
8 issues a privileged instruction to set data on the main memory in the register 302, and the above processing is performed. The start address of the program is sent to buffer storage via path 360.3-61. Instructions read from buffer storage are sent to instruction register 1 via path 175 in FIG.
Set to 00. An advance signal is sent from the buffer storage on path 176 in response to the read instruction. Advance signals are F, D, and E of the instruction pipeline.
, W stages are set in the registers 310 to 313. Logic circuit 314 connects register 302 . This is a logic unit that generates a set signal for the instruction register 100. pass 159
When the set signal is sent to the adder 301, the instruction address on the path 361 and the data on the register 300 are sent to the adder 301.
The next instruction address that has been added and sent on path 154 is set in register 302.

The register 303 stores the start address of the interrupt processing routine when an exception occurs. When a signal indicating that a designated exception or the like has been detected is issued on the paths 550 and 551, these detection signals are collected by the OR circuit 304 and act on the selector 305. Selector 305 is register 303
The output of is connected to path 361, and the process shifts from user program processing to interrupt processing routine processing. At this time, the address of register 302 is set in register 306.

When processing is completed in the interrupt processing routine and control is transferred to the user program again, the selector 305 selects the signal on the path 150σ from which the opcode is decoded from the decoder 101 in FIG.
to connect paths 360 and 361. The address saved in the register 306 is sent to the buffer storage via path 367, and from there it is sent to the buffer storage via path 15.
It is set in the register 302 at the fourth output.

This method is just one example, and it is also possible to send the address of the register 302 to the register group 102 in FIG. 1 and perform the save and recovery process. In this case, the sink destination of the path 367 is the switching circuit 110 in FIG. 1, and the path 157 is connected to the register 302.

FIG. 4 is a block diagram of a portion of an address adder that issues an address specified by an operand to a buffer storage. The address adder operation is performed in the E stage of the instruction pipeline. The data read from register group 102 sent on path 157.8 is stored in registers 401 to 40.
4 and input to adder 400 to generate an operand address. This address is path 45o.

451 to the buffer storage.

FIG. 5 is a block diagram of decoder 101 of FIG. 1.

The instruction set in the instruction register 100 is OP, /, α
, y, and R1 to R3 fields. These are the opcode, /, α, and y subfields, and three operand fields, respectively. The opcode is sent to RA via path 555.
M500 is cited to generate order information for the arithmetic unit or address adder. These pieces of information are set in register 501. Here, it is assumed that 1' is set in the register 5016 at the time of an instruction to set a value in the mask register. The output of the register 5018 is ANDed with the value of the α subfield by an AND circuit 502. AND circuit 502 corresponds to decoder 101 in FIG. The outputs of the plurality of AND circuits 502 are logically summed by an OR circuit 503, inverted by an inverter 504, and sent onto a path 550. The signal on path 550 becomes 1' when the α subfield is 1' in one block (that is, there is an instruction that is repeatedly executed) and there is no instruction that sets a value in the mask register. The signal detects a condition of specified exception.

The mask register number of the y subfield is determined by the comparator circuit 50.
6 is compared with the mask register number of the y subfield of other instruction registers. When the two match, an output "1" is obtained. The output is inverted and then sent to the AND circuit 5.
A logical product is taken at step 07, and a logical sum is taken at an OR circuit 508. Information as to whether the α subfield of the instruction is 1' is input to the AND circuit 507. OR circuit 508
The output becomes ``1'' when a different mask register is referenced by the instruction of α field ``1'' within one block. pass 5
The signal on 51 detects one condition of the specified exception.

! , α, y subfields, and R1 to R3 fields are once latched and then passed through each path 150.
(L, 162, 163c, 150c.

163α,b.

FIG. 6 is a block diagram of the instruction execution determination circuit 105 of FIG. 1. In FIG. 6, when the value of the mask register is read on path 160α, an AND circuit 600 performs a logical product with the successive result of the f subfield on path 150cL. This result is! Next, register 601 indicates whether the instruction whose subfield is 1' is executed.
The output is inverted by an inverter 602, and logically multiplied with the α subfield data on the path 162 by an AND circuit 603. This result indicates whether the instruction whose α subfield is 1' is executed or not. ! When the subfield is 0', the instruction is executed regardless of the value of the mask register.

Therefore, the output of the register 604 is inverted by an inverter 605 and input to the OR circuit @606. The same circuit has an execution condition when the I subfield is 1', and an execution condition when the α subfield is 1'.
The execution conditions at the time are input through paths 651 and 652, respectively. An order signal for executing an instruction is sent on path 155α. When this signal is O', the instruction is processed as an invalid instruction. That is, the path 155 instructs the arithmetic units and address adders in FIGS. 1 and 4 to not operate.

When the outputs of registers 604 and 607 are both 1', that is! ,
When both α subfields are 1', a designated exception signal is sent on path 650. This signal is transmitted to the OR circuit 30 in FIG.
Sent to 4.

FIG. 7 is a block diagram of the switching circuit 104 of FIG. 1. In FIG. 7, register 700 is one of the mask registers. The output of the register 700 is the selector 70
1,702, and signals on paths 163 and 164 select the output of the mask register specified by the instruction and send it out on paths 160a,b.

FIG. 8 is a block diagram of logic circuit 314 of FIG. 3.

Data of the α subfield is sent from the decoder 101 in FIG. 1 via paths 162 and 172. pass 152
, 153, mask register data is sent from the arithmetic unit 106 in FIG. Assume that this logic circuit operates in the W stage.

For instructions that do not use the α subfield, the mask side output (path 171 side) of the arithmetic unit is set to 0'.

In FIG. 8, AND circuits 800 and 801 detect a condition in which an instruction using the α subfield (that is, the field is 1') is completed when the value of the mask register becomes 1'. AND circuit 80o.

Reference numeral 801 corresponds to the instruction register 100 in FIG.

The output of the circuit is logically summed by an OR circuit 802, and then
The output is sent to D circuit 803.

The OR circuit 804 determines whether there is a case where there is only an instruction that does not use the α subfield. The output of the OR circuit 804 is input to the AND circuit 803, and at the same time it is inverted and output as O.
It is input to the R circuit 805.

When the signal on path 850 is 1', the α subfield is 11.
' and the mask register becomes 1'. This shows that when the signal on path 851 is 11', the α subfield is 0' for all instructions within one block. The logical sum of the two is taken to generate an instruction signal on path 852 for reading out the instruction sequence of the next block. Path 350 propagates a signal indicating that the instruction is entering the W stage. An AND circuit 806 is provided for stage alignment with the instruction pipeline.

Signals on path 159 are used to set instruction register 100 in FIG. 1 and register 302 in FIG.

〔Effect of the invention〕

According to the present invention, in a data processing device that employs a control method that executes a plurality of instructions in one machine cycle, when a sequence of instructions executed in one machine cycle is called one block, the branch processing performed within one block is as follows: High-speed processing is possible using the concept of mask data that affects instruction execution processing. Furthermore, by holding mask data in a plurality of registers called mask registers that can be accessed by a program, it becomes possible to freely separate setting of branch conditions from branch instructions.

Furthermore, a program with a loop structure that is repeatedly executed within one block can be executed by holding a sequence of instructions in the instruction register. This effect allows processing to be performed without performing an instruction fetch operation to the main memory, buffer storage, etc., and has the effect of enabling much faster loop processing than the conventional branch acceleration method.

4. Brief description of the drawings - Fig. 1 is a schematic block diagram of the data processing device of the present invention, Fig. 2 is an instruction format diagram, Fig. 3 is a block diagram of the instruction read logic section, and Fig. 4 is an address adapter diagram. block diagram of the department,
5 is a block diagram of the decoder section, FIG. 6 is a block diagram of the instruction execution determination circuit, FIG. 7 is a block diagram of the switching circuit, and FIG. 8 is a block diagram of the logic circuit 314 of FIG. 3.

100...Instruction register.

101...Decoder, 102...(General purpose/floating point) register group, 103
... Mask register group, 105 ... Instruction execution determination circuit, 106 ... Arithmetic unit, 301 ... Adder.

506... Comparison circuit.

Akira/IEI tail 20 cross country 6th fjEJ 86th eye 7th eye

Claims (1)

[Claims] 1. A data processing device that divides and executes execution of instructions into a plurality of stages, characterized in that logically identical stages of a plurality of instructions are executed at the same timing. . 2. According to claim 1, a plurality of registers are provided that act on an instruction execution method, and the instruction field is used to select whether to execute the instruction or not, or whether to execute the instruction again after executing the instruction, depending on the contents of the register in the instruction field. A data processing device characterized by having an area for making a selection. 3. A data processing device according to claim 2, wherein completion conditions for a plurality of instruction sequences to be executed at one timing of the data processing device are generated by ANDing the contents of the register and a specific field of the instruction. 4. The data processing device according to claim 1, wherein an exception in a sequence of instructions executed at one timing of the data processing device is detected in parallel, and control is passed to the interrupt processing section using this as an opportunity.