JP2904624B2 - Parallel processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline type parallel processing device capable of processing a plurality of instructions in parallel, and more particularly, to at least one load instruction included in a plurality of preceding instructions. And a load instruction processing control method suitable for the

[0002]

2. Description of the Related Art Conventionally, VLIW (Very Long Instructio)
n) A computer (parallel processing unit) that processes multiple instructions in parallel (simultaneously), such as the Word) and Superscalar methods
In the case where there is a reference relationship in a register, a memory, or the like among a plurality of instructions to be input simultaneously (herein, called a compound instruction), a waiting time for guaranteeing the execution order relationship occurs, and the processing performance is reduced. It greatly decreases. For this reason, in this type of computer, it has been known that the waiting by the above-mentioned reference relationship is reduced by performing static program scheduling by a compiler.

[0003]

However, with static scheduling by a compiler, it is difficult to handle dynamically determined dependencies such as memory addresses.
Therefore, these dynamic dependencies must be analyzed by hardware support to guarantee the execution order.

A typical instruction for generating the above-mentioned dynamic dependency is a load instruction (reading of memory data).
The memory access by this load instruction is usually performed via a cache memory. For this reason, as long as the cache hits, even if an attempt is made to guarantee the order of instructions that depend on the load instruction, the effect on performance is small. However,
In the case of a cache miss, a block read occurs, so that the overhead is several times to several tens times that of the cache hit before the load data is obtained. In the conventional parallel processing unit, when a load instruction miss occurs, only a subsequent compound instruction is made to wait unconditionally, resulting in a large decrease in performance.

The present invention has been made in view of the above circumstances, and has as its object to reduce the waiting time of the subsequent compound instruction as much as possible and improve the processing performance even when the load instruction is a cache miss. An object of the present invention is to provide an arithmetic processing device.

[0006]

According to the present invention, a plurality of instructions (composite instructions) fetched by an instruction fetch mechanism are provided.
In a pipeline-type parallel operation processing device capable of processing data in parallel, at least between a compound instruction fetched earlier (preceding compound instruction) and a compound instruction fetched later (subsequent compound instruction) A dependency detection means for detecting the existence of one dependency; and a pipeline control mechanism for controlling a flow of the pipeline in accordance with a detection result of the dependency detection means. When there is no dependency with the compound instruction, the subsequent compound instruction is not made to wait even if the preceding compound instruction includes a load instruction.

Further, the present invention provides the above-mentioned dependency detecting means, wherein when a load instruction is included in the preceding compound instruction, the load data write destination specified by the load instruction is in use. State holding means, and load data write destination indicated by the state holding means,
And a match detecting means for detecting a match with an access destination specified by any one of the subsequent compound instructions.

[0008]

With the above arrangement, the dependency detection means detects whether or not a dependency exists between the preceding compound instruction and the subsequent compound instruction. For this detection, a state holding unit and a coincidence detecting unit are prepared. When the result of decoding of the fetched compound instruction indicates that a load instruction is included, the state holding means indicates that the load data write destination specified by the load instruction is in use. Information is retained. When a new compound instruction (subsequent compound instruction) is newly fetched by the instruction fetch mechanism, the coincidence detecting means outputs the load data write destination in the use state indicated by the state holding means at that time.
That is, when the preceding compound instruction includes a load instruction, it is determined whether the load data write destination specified by the same instruction matches the access destination specified by any of the following compound instructions. , And notifies the result to the pipeline control mechanism.

When the pipeline control mechanism receives a match / mismatch notification from the match detection means (within the dependency detection means), in the case of a match notification, the pipeline control mechanism intervenes between the subsequent compound instruction and the preceding compound instruction. Assuming that at least one dependency exists, the execution of the subsequent compound instruction is made to wait. On the other hand, in the case of a mismatch notification, the pipeline control mechanism:
Assuming that there is no dependency between the subsequent compound instruction and the preceding compound instruction, execution of the subsequent compound instruction is permitted.
As a result, even if the preceding compound instruction includes a load instruction and the instruction becomes a cache miss and is being read in a block, the subsequent compound instruction can be executed without waiting for the completion of the block read processing. Is executed to avoid unnecessary waiting time.

[0010]

FIG. 1 is a block diagram showing a configuration of a parallel processing unit according to an embodiment of the present invention. The parallel operation processing device of FIG. 1 includes, for example, a composite instruction fetch stage (I stage), a composite instruction decode stage (D stage), a composite instruction execution (including a cache access of a load instruction) (E stage), It is assumed that the computer is a four-stage pipeline processing computer that executes four instructions in parallel and applies a four-stage pipeline method of a stage (W stage) for writing a result (register write-back). In the arithmetic processing device of FIG. 1, it is assumed that the number of load instructions included in the four instructions processed in parallel is limited to one.

In FIG. 1, reference numeral 1 denotes an instruction fetch mechanism for fetching four instructions to be executed in parallel from a program storage device (not shown) such as an instruction cache or a main memory, and 2 denotes an instruction fetch mechanism fetched by the instruction fetch mechanism 1.
Instruction register for holding instructions.

Reference numeral 3 denotes a general-purpose register file including, for example, four registers R1 to R4, and reference numeral 4 denotes a decoding / register reading mechanism. The decoding / register reading mechanism 4 decodes the four instructions held in the instruction register 2 in parallel for each instruction, and when a source in the register file 3 is designated by the instruction, the contents of the register are read. Is read as source data. The decoding / register reading mechanism 4 includes a (4-bit) register use signal 41 indicating whether or not there is a load instruction to which the registers R1 to R4 in the register file 3 are to be loaded with the load data among the four decoded instructions. Indicates whether any of the four decoded instructions has an instruction to access (reference or write) the registers R1 to R4 in the register file 3 (4 bits).
A register use signal 42 is output.

Reference numeral 5 denotes a decoding result register for holding the decoding result for four instructions of the decoding / register reading mechanism 4 for each instruction. The information held in the decryption result register 5 includes register data read by the decryption / register reading mechanism 4 or load data read by the load execution mechanism 7 described later, depending on the instruction.

Reference numeral 6 denotes an operation executing mechanism for executing the operation indicated by the result of decoding when the result of decoding of the operation instruction is held in the decoding result register 5. The operation execution mechanism 6 includes four operation units in order to execute parallel operation processing for up to four instructions. When the decoding result register 5 holds the decoding result of the load instruction (the instruction to read out the memory data as the load data and write it into the register in the decoding result register 5), it executes the load processing indicated by the decoding result. It is a load execution mechanism. Load execution mechanism 7
Has a built-in operand cache (not shown),
A hit check is performed to determine whether or not the data specified by the load instruction exists in the same cache. When a mishit is detected, a block read from the memory is executed. The load execution mechanism 7 outputs a hit detection signal 8 that becomes a true value (logic "1") when a hit is detected.

Reference numeral 9 indicates that when a load instruction is included in a preceding compound instruction, there is a dependency (reference relation) regarding the use of a register in the register file 3 between the load instruction and the subsequent compound instruction. This is a dependency detection circuit for detecting the operation.

The dependency detection circuit 9 is a 4-bit (b0-b3) flag register 10 for holding the true value of the register use signal 41 corresponding to the registers R1-R4 output from the decryption / register read mechanism 4. And the logical values of the bits b0 to b3 of the flag register 10, the logical values of the register use signals 42 corresponding to the registers R1 to R4 output from the decryption / register read mechanism 4, and the load execution mechanism 7.
AND gates 11 to 14 which take AND (logical product) of the logical value of the level inversion signal of hit detection signal 8 output from
It is composed of

The bits b0 to b3 of the flag register 10 are
The reset is performed when the execution of the load instruction with the corresponding registers R1 to R4 as write destinations is completed. When the AND gate condition is satisfied, the AND gates 11 to 14 output WAIT signals 21 to 24 for instructing to wait for the execution of instructions after the compound instruction currently being processed by the decoding / register reading mechanism 4.

Reference numeral 25 denotes a pipeline control mechanism for controlling the pipeline of the apparatus shown in FIG. The pipeline control mechanism 25 includes the AND gate 11 (in the dependency detection circuit 9).
If any of the WAIT signals 21 to 24 from to 14 is true, execution of the instructions following the compound instruction currently being processed by the decoding / register reading mechanism 4 is made to wait.

Reference numerals 31 to 34 denote selectors (SEL) for selecting either one of the operation results corresponding to the four instructions of the operation execution unit 6 or the load data read from the memory by the load execution unit 7. Selectors 31-34
Is set to select the operation execution mechanism 6 in the normal state. Note that an identifier (for example, a register number) indicating the write destination is added to the operation result and the load data. 35 is selector 3
This is an operation result register for holding data selected by 1 to 34. The data held in the operation result register 35 is written to a write destination (for example, a register in the register file 3) specified by the identifier added to the data.

Next, the operation of the configuration shown in FIG. 1 will be described by taking, as an example, a case where three compound instructions including a load instruction are sequentially executed, and a register reference relationship (RAW; Read After Write) between compound instructions.
The case without e) (case 1) and the case with reference (case 2) will be described in order.

(Case 1) First, Case 1 will be described with reference to the timing chart of FIG. Here, as shown in FIG. 2, the first compound instruction CI1 is a load instruction L → R1 (a load instruction that reads load data from a memory and writes it into register R1), an addition instruction +, a multiplication instruction ×, and a subtraction instruction. -Four instructions, and the compound instruction CI
2 is a load instruction L → R2, a subtraction instruction −, an addition instruction +,
And a multiplication instruction × 4, and the composite instruction CI3 is
Load instruction L → R3, subtraction instruction−, division instruction ÷, and subtraction instruction−, which are compound instructions CI1 → CI2 →
Register reference relationship between CI3 (RAW; Read After W
rite).

First, in the cycle T1, the I stage is performed by the instruction fetch mechanism 1, and the first composite instruction CI1
Is fetched. The composite instruction CI1 is held in the instruction register 2.

In the next cycle T2, the D stage for each instruction of the compound instruction CI1 held in the instruction register 2, that is, instruction decoding is performed by the decoding / register reading mechanism 4, and the decoding result is obtained for each instruction. The result is stored in the decryption result register 5. At the same time, the next I stage is performed by the instruction fetch mechanism 1, and the compound instruction CI2 next to the compound instruction CI1 is fetched and held in the instruction register 2.

In the D stage of the compound instruction CI1,
Since the load instruction L → R1 is included in the same CI1,
The decoding / register reading mechanism 4 outputs a 4-bit register use signal 41 "1000" in which the bit corresponding to R1 among R1, R2, R3 and R4 is a true value. This register use signal 41 is supplied to the 4-bit flag register 10 of the dependency detection circuit 9, and a bit in the flag register 10 corresponding to a bit having a true value in the signal 41 is set at the end of the cycle T2. . Here, the bit b0 in the flag register 10 corresponding to R1 is set, and the content of the flag register 10 becomes "1000".

In the next cycle T3, according to the decoding result of each of the +, × and-instructions in the compound instruction CI1 held in the decoding result register 5, the operation execution unit 6 adds +, × and-.
(E stage) are performed in parallel. The result is selected by each of the selectors 32 to 34 and held in the operation result register 35.

In cycle T3, the load instruction L → R1 in the composite instruction CI1 held in the decryption result register 5
According to the result of decoding, the load execution mechanism 7 performs a process for reading the load data. In this process,
First, a hit check is performed to check whether the target load data exists in the operand cache. Here, assuming that there is a mishit, the load execution mechanism 7 starts block reading for reading block data including target data from the memory, and does not set the hit detection signal 8 to a true value.

Further, in the cycle T3, the D stage for each instruction of the second compound instruction CI2 held in the instruction register 2 is executed by the decoding / register reading mechanism 4, and the result is held in the decoding result register 5. Is done. At the same time, the compound instruction CI3 following the compound instruction CI2 is fetched by the instruction fetch mechanism 1 and held in the instruction register 2.

In the D stage of the compound instruction CI2, the register R2 in the register file 3 is included in the four decoded instructions.
There is a load instruction L → R2 whose access destination (write destination) is “0”.
A 4-bit register use signal 41 of "100" is output. If it is assumed that there is no instruction that makes the register in the register file 3 an access destination (reference destination, write destination) in the other three instructions, the decoding / register A 4-bit register use signal 42 whose value is "0100" is output from the read mechanism 4. At this time, the content of the flag register 10 is "100".
0 ", and the WAIT signals 21 to 24, which are output signals of the AND gates 11 to 14, do not become true values.

When the WAIT signals 21 to 24 are all false values, the pipeline control mechanism 25 determines that there is no register reference relationship between the compound instructions in the pipeline.
Refrain from stopping the pipeline flow (pipe lock). As a result, in the next cycle T4, as described below, the composite instruction CI1 currently in the E stage enters the W stage (excluding the load instruction L → R1 during block read), and enters the composite stage in the D stage. The instruction CI2 enters the E stage, and the composite instruction CI3 in the I stage enters the D stage. This is the same result even if there is an instruction in the compound instruction CI2 to access the register in the register file 3 if the access destination is not R1.

In cycle T3, as described above, the decoding / register reading mechanism 4 outputs the value "4" of "0100".
Since the bit register use signal 41 is output, R
Bit b1 in flag register 10 corresponding to 2 is set at the end of cycle T3. As a result, the content of the flag register 10 changes from "1000" to "1100".

In the next cycle T4, a W stage for writing the operation result of each of the +, ×, and − instructions in the composite instruction CI1 held in the operation result register 35 to the designated write destination is performed. Further, in accordance with the decoding result of each of the-, +, and x instructions in the composite instruction CI2 held in the decoding result register 5, each of the-, +, and -X operations (E stage) is performed in parallel in the execution unit 6. , Are held in the operation result register 35 via the selectors 32 to 34.

In cycle T4, load instruction L → R2 in compound instruction CI2 held in decoding result register 5
According to the result of decoding, the load execution mechanism 7 performs a process for reading the load data. Here, assuming that a mishit in which the target load data does not exist in the operand cache is detected, block reading is started, and the hit detection signal 8 remains a false value.

Further, in cycle T4, the D stage for each instruction of the third compound instruction CI3 held in the instruction register 2 is executed by the decoding / register reading mechanism 4, and the result is held in the decoding result register 5. Is done.

In the D stage of the compound instruction CI3, since the load instruction L → R3 is included in the decoded four instructions, the decode / register read mechanism 4 outputs the 4-bit register use signal 41 having the value “0010”. You. In addition, other three
Assuming that there is no instruction that makes the register in the register file 3 an access destination (reference destination, write destination) in the instruction,
From the decryption / register read mechanism 4, the value of "0010"
A bit register use signal 42 is output. At this time, the content of the flag register 10 is “1100”, and the WAIT signals 21 to 21 which are the output signals of the AND gates 11 to 14 are output.
24 is not a true value. For this reason, no pipe lock is performed, and in the next cycle T5, the composite instruction CI2 currently in the E stage is changed from the load instruction L → R
After entering 2, the stage enters the W stage, and the compound instruction CI3 in the D stage enters the E stage.

(Case 2) Next, Case 2 will be described with reference to the timing chart of FIG. Here, as shown in FIG. 3, the first composite instruction CI11 is a load instruction L → R1, an addition instruction +, a multiplication instruction ×, and a subtraction instruction −, and the composite instruction CI12 is a load instruction L → R2, a subtraction instruction-, an addition instruction R1 + R2 for adding the contents of the registers R1 and R2, and a multiplication instruction x.
3, a subtraction instruction-, a division instruction ÷, and a subtraction instruction-.
Assume that there is a reference relationship of 1.

In case 2, first, in cycle T1,
An I stage for fetching the compound instruction CI11 is performed. In the next cycle T2, a D stage for decoding the compound instruction CI11 is performed, and an I stage for fetching the compound instruction CI12 next to the compound instruction CI11 is performed. In the D stage of the compound instruction CI11, the value is “100” because the load instruction L → R1 is included in the CI1.
A register use signal 41 of "0" is output from the decryption / register read mechanism 4, whereby the content of the flag register 10 becomes "1000" at the end of the cycle T2.

In the next cycle T3, the composite instruction CI11
In accordance with the result of the D stage of each of the +, ×, and − instructions, the +, ×, and − operations (E stage) are performed in parallel in the operation execution mechanism 6, and the operation result registers are provided via selectors 32 to 34. 35.

In cycle T3, compound instruction CI11
According to the result of the D stage of the middle load instruction L → R1, the load execution mechanism 7 performs a process for reading the load data. Here, assuming that a mishit in which the target load data does not exist in the operand cache is detected, block reading is started, and the hit detection signal 8 remains a false value.

In the cycle T3, the D stage for each instruction of the second compound instruction CI12 is performed by the decoding / register reading mechanism 4. At the same time, the compound instruction CI13 following the compound instruction CI12 is
Fetched by

In the D stage of the compound instruction CI12, since the load instruction L → R2 is included in the instruction CI12, the register use signal 41 having the value “0100” is output from the decoding / register reading mechanism 4. You. Since the instruction CI12 also includes the addition instruction R1 + R2, if there is no instruction that makes the register in the register file 3 an access destination (reference destination or write destination) among the remaining instructions, the decoding / The register read mechanism 4 outputs a 4-bit register use signal 42 having a value of “1100”. At this time, the content of the flag register 10 is "100
Since the hit detection signal 8 is a false value, only the WAIT signal 21 of the WAIT signals 21 to 24 from the AND gates 11 to 14 has a true value.

As described above, when at least one of the WAIT signals 21 to 24 (here, the WAIT signal 21) is a true value, the pipeline control mechanism 25 determines whether or not the currently executed composite instruction and a subsequent composite instruction are to be executed. , A pipe lock for stopping the pipeline flow is performed. As a result, the compound instruction CI12 (including the addition instruction R1 + R2) next to the currently executing compound instruction CI11 is at the D stage, and the next compound instruction CI13 is at the I stage.
As described below, the process waits until the execution of the load instruction L → R1 in the composite instruction CI1 is completed.

In this embodiment, the block read process of the load execution unit 7 according to the load instruction L → R1 in the compound instruction CI11 is completed in cycle T5, and the designated data (load data) is output from the load execution unit 7. It shall have been done. This load data is selected by the selector 31 and, at the end of the cycle T5, the operation result register 35
Is held. The load data is held in the decoding result register 5 as if it were data read from the register R1 by the decoding / register reading mechanism 4.

As described above, when the processing of the load instruction L → R1 in the composite instruction CI11 is completed in the cycle T5, the bit b0 in the flag register 10 corresponding to R1 is set.
Is reset. As a result, the content of the flag register 10 changes from “1100” to “0100”. At this time, since the composite instruction CI12 including the addition instruction R1 + R2 is stopped in the D stage, the register use signal 42 output from the decoding / register read mechanism 4 is "11".
00 ", but since the contents of the flag register 10 have become" 0100 ", the AND gates 11 to 14
Are not satisfied, and all of the WAIT signals 21 to 24 become false values. As a result, the pipeline control mechanism 25 releases the pipe lock on the assumption that there is no register reference relationship between the compound instructions in the pipeline. As a result, in the next cycle T6, the compound instruction CI11 currently in the E stage enters the W stage, the compound instruction CI12 in the D stage enters the E stage, and the compound instruction CI13 in the I stage enters Enter the D stage.

In the processing of the load instruction L → R1 in the composite instruction CI11 in the load execution unit 7, if a cache hit is detected and the hit detection signal 8 becomes a true value, the composite instruction CI11 and the succeeding instruction Compound instruction C1
Even if there is a reference relationship of register R1 with
The AND condition of AND gate 11 (~ 14) is not satisfied,
The WAIT signal 21 (to 24) becomes a false value. in this case,
The pipeline control mechanism 25 does not stop the flow of the pipeline. That is, when a cache hit is detected by the load execution unit 7, the load processing is completed in that cycle, the target load data is held in the operation result register 35 and the decryption result register 5, and in the next cycle, This is because the addition instruction R1 + R2 using the load data can be performed. In the above, the parallel processing device that processes four instructions in parallel has been described. However, the present invention is applicable to all parallel processing devices that process a plurality of instructions in parallel. Further, for simplicity of description, the description has been made assuming that the number of load instructions included in the compound instruction is limited to one, but it is a matter of course that the present invention is not limited to this.

[0045]

As described in detail above, according to the present invention,
In a parallel processing device of a pipeline system, it is checked whether or not at least one dependency exists between a preceding compound instruction and a following compound instruction. Even if a load instruction is included, the following compound instruction is not made to wait.
Even if a load instruction causes a cache miss and a long block read process is performed, only the load instruction during the block read can be narrowed down and the subsequent compound instruction can be executed. The processing performance can be improved by minimizing the time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a parallel operation processing device according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation when there is no register reference relationship between compound instructions in the embodiment.

FIG. 3 is a timing chart for explaining an operation when a compound instruction has a register reference relationship in the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Instruction fetch mechanism, 2 ... instruction register, 3 ... register file, 4 ... decoding / register read mechanism, 5 ... decoding result register, 6 ... operation execution mechanism, 7 ... load execution mechanism, 9 ... dependency detection circuit, 10 ... Flag registers (state holding means), 11 to 14 AND gates (coincidence detecting means), 25... Pipeline control mechanism, 35.

Claims (2)

(57) [Claims] 1. A pipeline-type parallel processing device capable of processing a plurality of instructions fetched by an instruction fetch mechanism in parallel, comprising: a plurality of preceding instructions fetched earlier by said instruction fetch mechanism; Dependency detection means for detecting that at least one dependency exists between a plurality of subsequent instructions fetched later, and a flow of the pipeline according to a detection result of the dependency detection means. A pipeline control mechanism for controlling, wherein the pipeline control mechanism detects that there is no dependency between the preceding plurality of instructions and the following plurality of instructions by the dependency detection unit. in case of,
A parallel processing device, wherein even if a load instruction is included in the preceding plurality of instructions, the subsequent plurality of instructions are not made to wait. 2. A state in which, when a load instruction is included in the plurality of preceding instructions, the dependency detection unit indicates that a load data write destination specified by the load instruction is in use. Holding means, and match detecting means for detecting that the load data write destination indicated by the state holding means matches the access destination specified by any of the subsequent instructions. 2. The parallel processing device according to claim 1, wherein: