JPH0786838B2 - Interrupt processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention According to the present invention, the execution of some CPU resource consuming processing, which has a long processing time, is asynchronous with the execution of an instruction while guaranteeing the data dependency of the processing. The processing ends after the instruction ends.
After executing the instruction that started the process, the PU starts executing the next instruction before the end of the started process. ) C
The present invention relates to a method of terminating an asynchronous CPU process when an interrupt occurs in a PU and a method of reporting a CPU resource use process dependent interrupt factor generated in these asynchronous CPU processes. In particular,
The present invention is effective when the basic processing used by the interrupt handler of the OS is executed asynchronously with the instruction.

[0002]

2. Description of the Related Art Even in a CPU that executes a CPU resource use process having a long processing time in synchronization with an instruction, if a subsequent instruction is partially executed in advance and a program interrupt occurs in the previous processing, By canceling the influence, it is possible to partially execute the succeeding instruction of the instruction having a long processing time. However, in this case, CP
The instruction pipeline of U becomes complicated, and the preceding execution of subsequent instructions can be executed only within a limited range.

Therefore, in order to improve the CPU performance by not stopping the execution of the instruction of the CPU which can be executed simultaneously (there is no data dependency relation with the previous processing) when the CPU resource use processing having a long processing time is executed. One of the effective methods is to make the execution of the CPU resource consuming processing that takes a long processing time asynchronous with the execution of the instruction. At this time, 1
Multiple CPUs including more than one asynchronous CPU resource usage process
The resource use processing is executed at the same time.

In the conventional computer, the CPU when an interrupt occurs
One of the following methods has been used as a method of ending the resource use processing. There are two types of interrupts, a CPU resource use process dependent interrupt and a CPU resource use process independent interrupt. (1) The CPU resource use processing is all processing executed in synchronization with the instruction. When a CPU resource use process dependent interrupt factor is detected during the execution of an instruction, a corresponding CPU resource use process dependent interrupt occurs after the end of the execution of an instruction and before the start of the execution of the next instruction. The last executed instruction, C
The corresponding CPU resource use process independent interrupt occurs only when the PU resource use process dependent interrupt factor is not detected and when the CPU resource use process independent interrupt factor exists.

[0005]

In this method, since the CPU resource use processing started before the interrupt at the time of the interrupt is completed, it is easy to create the interrupt handler. Further, in the case of an interrupt for a necessary CPU resource use processing dependent interrupt factor, the original program can be restarted after the appropriate processing of the interrupt handler.

However, in the case of this processing (instruction) execution method, during execution of a CPU resource use processing that takes a long time to execute,
The execution of the subsequent CPU resource use processing cannot be completed, and at this time, the performance of the CPU deteriorates. (2) Processing in which a unit that performs input / output to some CPU resources and operates asynchronously (for example, a floating-point arithmetic unit) is started asynchronously with the execution of an instruction (asynchronous CPU resource use processing) ) Is executed. In these asynchronous CPU resource use processes, when a CPU resource use process dependent interrupt factor is detected, at the time of execution of an instruction to start a process that uses the CPU resource accessed next from this unit or a process to be executed by this unit. The processing specified by the instruction is not executed, and a CPU resource use processing dependent interrupt held by the asynchronous operation unit occurs in synchronization with the instruction.

When an interrupt factor other than the CPU resource use process dependent interrupt detected by the asynchronous operation unit is detected and an interrupt corresponding to this is generated, the end of the operation of the asynchronous operation unit is not waited. Further, at this time, the CPU resource use processing-dependent interrupt factor held by the asynchronous operation unit is not reported at the same time.

CPU resource use processing independent interrupt factor,
Even when the asynchronous operation unit holds the CPU resource use process dependent interrupt factor at the same time, the CPU resource use process dependent interrupt is not prioritized and the interrupt factor remains pending, and the CPU resource use process independent interrupt occurs.

If the asynchronous CPU resource use process and the output resource of this process are not used in the environment saving part of the interrupt handler, this method is an effective interrupt method. However, when the basic CPU resource use processing used in the interrupt handler is made asynchronous, this interrupt method has the following problems.

After a certain interrupt (first interrupt) is generated, during the operation of the interrupt handler that processes the interrupt, the CPU resource use process dependent interrupt factor detected by the process started by the program executed before the interrupt occurred An interrupt (second interrupt) is generated. In the process for the second interrupt, it becomes impossible or very difficult to determine which program started the process that generated the interrupt factor. Therefore, in this case, the processing for the CPU resource use processing dependent interrupt detected in the CPU resource use processing used by the interrupt handler becomes impossible,
Or, the processing of the interrupt handler for this interrupt becomes very complicated. (3) A unit that operates asynchronously executes an asynchronous CPU resource use process that is started by an instruction and is executed asynchronously with the execution of the instruction. When the output of the asynchronous unit is used in the subsequent processing, there are two types: a case where a prescribed procedure is required and a case where the start of execution of an instruction for starting the subsequent processing is delayed.

When any interrupt factor is detected, C
The PU performs the following interrupt operation. Do not start executing new instructions. Processing being executed by the asynchronous operation unit (asynchronous CPU
The CPU waits until all the resource use processing) is completed. The asynchronous operation unit executes all the processes whose execution has started regardless of whether or not a CPU resource use process dependent interrupt factor has been detected in the preceding process. The CPU resource use processing dependent interrupt factor is detected, and the output having a value different from the expected value is also used as it is in the subsequent processing. In this case, the execution result of the subsequent process also becomes different from the expected result, and since the input does not have the expected value, the CPU resource use process dependent interrupt factor is also detected in this subsequent process. There is.

As a result of the operation of 2,
When more than one CPU resource use process-dependent interrupt factors are detected, the asynchronous operation unit performs an operation of holding the interrupt factor detected first or holding all the detected interrupt factors. .

In the case of holding all the detected interrupt factors, when a certain CPU resource use process dependent interrupt factor triggers and the CPU resource use process dependent interrupt factor in the subsequent process is generated, it is originally triggered. It becomes difficult to identify the interrupt factor that has occurred.

If no CPU resource use process dependent interrupt factor is detected, the CPU resource use process independent interrupt that started the interrupt operation is generated.
When a CPU resource use process dependent interrupt factor is detected, a CPU resource use process dependent interrupt occurs regardless of the type of the interrupt factor that started the interrupt operation.

In this interrupt processing method, the CPU resource use processing-dependent interrupt factor is detected, and the execution of the processing that uses the output of the processing whose output has the expected value as an input is not stopped. Therefore, when the input is abnormal, If you desynchronize a process that cannot specify the resource to be destroyed (for example, if the address used as an input is abnormal, such as a store in main memory, the unpredictable area is destroyed), it will be very difficult to debug the program. .

Further, in this interrupt method, the original program cannot be restarted when a CPU resource use process dependent interrupt factor is detected in the asynchronous process. First
Invention is a basic C as used by interrupt handlers.
An object of the present invention is to provide an interrupt processing method capable of asynchronously executing PU resource usage processing and easily creating an interrupt handler.

A second aspect of the invention is capable of asynchronously executing a basic CPU resource use process as used by an interrupt handler, and a corresponding interrupt handler for a necessary CPU resource use process dependent interrupt factor. The object of the present invention is to provide an interrupt processing method for enabling the original program to be restarted after the end of the processing.

[0018]

The features and advantages of the present invention are as follows. When either the CPU resource use process dependent interrupt or the CPU resource use process independent interrupt factor is detected, the interrupt operation is started. During the interrupt operation, all or part of the asynchronous CPU resource use processing being executed while guaranteeing the data dependency is terminated. The process that uses the output of the process in which the CPU resource use process dependent interrupt factor is detected as an input is terminated without being executed. At the end of this operation, the data dependency is deleted. When a CPU resource use process dependent interrupt factor is detected at the end of the interrupt operation, a CPU resource use process dependent interrupt is generated without depending on the type of the interrupt factor that started the interrupt operation. If not, a CPU resource use process independent interrupt is generated.

When a CPU resource use process dependent interrupt occurs, information on all detected CPU resource use process dependent interrupt factors and unexecuted processes is displayed. Enables the hardware to re-execute the processing for an interrupt factor that is expected to be resumed depending on the CPU resource use processing and the processing that has ended without being executed, after the processing of an appropriate interrupt handler and when returning to the original program Or display enough information for the interrupt handler to emulate the process.

According to the present invention, (1) processing for performing input from CPU resources such as registers, output to CPU resources, or both (CPU resource use processing) is synchronous CPU resource use processing and asynchronous CPU resource use processing. It is classified into two types and each is executed as follows.

The synchronous CPU resource use process is a process which is started by an instruction for instructing the process and executed in synchronization with the execution of the instruction. When the execution of the instruction is completed, the synchronous CPU resource use processing started by the instruction is completed.

The asynchronous CPU resource use processing is processing that is started by an instruction that specifies the processing and that is executed asynchronously with the execution of the instruction. After the execution of the instruction ends, the asynchronous CPU resource use processing started by the instruction ends. (2) When an asynchronous CPU resource use process (preceding process) that outputs to a CPU resource is started by an instruction, a CP that is started by an instruction issued after the instruction that started the corresponding process
When the output to the resource of the preceding process is used as an input in the U resource use process (subsequent process), the input of the resource in the subsequent process is delayed until the output to the corresponding resource in the preceding process is completed.

When outputting to a resource having CPU resource use processing (subsequent processing), access (input) to the resource by all CPU resource use processing (preceding processing) started prior to the corresponding processing. And the output) are completed, the subsequent process outputs to the corresponding resource.

When the succeeding process is the synchronous CPU resource use process, the execution end of the instruction designating the succeeding process is delayed until the access to the related resource in the preceding process is completed.
(The program counter remains pointing to the instruction that then begins line processing). When the succeeding process is an asynchronous CPU resource use process, the end of execution of the instruction for starting the succeeding process may be delayed until the related access to the corresponding resource of the preceding process is completed, or the succeeding process is executed. Although the execution of the instruction to be started is completed and the subsequent processing is started, the access to the corresponding resource in the subsequent processing may be delayed.

When the execution of the asynchronous CPU resource use processing is started, the output to the corresponding resource in the subsequent CPU resource use processing waits until the input is completed. (3) Part of synchronous CPU resource use processing and asynchronous CP
A part of the U resource use processing generates a CPU resource use processing dependent interrupt factor. The CPU resource use process dependent interrupt factor is an interrupt factor detected when a specific event occurs during execution of the CPU resource use process, and the output of the process in which the CPU resource use process dependent interrupt factor is detected is expected. It is an interrupt factor indicating that the result (the result that the output is expected to be used as the input in the subsequent processing) is not obtained.

When the output of the process in which the CPU resource use process dependent interrupt factor is detected is used as the input in the subsequent process, the execution result of the subsequent process also differs from the expected execution result.

(4) CPU in the CPU resource use process being executed
An interrupt factor (CPU resource use process independent interrupt) that occurs when a resource use process dependent interrupt factor is detected or does not directly depend on the execution result of the CPU resource use process that is being executed, such as an external interrupt When detected, the hardware performs the following interrupt operation.

(A) The hardware does not start execution of a new instruction, but the instruction being executed and the asynchronous CPU resource use processing which has already started are continuously executed.
Executable asynchronous CPU resource use processing ends and asynchronous C
Wait for the state of the PU resource use processing to stop changing.

(B) After waiting for the end of the CPU resource use processing in step (A), all asynchronous CPU resource use processing that was being executed at the start of the interrupt operation is performed by one of the following methods. finish.

The process was completed without detecting a non-CPU resource use process dependent interrupt factor. The output of the process was the expected output. Execution ended when a non-CPU resource use processing dependent interrupt factor was detected.

The non-asynchronous CPU resource use process uses the output of the preceding process to the resource, and when the preceding process detects the CPU resource use process dependent interrupt factor and does not output as expected, The CPU resource use asynchronous processing ends without being executed. The data dependency on the output of the processing that has not been executed is deleted.

The asynchronous CPU resource use processing that uses the output of the non-non-executed or non-executed processing as an input ends without being executed. The data dependency on the output of the processing that has not been executed is deleted.

When at least one non-CPU resource use process dependent interrupt factor is detected, even if the asynchronous CPU resource use process already started by the instruction has no data dependency relationship with this interrupt factor, it is not executed yet. You can end with.

The synchronous CPU resource use process is terminated by any one of the following methods at the end of execution of the instruction for starting the process. When the operation of (A) is completed, the synchronous CPU resource use processing that was being executed is also completed by any of these methods.

The processing is completed without detecting the CPU resource use processing dependent interrupt factor. The CPU resource use processing dependent interrupt factor is detected,
Execution of the process is completed.

When no CPU resource use process dependent interrupt factor is detected in (C) or (B): The interrupt factor that started the interrupt operation is a CPU resource use process independent interrupt factor. The hardware generates an interrupt corresponding to the interrupt factor that started the interrupt operation.

When one or more interrupt factors depending on the CPU resource use process are detected in (B): Regardless of the interrupt factor that started the interrupt operation, the non-to-non-synchronous CPU resource use process of (B) And all the information about the same CPU resource usage synchronous processing is notified to the program at the same time by one CPU resource usage processing dependent interrupt (composite CPU
Make resource-dependent interrupts). (5) It may be expected that the program that generated the interrupt factor will be restarted after the appropriate process is executed by some CPU resource use process-dependent interrupt factor processing program (the interrupt factor such as page fault) (here: This kind of CP
U resource use process dependent interrupt factor is called a restart expected CPU resource use process dependent interrupt factor), and when a CPU resource use process dependent interrupt factor occurs, only a restart expected CPU resource use process dependent interrupt factor exists as an interrupt factor , There is a possibility that the original program can be restarted after appropriate processing for all the restart expected CPU resource use processing dependent interrupts. When the CPU resource use processing dependent interrupt occurs, the restart expected CPU resource use processing dependent Processing that generated an interrupt and C that has not been executed
For each of the PU resource usage processing, one of the following is possible: When the CPU resource usage processing that returns to the interrupt source program is executed, the specified restart expected CPU resource usage processing-dependent interrupt factor is detected. Processing and the processing that has not been executed are re-executed, or the interrupt factor processing program displays information sufficient for simulating the process in the program at interrupt time, and the restart of the source program When it is necessary to save input data at the time of an interrupt due to a certain type of CPU resource use process dependent interrupt factor, when the interrupt factor occurs, the input resource of the process that generated that factor is Subsequent processing as an output destination is equipped with a restart expected CPU resource use processing interrupting unit that terminates all unexecuted. Accordingly, in the event of resuming the expected CPU resource using process dependent interruption factor to be resumed program that generated the interrupt factor.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the asynchronous separation / attachment method according to the present invention will be described in comparison with the case where it is not used. FIG. 1 shows the basic timing in the pipeline system that does not use the separation method, and FIG. 2 shows the timing when the separation method is used.

Each time section is a synchronization timing in a time section of 1τ. Symbols are used to describe the operation of each time zone, and the meaning of each symbol is shown below. D: Decode: Decode instruction and detect execution start condition (data dependency and resource collision) E: Execute: Execute operation, calculate execution address for main memory access instruction W: Write: Write execution result P1: Priority of load: Enqueue to asynchronous processing queue and detection of execution start condition (data dependency and resource collision) C: Cache: Address translation and reading data from cache W1: Write of load: Reading from cache (and main memory) Data writing to register Pf: Priority of floating point operation: Enqueue to asynchronous execution queue and detection of execution start condition (data dependency and resource collision) Ef1: Execute of floating point operation 1 Ef2: Execute of floating point operation 2 Ef3: Execute of floating point operation 3 Floating point addition and floating point multiplication In the pipeline that does not use the write / write cycle of the operation result of (1), in the case of register-register operation, pipeline processing is performed in the order of D, E, W, as shown in (1) of FIG. E
Bypass is allowed at the end of the cycle. If a load from the cache is required, a C cycle is required for address translation and reading data from the cache, allowing bypass at the end of this cycle.

In the case of floating-point arithmetic, the execution cycle of arithmetic is extended from 1τ to 3τ, and Ef1,
Ef2 and Ef3 are required. Bypass comes after Ef3.

On the other hand, the case of using the separation method as in the present invention is shown in FIG. 2, and the case is the same as the case where the separation method is not used, and the case of loading from the cache is as shown in At the end of the D cycle, there is a P1 interval, ie enqueue to the asynchronous queue and execution start conditions (data dependencies and resource collisions) are detected, after which the C cycle is entered. However, these operations can be performed by the separation method. Even in the case of floating point, the separation method is used to detect enqueue to the asynchronous execution queue and execution start condition data dependency and resource collision), and then the floating point operation cycle is performed. In addition, in the separation method, the parallel operation is carried out in the form separated from the synchronization processing, but the detailed timings of the synchronization and the asynchronous are shown in FIG. : Pipeline of instruction execution control unit and synchronous operation execution unit D-Wait, E-Wait, W-Wait Yes: Asynchronous processing: Main memory read pipeline (at cache hit), P-Wait Yes, C Until the cycle starts, it synchronizes with the E cycle of the instruction execution control unit (since the effective address is input in the C cycle as the output of the E cycle).

A timing diagram of a program for obtaining the sum of arrays by using such a separation method and a basic timing when the separation method is not used will be described using the example of FIG.

The program of FIG. 4 is the sum of the elements of the array A [0: 100] X = A

An example of calculation for obtaining [0] + A [1] + ... + A [100] is shown. The elements of the array shall be (Project 754) double-precision floating point numbers (8 bytes long) in the IEEE 754 format.

A time chart when the program of FIG. 4 is executed in the synchronous computer of FIG. 5 which does not use separation / attachment will be described. Program instruction numbers 1 to 10
Corresponds to the numbers shown on the left side of the time chart.

Each instruction from 1 to 4 can be realized by a pipeline according to the synchronous processing D, E, W. At number 5, the program goes into looping, but at the first instruction that goes inside the loop, the fifth instruction,
Since the cache is used, the basic cycle is D, E,
C and W. Floating point arithmetic addition is performed in the sixth instruction, and its operands are the execution result of the fourth instruction and the execution result of the fifth instruction. There is a data dependency here, and if these data are not available, floating point addition cannot be entered. Therefore, as shown by the number 6 in the time chart of FIG. 5, an instruction 7 which becomes D, D, Ef1, Ef2, Ef3, Wf after 1τ
In the above example, GR2 and GR3 are added, which does not use the floating point result of instruction 6 and has no data dependency with it, but in this example that does not use the separation method, As shown in, the basic timing becomes D, D, D, E, W with the D cycle extended by 2τ.

Below, the eighth compare and the ninth Branch
The instruction is pipelined at D, E, W, and when jumping to instruction 5 at instruction 9, the branch penalty delays by 1τ and D, E, W begins.

FIG. 6 shows a case where this operation is executed by using the computer separation / attachment method of the present invention. The numbers 1, 2, and 3 are the same as those in FIG. 5, but in the case where the cache of the instruction 5 is used, the cache operation is performed asynchronously, and the cycle of Pl CWl is performed separately as shown by 5. I have 5 non-C cycles underneath the W of 5,
It is executed at the same time. It will be faster than in the case of FIG. Also, the floating point operation of the instruction 6 is executed by using the two instructions 6 and 6 non, and after decoding, it is possible to proceed to the 6 non state by the separation method. As shown in the figure, the output of C of 5 non is the input of Ef 1 in 6 non. Then, it becomes the synchronous processing of the instruction 7, but this D
As for the cycle, the E cycle of the instruction 6, that is, the Pf cycle of 6 or more can be similarly performed.

Therefore, it is faster by 2τ than in the case where the separation method of FIG. 5 is not used. Therefore, the speed of using the separation / attachment shown in FIG. 5 is 3t faster than that of the non-use.

Instructions 8, 9 and 10 are the same as in the previous case. The invention relating to the resuming operation for interrupt of asynchronous processing and the data dependent accounting of the present invention is used on a computer using such a separation method.

Next, a first embodiment of the present invention will be described with reference to FIG. First, each component of FIG. 7 will be described. The instruction format is as follows, as shown in FIG. OPC:
Depending on the instruction code and the value of OPC, the positions of other fields in the instruction may be ignored. Further, it is assumed that whether the bits 17 to 31 of the instruction indicate GR or FR is determined by the value of OPC as follows. When the most significant bit of OPC is 0: Bits 17 to 31 of the instruction indicate GR. When the most significant bit of OPC is 1: Bits 17 to 31 of the instruction indicate FR. However, in the data transfer instruction between main memory and FR, OPC
The most significant bit of 0 is 0, but bits 17-26 are GRN
1, GRN2 and bits 27 to 31 indicate FRN3. At this time, GR1 + GR2 + IMM indicates the effective address, and FRN is the transfer source or transfer destination FR with respect to the main memory.
Is shown.

IMM: Immediate data (input) GRN1: GR Number 1. Input GR register number
Part 1 GRN2: GR Number 2. Input GR register number
Part 2 GRN3: GR Number 3. Output GR register number FRN1: FR Number 1. Input FR register number
Part 1 FRN2: FR Number 2. Input FR register number
Part 2 FRN3: FR Number 3. Output FR register number Synchronous processing and asynchronous processing types, interrupt types 2-1 Synchronous processing Branch processing, program call processing (processing that changes the execution order of instructions) SVC (supervisor call) processing Access CR (control register) Processing (excluding processing to change only CC of PSR) Processing to access asynchronous processing queue copy register 2-2 Asynchronous processing Arithmetic processing with long execution time Transfer processing between GR and main memory and between FR and main memory Transfer processing 2-3 Interrupt Program interrupt Indicates that the output of CPU resource use processing dependent interrupt and CPU resource use processing is different from the expected one. SVC (Supervisor Call) interrupt When executing the SVC instruction, This is an interrupt that is generated. Lower 7 bits of IMM part of SVC instruction + 0x8
A value of 0 is used as the call number. External Interrupt An external interrupt signal, which is an input signal from the outside to the CPU, is an interrupt factor. There are levels 0 to 15 in the external interrupt, and only the external interrupt signal of the level equal to or higher than the EAL of PSR is accepted and the interrupt operation is started.

CPU resources accessed by asynchronous processing In asynchronous processing, GR, FR and CC are included in the CPU resources.
Access only. The CR and asynchronous process queue copy registers are accessed only by synchronous processes.

Description of Each Hardware Unit 4-1 CPU Resource GR (General purpose Register): General-purpose register This is a general-purpose register used as an input / output destination of an operation and a base register and an index register for addressing main memory access.

One GR has a 32-bit length, and there are 32 GRs. Unique GR numbers 0 to 31 are assigned to each GR. GR0 always holds 0, writes to GR0 are ignored, and reading GR0 always reads 0. FR (Floating point Register): Floating point register A register used as an input / output destination for floating point arithmetic. One FR has a 64-bit length, and there are 32 FRs. Unique FR numbers 0 to 31 are assigned to each FR. FR0 always holds 0, writes to FR0 are ignored, and reading FR0 always reads 0. CR (Control Register): Control register This is a register that holds parameters for controlling the operation of the CPU. There are 32 CRs of 32 bit length.
The following parameters are assigned to CR0 to CR4. CR0: PSR (Processor Status Register) This is a register for holding the parameters (supervisor mode / user mode etc.) that define the main operating environment of the program. 2-bit length CC (Condition Co
de: Condition code area) and 4-bit EAL (Exte
rnal interruptAccept Level) exists. CC is
It is an output target in a specific process, and is used as an input for branch determination in the conditional branch process.

EAL defines the level of the external interrupt factor that is accepted. Only external interrupt signals with a value greater than EAL are accepted and the interrupt operation is started. CRI: OPSR (Old PSR) This is a register that holds the value of PSR before the interrupt occurs when the interrupt occurs.

CR2: OIC (Old Instruction Counte)
r) A register that holds the value of the PC before the interrupt occurs (points to the address of the next instruction to be executed) when the interrupt occurs.

CR3: OLEP (Old Last Entry Point)
er) This register holds the value of the final entry pointer of the asynchronous process execution queue after waiting for the end of asynchronous process when a program interrupt occurs.

CR4: INTD (INTerrupt Designatio)
n) This register holds the code (INTTYPE) indicating the interrupt type when an interrupt occurs and the end code (LSRETC) of the last synchronous processing executed when a program interrupt occurs in the format shown in FIG.

The following values are assigned to INTTYPE, for example. 0x00-0x0F: Reserved 0x10: Program interrupt 0x11-0x1F: Reserved 0x20-0x2F: Level 0-level 15 external interrupt, (L + 32) Indicates a level L external interrupt. 0x30 to 0x7F: Reserved 0x80 to 0xFF: Supervisor call interrupt of call number 0x80 to 0xFF, lower 7 bits of IMM value of SVC instruction + 0x80 value is supervisor It will be the calling number. CR5: INTB (INTerrupt Base Address) This register holds the base address of the address newly set in the IC (instruction counter) when an interrupt occurs. When an interrupt occurs, INTB + INTTYPE * 1
The value of 6 is set as the new value of the IC. CR6: NPSR (New PSR) This register holds the value newly set in PSR when an interrupt occurs. CR7 to CR31 Used as a register for holding parameters defining other program operating environment. Asynchronous Pro Copy Register (Asynchronous Pro
cess Copy Register) When a program interrupt occurs, the contents of the asynchronous process queue after waiting for the end of asynchronous operation are copied. There are 32 asynchronous process queue copy registers, each 64 bits long. However, APCR
O always holds 0. Each APCR has the following format.

When the RTN (ReturN) instruction is executed,
When OLEP is not 0, the contents of APCR1 to APCR (OLEP) are written to the asynchronous processing queue. 4-2 Instruction buffer The instruction to be executed is the same as the instruction buffer of a normal CPU.
It is fetched into this instruction buffer once. Reading instructions from the main memory to the instruction buffer is the same as a normal computer. 4-3 Instruction execution control unit This is a unit that executes instructions and controls interrupts.
It controls instruction fetch including branching, instruction decoding, process execution control, interrupt operation control, and interrupt operation. For the operation of the instruction execution control unit, see / 5 /.

The instruction execution control unit contains the following registers. IC (Instrcution Counter): instruction counter A counter that indicates the address of the next instruction to be executed. SRETC (Synchronous process RETurn code) This register holds the end code of synchronous processing. SVCC (SVC Code) This register holds the SVC code of the SVC instruction executed immediately before. 4-4 Synchronous process execution part This part executes synchronous process according to an instruction from the instruction execution control part. Depending on the execution result of the process, SRETC (Synchr
onous process RETurn code) is set. 4-5 Asynchronous processing queue This queue holds the asynchronous processing that is being executed and the asynchronous processing that is started by an instruction and is waiting to be executed. APQE1 ~ AP
There are 31 entries for QE31. Each entry has an instruction code, end code (RETC: 8-bit length), execution ID (EXID
: EXecutionID).

Entries in the range of APQE1 to APQE (SEP-1) are being executed. APQE (SEP) is the next entry to be executed. APQE (SEP + 1) to APQE (LEP) are entries that have been started by an instruction but are waiting to be executed.

APQE (LEP + 1) indicates the entry to be enqueued next. There are the following register interference detection mechanisms for the instruction buffer and the entry pointed to by the starting point pointer. In the register interference detection mechanism below, if the CR number in the instruction buffer is 0 or the GR number in the entry pointed to by the start point pointer is 0, it is determined that the area is not included in the area to be compared. To be done. Instruction buffer (IB) ・ Mechanism for determining whether IB.GRN1 is included in the GRN3 area of APQE1 to APQE (LEP) ・ Whether IB.GRN2 is included in the GRN3 area of APQE1 to APQE (LEP) IB.GRN3 is APQE1 to APQE (LEP) GRN1, GRN2 or GR
Judgment mechanism for whether or not it is included in N3 area ・ Judgment mechanism similar to the above three items when the instruction in IB is an instruction that specifies FR.・ APQE1 when IB.OPC is a process to change or refer to CC
~ APQE (LEP) includes a processing to change CC (OPC) whether or not it is judged. When IB.OPC does not access CC, it is judged that there is no CC interference. When any of these interferences exists, the value of the data interference signal line to the instruction execution control unit becomes 1. Entry pointed to by the start point pointer (Start Entry) S
A mechanism for determining whether E.GRN1 is included in the GRN3 region of APQE1 to APQE (SEP-1), ・ Whether SE.GRN2 is included in the GRN3 region of APQE1 to APQE (SEP-1). Judgment mechanism ・ SE.GRN3 is APQE1 to APQE (SEP-1) GRN1, GRN2 or
Mechanism for judging whether or not it is included in the GRN3 area, ・ Determining mechanism similar to the above three items even if the instruction in SE is an instruction that specifies FR ・ SEQ is APQE1 to APQE when processing is changing CC (SEP
-1) is a mechanism for determining whether or not CC processing (OPC) is included. If SE.OPC does not change CC, CC
It is determined that there is no interference.

Enqueuing and dequeuing to the asynchronous process queue are executed by the enqueue dequeue controller as follows. Enqueue When the instruction execution control unit detects that the instruction in the instruction buffer indicates asynchronous processing, the instruction execution control unit issues an enqueue request for asynchronous processing to the enqueue deque control unit. When LEP is less than 31, the enqueue dequeue controller adds 1 to LEP and copies the contents of the instruction buffer to the entry pointed to by the new value of LEP. The RETC and EXID of the corresponding entry are initialized to 0.

When LEP is 31, the asynchronous process queue is 1
Full and cannot enqueue new entries. At this time, the execution of the instruction is delayed until the queue entry is dequeued. When the process with an entry number smaller than the dequeue start point pointer (SEP) ends without a program interrupt factor, the asynchronous process execution control unit specifies EXID to instruct the enqueue dequeue control unit to dequeue the entry. The enqueue dequeue control block shifts all entries after the entry with the specified EXID to the previous entry, and SE
Decrease the values of P and LEP by 1. 4-6 Enqueue Dequeue Control Unit The enqueue dequeue control unit is a hardware unit that holds the start entry pointer (SEP) and the last entry pointer (LEP) and performs the next operation. The contents of the instruction buffer are enqueued at the end of the queue according to an instruction from the instruction execution control unit. When a program interrupt factor occurs, after waiting for the end of the asynchronous operation, the AP is instructed by the instruction execution control unit.
The contents of QE1 to APQE (LEP) are copied to APCR1 to APCR (LEP), and the value of LEP is copied to OLEP. Then LEP to 0,
Set SEP to 1. The EXID specified by the asynchronous process execution control block is written to the entry pointed to by SEP, and SEP is incremented by 1. Dequeue the entry with the EXID specified by the asynchronous process execution controller. Set the specified value to RETC of the entry with the specified EXID by the asynchronous process execution controller. 4-7 Asynchronous process execution control block The asynchronous process execution control block determines the start of the entry pointed to by SEP, controls the sending of the instruction code and EXID for the started process to the process execution unit, and the execution start of the process. Performs control at the end. For the operation of asynchronous process execution control block, refer to / 5 /.

The asynchronous process execution control unit is composed of the following two 31
Holds the bit length register. EXIDB (EXID Busy flag) This register consists of 31-bit flags EXIDB # 1 to EXIDB # 31, each of which is 1-bit long. EXIDB # (X) sets the value of X
Whether asynchronous processing with EXID is used,
Display as follows. 0: EXID of value X is not used. The value of 1: X is used as EXID. EXID the value of X
Asynchronous processing that has is in a state of either being executed or ended by detecting a program interrupt factor. EXIDR (EXID interRupt flag) This register consists of 31-bit flags EXIDR # 1 to EXIDR # 31 each having a 1-bit length. EXIDR # (X) sets the value of X
Displays whether or not the asynchronous processing that has EXID is detected by detecting the program interrupt factor and ended. A process having an EXID value of 0: X does not exist or is being executed. The processing that the value of 1: X has as EXID ends after detecting the program interrupt factor.

The asynchronous process execution control section inputs the next signal from the instruction execution control section, and when the signal is 1, performs the specified operation. Asynchronous process reset signal When this signal is input, the asynchronous process execution control unit performs the following operation at the specified timing. -Set EXIDB to 0. -Set EXIDB to 0.

Further, the asynchronous process execution control section sends the following two types of signals to the instruction execution control section. Asynchronous processing program interrupt signal This signal takes the logical OR value of all bits of EXIDR # 1 to EXIDR # 31. The following is displayed whether or not there is an asynchronous process that has ended by detecting a program interrupt factor. 0: There is no asynchronous processing that has ended by detecting a program interrupt factor. 1: There is an asynchronous process that ends after detecting a program interrupt factor. Asynchronous process stop signal This signal is 1 when there is no asynchronous process being executed and the asynchronous process execution control unit is in a state where it does not newly start the process in the asynchronous process queue. This signal becomes 1 under the following conditions.

(LEP is 0) or (EXIDB is not all 0 and EXIDB and EXIDR are equal) 4-8 Asynchronous process execution unit A unit group that executes a specific asynchronous process according to an instruction from the asynchronous process execution control unit. . The following operations are performed. An instruction code and ESID are sent from the asynchronous process execution control unit to start the process. At the end of the process, EXID and RETC are notified to the asynchronous process execution control unit.

Next, the operation for controlling instruction execution of the first embodiment will be described with reference to FIGS. First, in the figure, starting from [A], 4 bytes are read into the instruction buffer from the address indicated by the IC. Next, it is judged whether or not a program interrupt factor relating to instruction reading has occurred, and if YES, a value corresponding to the program interrupt factor generated in SRETC is output. If NO, the process moves to [B] when there is no factor for starting the interrupt operation. SRETC is not 0 as a factor for starting the interrupt operation. Asynchronous processing program interrupt signal is 1 SVCC is not 0. There is an external interrupt signal at a level greater than EAL. Is.

Next, when there is a factor for starting the interrupt operation, it is judged whether or not the OPC in the instruction buffer specifies asynchronous processing, and if YES, the OPC in the instruction buffer.
Specifies a process for which is not defined.

If this designation is NO, it is checked whether there is a data dependency relationship between the instruction in the instruction buffer and the entry before LEP in the asynchronous processing queue. If NO, the synchronous processing execution unit executes the processing. , The synchronous processing unit outputs the execution result to SRETC at the end of the process, sets SVCC in the SVC process, adds 4 to the IC when the executed process is not the process of changing the IC, and whether SRETC is 0 or not. Check if there is no program interrupt factor in the synchronous processing.

If YES, the process returns to the beginning. When specifying a process in which OPC in the instruction buffer is not defined, a code indicating an OPC abnormality is set in SRETC. When OPC in the instruction buffer does not specify asynchronous,
The enqueue dequeue control unit is instructed to enqueue the processing of the instruction buffer, and if the asynchronous processing queue is 1 byte, if NO, add 4 to IC and return to the beginning.

Next, as shown in FIG. 12, in the processing of [B], it is judged whether or not the asynchronous processing stop signal is 0, and YES.
If SRETC is not 0 or the asynchronous processing program interrupt signal is 1, it is determined whether SVCC is 0 if NO, and INTTYPE if NO.
Copy SVCC to E, set 0 to SVCC, OPS
R ← PSR, PSR ← NPSR (however, the value of EAL is unchanged).

When SVCC is 0, the existing external interrupt signal having the highest level is selected, and the selected level is set to L.
And And OPSR ← PSR, INTTYPE ←
L + 0 × 20, PSR ← NPSR (L is set to EAL), OIC ← IC, IC ← INTB + INTT
Return to [A] as YPE * 16.

When SRECC is not 0 or when SVCC is not 0 when the asynchronous processing program interrupt signal is 1, IC is decremented by 4 to set SVCC to 0. Then, the enqueue dequeue control unit is instructed to copy and initialize the asynchronous process queue to the asynchronous process queue copy register, and the enqueue dequeue control unit APQE # 1 to APQE # (LEP).
Is copied to APCR # 1 to APCE # (LEP). Also, LEP to OLEP
After copying, set LEP to 0 and SEP to 1. 1 is output to the asynchronous process reset signal for a certain period of time, and during this period, the asynchronous process execution control unit sets EXIDB and EXIDR to 0. Copy SRETC to LSRETC, and INTTYPE 0x10
To set.

Then, OPSR ← PSR, PSR ← NPSR where EAL
The value of is unchanged. Next, the operation of the asynchronous process execution controller will be described with reference to FIG. SEP <= LEP and EXIDR =
When it is 0, it is determined whether there is no data dependency between the instruction in the entry pointed to by SEP and the entry prior to SEP in the asynchronous processing queue, and the asynchronous processing unit executing the corresponding processing is in a state where it can start processing. If YES, EXID
Of B # 1 to EXIDB # 31, the lowest numbered flag holding 0 is recognized. This number X is assigned as the EXID of the entry pointed to by SEP.

EXIDB #X is set to 1. Add X as EXID to the contents of the entry pointed to by SEP and send it to the asynchronous process execution unit that executes the process. The corresponding asynchronous process execution unit starts the process.

X is added and the SEP change instruction is transmitted to the enqueue dequeue control unit. The enqueue dequeue controller sets X in the EXID of the entry pointed to by SEP, and then sets it in SEP.
Add 1.

Next, the EXID and RECT (end code) of the execution end process transmitted by each asynchronous process execution unit are accepted. Perform the following process for all the accepted EXID-X and RETC-Y pairs.

When Y is 0 (processing ends without a program interrupt factor), the EXID is sent to the enqueue dequeue control unit.
Directs dequeuing of entries with -X. The enqueue dequeue control unit moves the entry after the entry having EXID-X to the previous entry. Subtract 1 from the SEP and LEP values. Set EXIDB # (X) to 0.

When Y is not 0, the enqueue dequeue control unit is instructed to set RETC-Y to RETC of the entry having EXID-X. The enqueue dequeue controller does this. Set EXIDR # (X) to 1.

FIG. 14 shows a processing flow of the RTN instruction in [C] in the flow shown in FIG. LEP is 0 (SE
If P is 1, PSR ← OPSR, IC ← OIC are set, and the enqueue dequeue control unit is instructed to transfer the contents of the asynchronous queue copy register to the asynchronous processing queue. The enqueue dequeue control unit uses APCR # 1 to Change the contents of APCR # (OLEP) to APQE
After copying to # 1 to APQE # (OLEP), set LEP ← OLEP.
Then, at the end of the part [C], and if LEP is not 0, it is treated as NOP.

Next, the data dependency used in the present invention
A circuit for checking is described with reference to FIG. Figure
QB for all asynchronous queue entries at 15
#X Conflicts IB By ORing N1 signal, N in IB
It is possible to detect whether or not there is a data dependency relationship with respect to one area.

The same applies to the N2 area of the IB. For the N3 area of the IB, N1 of each queue entry
A comparison is made with all of the N2, N3 regions.

The following two types of methods can be considered for detecting the data dependency of the entry pointed to by the SBP (start entry pointer). (1) QB # X (queue entry #
X), and a detection circuit for detecting the data dependency between QB # X and QB # X1 to QB # (X-1) is provided for each QB. (2) Asynchronous process execution start buffer (APSB: Asynchro
Nous process Start Buffer) is provided and the entry pointed to by SEP is copied to this APSB buffer. A data dependency detection circuit as shown in FIG. 15 is provided between the APSB buffer and each QB.

In FIG. 15, IB is replaced with APSB. Also, LEP and its decoder are replaced with SEP and its decoder. The dependency relationship between the instruction buffer of FIG. 7 and the #th asynchronous queue entry of the 32 asynchronous queue entries is checked, and if there is a dependency relationship, QE
# Λ Conflicts IBN1 is set to 1.

The instruction that has entered the instruction buffer is the newest instruction, and the dependency relationship with the asynchronous instruction that has entered in the past will be examined. First, O of the instruction buffer
Decode and check the type of the PC. The instruction is GR
Are classified into those that specify and those that specify FR. N1, N2 and N3 shown in the instruction buffer are
GR N1, N2, N3 or FR N1, N2, N3
, Which are revealed by OPC decryption.

Whether it is GR or FR is the highest or lower of OPC, and O means GR and 1 means FR. The decoded output, eg IB N1 GRbyOPC, is OP
As a result of being decoded by C, it is a signal which becomes 1 when N1 is GR. The same applies to N2 and N3. Similarly, the OPC of the instruction in the asynchronous queue entry
It is possible to determine whether each field of N1, N2 and N3 is GR or FR by decoding
For example, QE # × N3 GR by OPC is a signal which becomes 1 when the × th asynchronous instruction in the asynchronous queue is the N3 field GR. The same applies hereinafter.

The N1 field in the instruction buffer 1B is decoded, all 0s are detected, and if not 0, 1B
N1 NOT 0 becomes 1. If the N1 area is 0, the specified instruction and the queued instruction and co
There is no nflicts (data dependency). When N1 is 0, the contents of GRO and FRO specified by N1 are 0.
Since it is fixed, there is no data dependency. Conversely, 1B
If N1 NOT 0 is 1, there is a possibility of conflict.

In AND1, the N1 area is GR, and N1
When the area of is not 0, 1 is output. Similarly, when the N1 region is FR and N1 is not 0, AND2
1 becomes 1 at the output of.

The same is done for N3. AND5 outputs 1 when the N3 area is GR and the N3 area is not 0.

In AND6, the N3 region is FR, and N3 is
When the area of is not 0, 1 is output. However, AND
AQE # X LEP Valid is input to both 5 and 6, which is a signal obtained by decoding the last entry pointer LEP of the queue, and the #Xth entry for which asynchronous processing has not yet been executed is more than the last entry pointer. , A signal that becomes 1 when there is no previous execution result. The outputs of the valid signals AND5 and AND6 are signals in which N3 is GR and there is a possibility of conflict.

AND3,4 determines if N1 is a GR in the instruction buffer and its content is non-zero, and also if that same GRN1 is the same GR indicated by N3 in the queuing. to see.

Whether N1 of OPC is GR and that GR is N3 of the queued instruction,
That is, GR in which N3 puts the result of asynchronous queue processing
Check if N3 in the instruction buffer is the same as N3 in the asynchronous queue.
E # X LEP Valid is input, and this is the signal obtained by decoding the last entry pointer LEP of the queue. The #Xth entry for which asynchronous processing has not yet been executed is before the last entry pointer. This signal is 1 when is not displayed. The outputs of the valid signals AND5 and AND6 are signals in which N3 is FR and there is a possibility of conflict.

AND3,4 determines if N1 is an FR in the instruction buffer and its content is not 0, and also if that same GRN1 is the same FR indicated by N3 in the queuing. to see.

Whether N1 of OPC is FR and that FR is N3 of the queued instruction,
That is, FR in which N3 puts the result of asynchronous queue processing
By ORing the outputs of AND3 and 4 for checking whether N3 of the instruction buffer is the same as N3 of the asynchronous queue, a signal indicating the presence / absence of the entire dependency is created.
However, the AND3 and 4 compare the contents of N3 of the asynchronous queue entry and the contents of N1 of the instruction buffer for 5 bits respectively, and if they match, a signal of 1 is taken. QE # 1N3eqn113N1 is input as a condition. That is, if N1 of the designated GR and N3 of GR of the asynchronous queue (N3 used as a result) match, there is a data dependency relationship.

The same applies to F1. If the F1 of the IB and the F3 of the queuing are the same, there is a data dependency relationship. Since there is one instruction buffer and 32 asynchronous queues, 32 circuits are the same as in FIG.

FIG. 16 shows a second embodiment of the present invention. The difference between the second embodiment and the first embodiment shown in FIG. 7 is that instead of using the asynchronous process queue copy register,
Add an asynchronous process freeze signal to the asynchronous process queue,
The contents of the asynchronous process queue are fixed. Further, this second embodiment is different from the first embodiment in that FEP, LEP,
The difference is that FXIDB and FXIDR can be accessed as CR, and the asynchronous process reset signal is an asynchronous process freeze signal.

FIG. 17 is a flow chart showing the operation of the instruction execution control section in the second embodiment, and corresponds to the flow chart of the first embodiment shown in FIG. First, following [B] in FIG. 11, it is determined whether the asynchronous process stop signal is 0, and if YES, SRETC is not 0,
Alternatively, it is determined whether the asynchronous processing program interrupt signal is 1, and if NO, it is determined whether SVCC is 0. When SVCC is not 0, copy SVCC to INTTYPE,
Set SVCC to 0, OPRS ← PSR, PSR ← NPSR However, EAL
The value of is unchanged, or 1 is set in PRS and FASP when there is an asynchronous processing program interrupt.

When SVCC is 0, the existing external interrupt signal having the highest level is selected. Let the selected level be L. OPSR ← PSR, INTTYPE ← L ＋ 0 × 20, PSR ← NPS
R, but set L to EAL, OIC ← IC, IC ← INTB ＋ INT
Return to A as TYPE * 16.

When SRETC is not 0, or SVCC is not 0 when the asynchronous processing program interrupt signal is 1, IC is decremented by 4 to set SVCC to 0. Next, it is judged whether the asynchronous processing program interrupt signal is 1, and when YES, the asynchronous processing freeze signal is set to 1 and SRETC is set to LSRE.
Copy to TC. Also, set INTTYPE to 0x10 and OP
SR ← PSR, PSR ← NPSR However, the EAL value is unchanged, and
If an asynchronous processing program interrupt exists, PSR,
FASP is set to 1. If the asynchronous processing program interrupt signal is not 1, set the asynchronous processing freeze signal to 1
And copy SRETC to LSRBTC.

FIG. 18 shows the processing flow of the RTN instruction shown in FIG. 11C according to the second embodiment, and corresponds to FIG. 14 of the first embodiment. LEP is 0
When (SEP is 1), PSR ← OPSR, IC ← OIC is set, and when LEP is not 0, it is treated as NOP, which is the end of the part [C].

[0104]

As described above, according to the present invention, the speed of asynchronous CPU resource use processing can be increased, and a basic CP used by an interrupt handler can be obtained.
It is possible to provide an interrupt processing method that enables asynchronous execution of U resource usage processing and that makes it easy to create an interrupt handler.
Furthermore, it is possible to asynchronously execute the basic CPU resource usage processing used by the interrupt handler, and the required CPU
For the resource use processing dependent interrupt factor, an interrupt processing method for enabling the original program to be restarted after the processing of the corresponding interrupt handler is completed becomes possible.

[Brief description of drawings]

FIG. 1 is a timing diagram showing a pipeline of a conventional computer.

FIG. 2 is a timing diagram showing a pipeline of a computer in which an asynchronous CPU resource processing is a target of the present invention.

FIG. 3 is a timing diagram showing synchronization between an instruction execution control unit and a main memory reading pipeline in FIG.

FIG. 4 is a diagram showing an example of a program.

5 is a timing diagram of the program of FIG. 4 in a conventional computer.

FIG. 6 is a timing diagram of the program of FIG. 4 in the computer of the present invention.

FIG. 7 is a hardware configuration diagram of the first embodiment of the present invention.

FIG. 8 is a diagram showing an instruction format.

FIG. 9 is a diagram showing an end code of a synchronization process.

FIG. 10 is a diagram showing a format of an asynchronous queue copy register.

FIG. 11 is a flowchart showing the operation of the instruction execution control unit in the first embodiment.

FIG. 12 is a flowchart showing the operation of the instruction execution control unit in the first embodiment.

FIG. 13 is a flowchart showing the operation of the asynchronous process execution control unit in the first embodiment.

FIG. 14 is a flowchart showing processing of an RTN instruction in the first embodiment.

FIG. 15 is a block diagram showing a hardware configuration for detecting data dependency.

FIG. 16 is a hardware configuration diagram of a second embodiment of the present invention.

FIG. 17 is a diagram showing a part of an instruction execution control unit in the second embodiment.

FIG. 18 is a flowchart showing the processing of an RTN instruction in the second embodiment.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP 62-163144 (JP, A) JP 51-854 (JP, A) JP 58-101346 (JP, A) JP 57- 162035 (JP, A)

Claims (22)

[Claims] 1. A queuing unit that determines whether an instruction stored in an instruction buffer is a synchronous process or an asynchronous process, and if the instruction is an asynchronous process, a queuing unit for queuing the instruction, and the queued instruction Data dependency checking means for checking data dependency by checking whether the register designated and the register designated by the input instruction are the same register, and synchronizing while checking the data dependency. An instruction processing device comprising: a control unit that performs asynchronous processing. 2. A queuing means for deciding whether an instruction stored in an instruction buffer is a synchronous processing or an asynchronous processing, and if the instruction is an asynchronous processing, a queuing means and a synchronous processing section or an asynchronous processing section. When an interrupt occurs or an interrupt from the outside of the CPU is detected, one or more queued asynchronous processes may end unprocessed or end with an exception,
At this time, it should consist of a means to display the contents of all unprocessed or exception-caused asynchronous processes and the termination method (unexecuted or exception type) in the program when an interrupt occurs so that the program before the interrupt occurred can be restarted. Interrupt handling method characterized by. 3. The interrupt processing method according to claim 2, wherein the displaying means includes means for saving the queuing contents in a register different from the queuing means. 4. The interrupt processing system according to claim 2, wherein the displaying means includes means for freezing (fixing) the contents of the queuing means. 5. A queuing means for deciding whether an instruction stored in an instruction buffer is a synchronous processing or an asynchronous processing, and if the instruction is an asynchronous processing, a queuing means for queuing the instruction, and a synchronous processing section or an asynchronous processing section. When an interrupt occurs or an interrupt from the outside of the CPU is detected, one or more queued asynchronous processes may end unprocessed or end with an exception,
At this time, in order to restart the program before the interrupt occurred, a method to display the contents of all asynchronous processing that has not processed or an exception and the termination method (type of unexecuted or exception) in the program when the interrupt occurred, and An interrupt processing method characterized by having a resuming control procedure for unprocessed and asynchronous processing that has ended by generating an exception as indicated at times. 6. A queuing unit for deciding whether an instruction stored in an instruction buffer is a synchronous process or an asynchronous process and queuing the instruction when the instruction is an asynchronous process, and the queued instruction Data dependency checking means for checking data dependency by checking whether the designated register and the register designated by the input instruction are the same register, a process in the asynchronous process queue, and By providing a means for checking the data dependency relationship with the process queued in the asynchronous process queue before the process, the process specified by the instruction is executed while maintaining the data dependency relationship of the input instruction sequence. If an interrupt occurs in the synchronous processing unit or the asynchronous processing unit, or if it is an external processor. If only one or more of the asynchronous processes that have been queued are unprocessed, they may end or end with an exception, so that the program before the interrupt occurred may be restarted. An interrupt processing method characterized by comprising an asynchronous processing queuing content storage means for displaying in a program the content and termination method (type of unexecuted or exception) of all asynchronous processing in which processing or exception has occurred. 7. The queuing means for queuing the instruction stored in the instruction buffer to determine whether the instruction is synchronous processing or asynchronous processing, and if the instruction is asynchronous processing, the queued instruction is Data dependency checking means for checking data dependency by checking whether the designated register and the register designated by the input instruction are the same register, a process in the asynchronous process queue, and By providing a means for checking the data dependency relationship with the process queued in the asynchronous process queue before the process, the process specified by the instruction is executed while maintaining the data dependency relationship of the input instruction sequence. If an interrupt occurs in the synchronous processing unit or the asynchronous processing unit, or if it is an external processor. If only one or more of the asynchronous processes that have been queued are unprocessed, they may end or end with an exception, so that the program before the interrupt occurred may be restarted. Asynchronous processing queuing content holding means that saves the contents and termination method (type of unexecuted or exception) of all asynchronous processing that generated processing or exception, and displays them in the program when an interrupt occurs; An interrupt processing method characterized by having a control procedure for resuming asynchronous processing that has occurred and ended. 8. (1) There are two types of processing (CPU resource use processing) for performing input from CPU resources such as registers, output to CPU resources, or both (synchronous CPU resource use processing). Each execution of the synchronous CPU resource use processing is started by an instruction that directs the processing, and is executed in synchronization with the execution of the instruction. At the end of the execution of the instruction, the synchronous CPU resource use processing started by the instruction is executed. End the use process, start the asynchronous CPU resource use process by an instruction that specifies the process, execute the process asynchronously with the execution of the command, and start the asynchronous CP by the command after the execution of the command
A synchronous instruction / asynchronous instruction processing means for terminating the U resource use processing, and (2) an asynchronous CP for outputting the CPU resource by the processing means.
When a U resource use process (preceding process) is started by an instruction, the output to the resource of the preceding process is used as an input in the CPU resource use process (subsequent process) started by an instruction issued after the command that started the process. When it is used, that is, when there is a data dependency, the input of the resource in the subsequent process is made to wait until the output to the resource in the preceding process is completed, and there is the CPU resource use process (subsequent process). When outputting to resources, all CPUs started prior to the processing
When access to the resource (both input and output) by the resource use process (preceding process) is completed, the subsequent process outputs to the resource, and when the subsequent process is the synchronous CPU resource use process Delays the end of execution of the instruction specifying the subsequent processing until the access to the related resource in the preceding processing is completed, that is, the program counter is kept pointing to the instruction to start the subsequent processing, and When the process is an asynchronous CPU resource use process, the end of execution of the instruction to start the subsequent process may be delayed until the related access to the resource of the previous process is completed, or the subsequent process is started. Although the execution of the instruction is completed and the subsequent processing is started, the access to the resource in the subsequent processing may be delayed. When the execution of the asynchronous CPU resource use processing is started, the subsequent processing is continued until the input is completed. CP A data dependency processing unit to wait an output to said resource in the resource use processing, (3) further when said processing means said CPU resource using process dependent interruption factor in CPU resource using process being executed is detected, Alternatively, an interrupt that occurs without directly depending on the execution result of the CPU resource use process during execution of an external interrupt or the like (C
When the interrupt source PU resource use process-independent interruption) is detected, (A) but does not begin execution of the new was Do instruction, the asynchronous CPU resource using process instructions and already running running is started Waiting means for instructing to wait until the state of the asynchronous CPU resource use process stops changing after the executable asynchronous CPU resource use process ends
If, (B) said After executing the wait for end of the CPU resource using process by state waiting means, prior to terminate all the asynchronous CPU resource using process was running at the beginning of the interrupt operation
Asynchronous CPU resource use processing termination means for instructing the processing means, and, in the case of synchronous CPU resource use processing , terminates at the end of execution of the instruction to start the processing, and instructs from the state waiting means.
An interrupt processing method comprising a synchronous CPU resource use processing ending means for ending the synchronous CPU resource use processing that was being executed when there was an error. (4) When it is detected that a part of the synchronous CPU resource use processing and a part of the asynchronous CPU resource use processing generate a CPU resource use processing dependent interrupt factor, the output of this processing is When used as input in line processing,
9. The interrupt processing system according to claim 8, further comprising CPU resource use processing dependent interrupt control means for making the execution result of the subsequent processing different from the expected execution result. 10. The CPU resource use process dependent interrupt factor is an interrupt factor detected when a specific event occurs during execution of the CPU resource use process.
A resource-use process-dependent interrupt factor is an interrupt factor that indicates that the output of the detected process is the expected result and that the output was not the result that was expected to be used as an input in the subsequent process. The interrupt processing method according to claim 9, 11. The interrupt processing method according to claim 8, wherein the asynchronous CPU resource use processing termination means completes without detecting a CPU resource use processing dependent interrupt factor, and the processing output is an expected output. 12. The interrupt processing method according to claim 8, wherein said asynchronous CPU resource use processing termination means detects a CPU resource use processing dependent interrupt factor and terminates execution. 13. The asynchronous CPU resource use process ending means is a process that uses output to a resource of a process preceding the asynchronous CPU resource use process, and the preceding process is a CPU.
When the resource use process dependent interrupt factor is detected and the expected output is not performed, the CPU resource use asynchronous process ends without being executed, and the data dependency relationship with respect to the output of the process that has ended without executing is deleted. The interrupt processing method according to claim 8. 14. The asynchronous CPU resource use processing ending means ends the asynchronous CPU resource use processing that uses the output of the processing that has not been executed in claim 13 as an input, and ends the processing without executing the asynchronous CPU resource use processing. 9. The interrupt processing method according to claim 8, wherein the data dependency on the output of the processed processing is deleted. 15. The asynchronous CPU resource use processing termination means, if at least one CPU resource use processing dependent interrupt cause is detected, the asynchronous CPU resource use processing already started by the instruction causes this interrupt cause. 9. The interrupt processing method according to claim 8, wherein even if there is no data dependency relationship with, the processing may be terminated without being executed. 16. The interrupt processing method according to claim 8, wherein the synchronous CPU termination means is completed without detecting a CPU resource use processing dependent interrupt factor. 17. The interrupt processing method according to claim 8, wherein said synchronous CPU termination means detects a CPU resource use processing dependent interrupt factor and terminates execution of processing. 18. (C) End of the asynchronous CPU resource use processing
Ryo when resources used process depends interrupt source when there is an end instruction from the means has not detected one: interrupt factor that initiated the interruption operation, Ri CPU resource using process-independent interruption factor der, interrupt generating means for generating an interrupt corresponding to the interrupt factor that initiated the interrupt operation, end instruction from the asynchronous CPU resource using process ending means
When one or more interrupt factors depending on the CPU resource use processing are detected when there is an error, regardless of the interrupt factor that started the interrupt operation, the CP
(3) It has an interrupt notifying means for simultaneously notifying the program of all the information related to the U resource use asynchronous processing and the CPU resource use synchronous processing by one CPU resource use processing dependent interrupt, and performs the composite CPU resource use processing dependent interrupt. By executing the interrupt operation of), after the interrupt occurs, the CPU resource use process dependent interrupt factor newly caused by the asynchronous CPU resource use process started by the program that was executing before the interrupt occurred is newly detected. Is guaranteed, and after an interrupt occurs, CP
It is guaranteed that all resources of U are released. (Because it is the output of the asynchronous CPU resource use process started before the interrupt occurred, the execution start of the CPU resource use process used as the CPU resource is sent. 9. The interrupt processing method according to claim 8, characterized in that it is guaranteed that nothing will happen. (5) Further, when a CPU resource use process dependent interrupt occurs, if only a restart expected CPU resource use process dependent interrupt factor depends as an interrupt factor, all the restart expected CPU resource uses that have occurred. There is a possibility that the original program can be restarted after the appropriate processing for the processing-dependent interrupt, and when the CPU resource usage processing-dependent interrupt occurs, the processing that generated the restart expected CPU resource usage processing-dependent interrupt and the CPU that has not finished executing When the CPU resource use process that returns to the interrupt source program is executed for each resource use process, the process that detects the specified restart expected CPU resource use process dependent interrupt factor and the process that has ended without execution are re-executed. The interrupt factor handler has enough information to simulate the process. Is displayed in the program at the time of an interrupt, and if the input data is required to be saved at the time of the interrupt due to some kind of CPU resource use process-dependent interrupt factor that is expected to restart the program that generated the factor, the interrupt When a factor occurs, the subsequent processes whose output destination is the input resource of the process that generated the factor are equipped with restart expected CPU resource use process interrupt means for ending all unexecuted processing. 9. The interrupt processing method according to claim 8, wherein when a processing-dependent interrupt factor is generated, the program in which the interrupt factor is generated can be restarted. 20. Some CPU resource use processing save interrupt factors may be expected to restart the program that generated the interrupt factors after execution of appropriate processing by the corresponding interrupt factor processing program, such as page absence. 20. The interrupt processing method according to claim 19, wherein the CPU resource use process dependent interrupt factor of this type is called a restart expected CPU resource use process dependent interrupt factor. 21. (1) A CPU resource use process for outputting a CPU resource such as a register to an input resource, or bidirectionally outputting the CPU resource is classified into two types: a synchronous CPU resource use process and an asynchronous CPU resource use process. , The synchronous CPU resource use processing is started by an instruction to instruct the processing, is executed in synchronization with the execution of the instruction, and at the end of the execution of the instruction, the synchronous CPU is started by the instruction.
The resource use processing has been completed. Asynchronous CPU resource use processing is started by an instruction that specifies the processing, executed asynchronously with the execution of the instruction, and asynchronously started by the instruction after the execution of the instruction is completed. CP
Synchronous instruction for terminating U resource use processing-processing of asynchronous instruction
Means, and (2) an asynchronous CP in which the processing means outputs to a CPU resource
When the U resource use process (predecessor process) is started by an instruction, the CPU resource use process (subsequent process) started by an instruction issued after the command that started the process outputs the resource to the preceding process resource. When using as an input, the resource input in the subsequent process is waited until the output to the corresponding resource in the preceding process is completed, and the output to the resource with the CPU resource use process (subsequent process) is performed. In this case, all CPs started before the corresponding process
When access (both input and output) to the relevant resource by U resource use processing (preceding processing) is completed, subsequent processing outputs to that resource, and subsequent processing is synchronous CPU resource use processing Delays the execution end of the instruction specifying the subsequent processing until the access to the related resource in the preceding processing is completed, and the program counter keeps pointing to the instruction to start the subsequent processing. Is an asynchronous CPU resource use process,
The end of execution of the instruction to start the subsequent processing may be delayed until the related access to the resource of the previous processing is completed, or the execution of the instruction to start the subsequent processing is completed and the subsequent processing is started. May delay the access to the corresponding resource in the subsequent processing, and when the execution of the asynchronous CPU resource use processing is started, until the execution is completed, the access to the corresponding resource in the subsequent CPU resource use processing is performed. Data dependency processing means for making output wait, (3) Part of synchronous CPU resource use processing, and asynchronous C
A part of the PU resource use process generates a CPU resource use process dependent interrupt factor, and the CPU resource use process dependent interrupt factor is an interrupt detected when a specific event occurs during execution of the CPU resource use process. Factor and CPU
A resource-use process-dependent interrupt factor is an interrupt factor that indicates that the output of the detected process is the expected result, and that the output is not the result that is expected to be used as an input in the subsequent process. When the output of the process in which the resource use process dependent interrupt factor is detected is used as the input in the subsequent process, the execution result of the subsequent process does not differ from the expected execution result. (4) CPU resource use during execution An interrupt (CPU resource use process independent interrupt) that occurs when a CPU resource use process dependent interrupt factor is detected in processing, or that does not directly depend on the execution result of the CPU resource use process being executed, such as an external interrupt when the interrupt source is detected, the hardware performs the following interruption operation, (a) but does not begin execution of the new was do instruction being executed instructions and already Row asynchronous CPU resource using process that has been started and run continuously, all executable asynchronously CP
Wait for status to instruct to wait until the state of asynchronous CPU resource use processing does not change after the U resource use processing ends
And (B) after waiting for the end of the CPU resource use processing by the state waiting means , all asynchronous CPU resource use processing that was being executed at the start of the interrupt operation is performed by one of the following methods. Ends and completes without detecting non-CPU resource use processing dependent interrupt factors. The output of the process is as expected output, execution ends when non-CPU resource use processing dependent interrupt factors are detected, and non-asynchronous CPU The resource use process is a process that uses the output to the resource of the preceding process, and the preceding process is the CPU
When the resource use process dependent interrupt factor is detected and the expected output is not performed, the CPU resource use asynchronous process is terminated without being executed, and the data dependency relationship with respect to the output of the process which is not executed is deleted. Asynchronous CPU resource use processing that uses the output of non-non-executed or non-executed processing as an input ends without being executed, and the data dependency on the output of the non-executed processing is deleted. If at least one CPU resource use process dependent interrupt factor is detected, even if the asynchronous CPU resource use process already started by the instruction has no data dependency relationship with this interrupt factor, it will be terminated without being executed. Previous
Asynchronous CPU resource use processing end instruction to instruct the processing means
In the case of a synchronous CPU resource use process , the synchronization that was being executed when the instruction for starting the process is terminated by one of the following methods and the operation (A) is terminated. The CPU resource use processing is also terminated by one of these methods, and is completed without detecting the CPU resource use processing dependent interrupt factor . When the CPU resource use processing dependent interrupt factor is detected, the processing execution is ended. End of synchronous CPU resource use processing
And no CPU resource use process dependent interrupt factor is detected in (C) and (B): The interrupt factor that started the interrupt operation is the CPU resource use process independent interrupt factor, and Is
Interrupt generation means for generating an interrupt corresponding to the interrupt factor that started the interrupt operation, and when one or more resource use process dependent interrupt factors are detected in (D) and (B) : Interrupt factor that started the interrupt operation Regardless of
(B) interrupt notifying means for notifying all of the information regarding the non-to-non-synchronous CPU resource use asynchronous processing and the same CPU resource use synchronous processing to the program simultaneously by one CPU resource use processing dependent interrupt ; By performing the interrupt operation of (4), after the interrupt occurs, the CPU resource use process dependent interrupt factor caused by the asynchronous CPU resource use process started by the program being executed before the interrupt is newly generated. Is guaranteed not to be detected in the
It is guaranteed that all resources of U are released (Because it is the output of the asynchronous CPU resource use process started before the interrupt occurred, the execution start of the CPU resource use process used as the CPU resource is sent. (5) Some CPU resource use processing-dependent interrupt factor processing programs may be expected to restart the program that generated the interrupt factor after executing appropriate processing ( Interrupt factors such as page absence) (Here, this type of CPU resource use process-dependent interrupt factor
U resource use process dependent interrupt factor), when a CPU resource use process dependent interrupt occurs, if only a restart expected CPU resource use process dependent interrupt factor exists as an interrupt factor, all restart expected CPU resources that have occurred There is a possibility that the original program can be restarted after the appropriate processing for the usage-dependent interrupt, and when the CPU resource usage-dependent interrupt occurs, the processing that generated the restart expected CPU resource usage-dependent interrupt and ended without execution For each CPU resource usage process,
If any of the following is possible: When the CPU resource usage process that returns to the interrupt source program is executed, the process that detected the specified restart expected CPU resource usage process dependent interrupt factor It is re-executed or the interrupt handler program has enough information in the interrupt program to simulate the process.
Certain C to a display means for displaying, resumption of factors originating program is expected
When it is necessary to save the input data at the time of the interrupt due to the PU resource use process dependent interrupt factor, when the interrupt factor occurs, the subsequent process with the input resource of the process that generated the factor as the output destination is In addition, it is possible to restart the program that generated the interrupt factor when the restart expected CPU resource use process interrupting unit is provided, which is a restart expected CPU resource use process interrupting unit that terminates all of the interrupt factors. A characteristic instruction processing device. 22. A synchronous C which is started at least by an instruction designating a process using resources of a central processing unit (CPU) such as a register and is executed in synchronization with the execution of the command.
There are a PU resource use process and an asynchronous CPU resource use process that is started by an instruction that specifies a process that uses a resource of the central processing unit (CPU) and that is executed asynchronously with the execution of the instruction. The synchronous CPU resource use process and the asynchronous CPU resource use process are controlled so that a data dependency relationship is maintained between the asynchronous CPU resource use process, and the synchronous CPU resource use process or the asynchronous CPU resource use process. The interrupt processing that occurs during the execution of processing is: an interrupt factor, such as a program interrupt, which depends on the resource use processing of the central processing unit (CPU), an input / output interrupt
When any of the above interrupt factors is detected in a data processing device in which an interrupt process is performed by an interrupt factor that does not depend on the resource use process of the central processing unit (CPU), at that time, the process is executed by the central processing unit (CPU). Above synchronous CPU
At the end of the instruction to instruct the resource use processing / asynchronous CPU resource use processing, the start of execution of the next instruction is suppressed, and while waiting for the end of execution of the plurality of asynchronous CPU resource use processing already being executed, Of the asynchronous CPU resource use processing
An end condition is stored, an interrupt factor dependent on the asynchronous CPU resource use is generated at the end of execution of all the asynchronous CPU resource use processes, and at the time of completion of the prepared interrupt process.
An interrupt processing method for restoring the hardware state of the central processing unit (CPU) based on the stored termination condition of the asynchronous CPU resource use processing.
Law .