JPH04175930A - Data processor - Google Patents

Abstract

PURPOSE:To process instructions at a high speed by providing a bypass means for setting outputs of plural computing elements in the input registers of the computing elements directly. CONSTITUTION:A processor 100 which executes two instructions in parallel consists principally of a register file 110, two computing elements 120 and 130, instruction registers 140, 141, 150, 151, 160, and 161, and an instruction buffer 180. The computing elements 120 and 130 are connected to A-side input registers 121 and 131 and B-side input registers 122 and 132, and selectors 124 and 125, and 134 and 135 are connected to the input ports of input registers 121 and 122, and 131 and 132 respectively. The selectors select the readout port of the register file and one of the outputs 126 and 136 of the two computing elements and input them to the input registers. Consequently, the instructions can be processed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device such as a microprocessor, and particularly to a processing method for simultaneous execution of multiple instructions in a parallel processing RISC processor.

[Conventional technology]

In the conventional device, as described in Japanese Patent Application Laid-Open No. 63-49843, the input of the input register of the arithmetic unit is connected only to the output port of the register file, and the output of the arithmetic unit is connected only to the output port specific to the arithmetic unit. was connected to.

[Problem to be solved by the invention]

In the above conventional example, the command is (1) read register.

When adopting a pipeline processing method that executes in three stages: (2) operation and (3) register write, the read register number of the instruction in the register read stage is the same as the write register number of the instruction in the operation stage. There is no consideration given to the case of coincidence, and there is a problem in that the execution result of an instruction in the arithmetic stage is not reflected in the operand data of a subsequent instruction, that is, an instruction in the register read stage.

An object of the present invention is to provide a means by which the execution result of an instruction in the calculation stage can be correctly reflected in the next instruction (that is, the instruction in the register read stage) even if the register numbers match as in the above case. It is about providing.

Another object of the present invention is to avoid inserting a delay cycle even if the register numbers match as in the above case.
The purpose of the present invention is to provide a means for correctly reflecting the execution result of an instruction in an arithmetic stage on the next instruction.

Still another object of the present invention is to process the execution results of multiple instructions in the arithmetic stage without inserting a delay cycle even if the register numbers match as in the above case.
The purpose is to provide a means that can correctly reflect the following commands.

[Means to solve the problem]

In order to achieve the above object, the input of the input register of the arithmetic unit is connected not only to the output port of the register file but also to the output of the arithmetic unit, so that data can be input selectively.

In addition, a means is provided to compare the read register field of the instruction in the register read stage and the write register field of the instruction in the arithmetic stage, and if they match, instead of reading from the register file, the register field of the corresponding arithmetic unit is read. A means is provided for directly setting the output to the input register of the arithmetic unit.

[Effect]

Among multiple (n) instructions executed in parallel.

It is assumed that the first instruction is operated by the first arithmetic unit.

In the first instruction (first instruction) among multiple instructions in the register read stage, the read register number of the first instruction matches any of the write register numbers of the n instructions in the calculation stage. If not, the contents of the corresponding register number are read from the register file and set in the input register of the first arithmetic unit. On the other hand, if it matches the write register number of the j-th instruction (second instruction) among the n instructions in the calculation stage, the j-th instruction is written instead of reading from the register file.
The operation result of the th arithmetic unit is directly set to the input register of the 1st arithmetic unit.

Thereby, the first instruction can correctly reflect the execution result of the second instruction, so that malfunctions will not occur.

In addition, when the write register numbers of multiple instructions in the calculation stage match, and if this register number also matches the read register number of the first instruction, the instruction with the matching register number Among them, the output of the arithmetic unit corresponding to the instruction that is originally supposed to be executed the slowest, that is, the instruction with the largest number (third instruction) is selected and stored in the input register file of the first arithmetic unit. Also, when writing to the register file, only the operation result of the third instruction is written, and the operation results of other instructions with the same write register number are written so that the execution result of the third instruction is valid. Prevent writing to the register file. As a result, the contents of the register file and the execution result of the third instruction are valid in the first instruction, and malfunctions do not occur.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a processor 10'O that executes two instructions in parallel, which is an embodiment of the present invention.

The processor 100 mainly includes a register file 110, two arithmetic units 120 and 130, and an instruction register 140, 141.
．． 150, 151, 160, 161. and an instruction buffer 180.

The register file 110 has 32 registers from RO to R31.
Consists of book registers.

Each of the arithmetic units 120 and 130 has A input registers 1
21, 131, and B bias input register number 2.132.

In addition, the input ports of the input registers 121, 122, 131゜132 have selectors 124, 125゜134.13.
5 is connected.

The selector 124 selects one of the read port 111 of the register file and the outputs 126° and 136 of the two arithmetic units.
Select one and input it to the input register 121.

The selector 125 selects one of the read port 112 of the register file and the outputs 126° and 136 of the two arithmetic units.
Select one and input it to the input register 122.

The selector 134 selects one of the read ports 113 of the register file and the outputs 126° 136 of the two arithmetic units.
Select one and input it to the input register 131.

The selector 135 selects one of the read port 114 of the register file and the outputs 126° 136 of the two arithmetic units.
Select one and input it to the input register 132.

Instruction registers 140, 150, and 160 are connected in series, and instructions at even addresses transferred from instruction buffer 180 are sequentially sent through instruction registers 140°L50 and 160.

The instruction registers 141, 151, and 161 are connected in series, and the instructions at odd addresses transferred from the instruction buffer 180 are sequentially sent through the instruction registers 141, 151, and 161.

The instruction buffer 180 temporarily stores instructions read from main memory or cache memory.

The instructions (for example, 140) handled by the processor of this embodiment are as follows:
It consists of four fields, the first field is the instruction (
○P code section (140a) indicating the type of operation), a first source section (140b) indicating the first source operand (A biased input of the operation unit), and a second source operand (B inputs of the operation unit) It consists of a second source section (140c) indicating the , and a destination section (140d) indicating the destination operand (output light of the arithmetic unit).

The processor of this embodiment divides the execution of instructions into three stages and processes them in a pipeline manner.

The three stages are (1) register read stage, (2) operation execution stage, and (3) register write stage.

The instruction registers 140 and 141 hold the instructions in the read stage of the above registers, and the instruction registers 150 and 1
Reference numeral 51 holds instructions in the arithmetic execution stage, and instruction registers 160 and 161 hold instructions in the write stage to the registers.

Below, the manner in which instructions are executed will be explained cycle by cycle.

In the first cycle, instructions read from memory are first transferred from instruction buffer 180 to instruction register 140 and
Transferred to 41.

The instructions set in the instruction registers 140 and 141 are:
Read the source operand from the register file 110, input register 121゜122.131,1 of the arithmetic unit
Set to 32.

Here, the read port 111 of the register file reads the contents of the register with the register number indicated in the first source part 140b of the instruction register 140, and the read port 112 of the register file reads the contents of the register with the register number indicated in the first source part 140b of the instruction register
Reads the contents of the register with the register number indicated in the source section 140c, and reads the register file read port 1.
13 reads the contents of the register with the register number indicated in the first source part 141b of the instruction register 141, and the read port 114 of the register file reads the contents of the register indicated by the first source part 141b of the instruction register 141.
The contents of the register with the register number indicated by the second source section 141C of No. 41 are read out.

In the second cycle, the instructions set in instruction registers 140 and 141 are transferred to instruction registers 150 and 151, respectively.

The instructions set in the instruction registers 150 and 151 are:
Arithmetic unit input register 121, 122゜131.132
The operand data set in the arithmetic units 120 and 13
The calculation is performed using 0, and the result of the calculation is stored in the register 123,
Set to 133.

Note that here, the arithmetic unit 120 inputs ○ in the instruction register 150.
Controlled by the output signal of the decoder 152 that decodes the P code section 150a, the arithmetic unit 130 is controlled by the instruction register 15.
It is controlled by a high power signal of the decoder 153 which decodes the 1 opco-1151a.

In the third cycle, the instructions set in instruction registers 150 and 151 are transferred to instruction registers 160 and 161, respectively. The instructions set in the instruction registers 160 and 161 are the execution results of the instructions (output register 1
23, 133) to the destination operand of the register file. Note that the write port 115 of the register file is the instruction register 160.
The write port 116 of the register file writes to the register number indicated by the destination section 161d of the instruction register 161.

Next, comparators 171, 172°17 which are a feature of the present invention
3.174, 175, 176.177.178 will be explained.

The comparator 171 is connected to the first source section 1 of the instruction register 140.
40b and the destination part 1 of the instruction register 151
51d, and if the register numbers match, the selector 124 is controlled and the output 13 of the arithmetic unit 130 is used instead of the read port 111 of the register file.
6 is selected and input to the input register 121.

The comparator 172 is connected to the first source section 1 of the instruction register 140.
40b and the destination part 1 of the instruction register 150
50d, and if the register numbers match, the selector 124 is controlled and the output 12 of the arithmetic unit 120 is used instead of the read port 111 of the register file.
6 is selected and input to the input register 121.

Note that when both the comparators 171 and 172 described above detect a match, control of the comparator 171 is given priority. Priority circuit 1
90 is a circuit for performing the above processing.

The comparator 173 is connected to the second source section 1 of the instruction register 140.
40c and the destination part 1 of the instruction register 151
51d, and if the register numbers match, the selector 125 is controlled to output the output 13 of the arithmetic unit 130 instead of the read port 112 of the register file.
6 is selected and input to the input register 122.

The comparator 174 is connected to the second source section 1 of the instruction register 140.
40c and the destination part 1 of the instruction register 150
50d, and if the register numbers match, the selector 125 is controlled to read the output 12 of the arithmetic unit 120 instead of the read port 112 of the register file.
6 is selected and input to the input register 122.

Note that when both the comparators 173 and 174 described above detect a match, control of the comparator 173 is given priority. Priority circuit 1
91 is a circuit for performing the above processing.

The comparator 175 is connected to the first source section 1 of the instruction register 141.
41b and the destination part 1 of the instruction register 151
51d, and if the register numbers match, the selector 134 is controlled to select the output 13 of the arithmetic unit 130 instead of the read port 113 of the register file.
6 is selected and input to the input register 131.

The comparator 176 is connected to the first source section 1 of the instruction register 141.
41b and the destination section 1 of the instruction register 150
50d, and if the register numbers match, the selector 134 is controlled to read the output 12 of the arithmetic unit 120 instead of the read port 113 of the register file.
6 is selected and input to the input register 131.

Note that if both of the comparators 175 and 176 detect a match, control of the comparator 175 is given priority. Priority circuit 1
92 is a circuit for performing the above processing.

The comparator 177 is connected to the second source section 1 of the instruction register 141.
41c and the destination part 1 of the instruction register 151
51d, and if the register numbers match, the selector 135 is controlled to read the output 13 of the arithmetic unit 130 instead of the read port 114 of the register file.
6 is selected and input to the input register 132.

The comparator 178 is connected to the second source section 1 of the instruction register 141.
41c and the destination part 1 of the instruction register 150
50d, and if the register numbers match, the selector 135 is controlled to read the output 12 of the arithmetic unit 120 instead of the read port 114 of the register file.
6 is selected and input to the input register 132.

Note that when both the comparators 177 and 178 described above detect a match, control of the comparator 177 is given priority. Priority circuit 1
93 is a circuit for performing the above processing.

In the register file 110 of this embodiment, data written to the registers consisting of the write ports 115 and 116 is reflected in the read ports 111, 112, 113, and 114 during reading in that cycle. In other words, the write boat 115 writes data to the R2 register, and the read port 111 writes data to the R2 register in the same cycle.
When the contents of register 2 are read, write port 1
The data written from 15 is correct and read from boat 1.
It can be read from 11. This can be achieved by creating a bypass path in the register file, but it is easier if you write to the register file in the first 1/2 cycle of one cycle and read the register file in the latter 172 cycles. According to the present embodiment, two instructions can be executed in parallel within the cycle time that conventionally required one instruction to be executed.

〔Effect of the invention〕

As explained above, according to the present invention, the bypass means for directly setting the outputs of a plurality of arithmetic units to the input registers of the arithmetic units is provided. In the pipeline processing processor as a stage, the operation result of the instruction in the operation execution stage can also be used for the operation execution in the next cycle, so that high-speed instruction processing is possible.

In addition, it has a means for comparing the read register number of the instruction in the register read stage and the write register number of the instruction in the operation execution stage, so if the register numbers match, the above-mentioned bypass means is used to Since the calculation result can be controlled to be set directly to the input register of the calculation unit, reading out old values in the register can be prevented.
Furthermore, high-speed execution of instructions becomes possible.

Furthermore, since it has bypass path priority determining means, even if the write register number and read register number of multiple instructions in the operation execution stage match, the latest operation output can be selected. Reading old values can be prevented, and furthermore, instructions can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing device that is an embodiment of the present invention. 124.125, 134, 135... Bypass input selector, 126, 136... Bypass path for arithmetic unit output, 171, 172, 173, 174, 175° 176
．． 177.178...Register number comparator, 190.
191, 192, 193... Bypass route %r Diagram 7

Claims (1)

[Claims] 1. A data processing device that executes a plurality of instructions in parallel, the data processing device comprising a register file and a plurality of arithmetic units, each of which has two input registers and one arithmetic unit. The input of the output register is connected to the output of the arithmetic unit, the output is connected to the input port of the register file, and the output of the input register is connected to the output of the arithmetic unit. The input register is connected to an input, the input is connected to an output port of the register file and an output of the plurality of arithmetic units, and has a selector means for selectively inputting data. data processing equipment. 2. The data processing device according to claim 1, wherein the instruction includes a read register field, a write register field, and an instruction code field, and the data processing device executes a plurality of instructions every cycle. The data processing device executes instructions in three stages: (1) register read, (2) operation, and (3) register write, and the processor executes instructions in the operation stage. It has means for comparing write register numbers of a plurality of instructions with read register numbers of a plurality of instructions in the register read stage, and it is detected by the comparison stage that the register numbers match. 2. A data processing device comprising means for controlling the output of the arithmetic unit to be directly input to the input register as claimed in claim 1, instead of reading the register file. 3. The data processing device according to claim 2, further comprising priority determining means connected to input control means from a plurality of arithmetic units for the same input register, and the priority determining means is connected to the input control means for the input register from the plurality of arithmetic units. When the read register number of an instruction in the read stage matches the write register number of a plurality of instructions in the calculation stage,
A data processing device characterized in that it is a control means for preferentially setting an input instruction from an arithmetic unit corresponding to an instruction indicating the latest operation result among the plurality of instructions into the input register.