JPH0419575B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to registers of a central processing unit in a computer system when the registers are referenced by the central processing unit and a vector processing unit connected to the central processing unit. Concerning methods for controlling references.

2. Description of the Related Art A parallel processing method based on a so-called pipeline method is used as a method for increasing the speed of a central processing unit (hereinafter referred to as a CPU) of a computer system.

In such a parallel processing method, there is a flow of multiple instruction executions at the same time, so there is a relationship between different instructions in which a scalar register updated by the execution of a certain instruction is referenced by another subsequent instruction. In this case, control is required to ensure that the temporal order of execution of these instructions is in accordance with the program (that is, in accordance with the instruction fetch order).

On the other hand, in systems that require even faster processing, a vector processing device (hereinafter referred to as VP), which is a dedicated processing device configured for high-speed calculation of vector data, may be used in combination.

As is well known, the VP is a processing device configured to mainly process operations on vector data stored in the main memory at high speed. However, in a configuration where it is used in conjunction with a CPU, the VP can be used as a general-purpose register and It is also necessary to refer to floating point registers and the like (hereinafter, these will be collectively referred to as scalar registers).

As a result, the above register reference order control is also necessary between instructions being executed by the CPU and processing in the VP, but since the processing in the VP is asynchronous with the pipeline of the CPU, ,
Its control requires special consideration.

[Conventional technology]

In one type of configuration that uses VP and CPU together, as shown in Fig. 2, VP1 and CPU2 are connected to each other, and each is connected to a main memory access control unit (hereinafter referred to as MCU) through an individual port. 3, the main memory (in the following,
4 (referred to as MSU).

The CPU 2 decodes the instruction taken out from the MSU 4 via the MCU 3, and if the instruction is a vector operation instruction, transfers necessary control information and data from the CPU 2 to the VP1 via the transfer line 6,
Request processing to.

VP1 accesses MSU4 by itself via MCU3 and proceeds with processing independently of CPU2, but
When outputting a processing result to, for example, a scalar register of the CPU 2, data, control signals, etc. are transferred to the CPU 2 via a transfer line 7.

Figure 3 shows the pipeline control of CPU2.
FIG. 2 is a block diagram illustrating control of addresses of scalar registers, etc.

Lines 10 at the top of the diagram indicate the stages of the pipeline, proceeding from left to right, and in a typical case of instruction execution, the D stage involves decoding of the instruction code.

In the A stage, the scalar register specified by the instruction is read from the register stack 23, inputted to the base register 11 and index register 12, and an address is calculated based on these and the contents 13 of the displacement part of the instruction. Get main memory address.

In the T stage, the main memory operand is accessed and the arithmetic unit is activated, in the B stage, data is read from the buffer, register stack 23, etc., and in the E stage, arithmetic operations are performed on the data prepared so far. The operation result is written to a predetermined scalar register or the like on the register stack 23 at the W stage.

In response to the control of each stage as described above,
A register that holds an address such as a scalar register used by an instruction at each stage is provided.

That is, the registers connected in series in the register groups 14, 15, and 16 indicate these registers, and the required values of registers A1 and A2 are set in the A stage according to the result of instruction decoding.

When the above settings are made, registers A1 and A
The contents of T2 are stored in registers T1 and T1 in the next control cycle.
It is shifted to T2. Also, in the case of another order,
At the T stage, addresses may be set in registers T1, T2, and T3.

The contents of registers T1, T2, T3 are shifted into registers B1, B2, B3 in the next control cycle.

Registers B2 and B3 are read out at the B stage and used as input registers 18 and 19 of the arithmetic unit 17, for example.
Used to specify a scalar register to be supplied as a register operand to.

The contents of registers B1 and B2 are shifted to registers E1 and E2 in the next cycle, and further shifted to registers W1 and W2 in the next cycle.

Register W1 is used in the W stage to specify the address of the scalar register to which data is written.

The register group 15 constitutes a write destination register instruction pipeline that specifies the scalar register to be written to, so in the D stage, registers A1, T1, B1, E1, W1 and the address specified by the instruction operand are Specifying the scalar register used for calculation (in the figure, 11, 1
2 and 13) are compared by a comparator 24.

As a result, if there is a matching address in even one register of both, the comparator 24
output 25 interlocks the instruction in the D stage and delays the instruction from proceeding beyond the D stage until the match signal at output 25 disappears.

Also, in the B stage, it is the write register address in the stage before it.
Registers E1, W1 and registers B2, B3 are compared by a comparator 20, and while the match output signal 21 is present, the progression from the B stage onward is interlocked.

As described above, the interlock control by the comparators 20 and 24 and the outputs 21 and 25 of their comparison results is used to eliminate the conflict between updating a scalar register and referencing the same register by a subsequent instruction. It constitutes a conflict resolution mechanism.

As is well known, while a stage of a pipeline is interlocked, instructions in that stage and in previous stages are prevented from proceeding to the next stage.

Similarly, the CPU 2 executes vector processing instructions by preprocessing them on the pipeline and executing them.
It prepares the necessary information by calculating addresses, reading data from required scalar registers, etc., and transfers the information and instruction code to VP1 for processing.

For these preprocessing steps, as shown in FIG. 4a, normally about four processing flows 30, 31, 32, and 33 are passed through the pipeline, and then the D stage of the next instruction starts from cycle 34. Begins.

Note that in the diagram, alphabetical characters indicate the names of each stage of the pipeline used in the above explanation, and time progresses from left to right in the diagram.

In the W stage cycle of processing flow 33 in the figure, the transfer of the necessary information from CPU2 to VP1 is completed, but if this vector processing instruction
If the scalar register in the register stack 23 of No. 2 is updated, when the processing of this vector processing instruction in VP1 is completed and the write data of the scalar register is complete (time 36).
Then, the output data is transferred from VP1 together with the write request signal, and the specified scalar register is updated.

Therefore, if an instruction subsequent to such a vector operation instruction references the scalar register to be updated, it is necessary to delay the reference until the update is completed.

Conventionally, for this purpose, when the CPU 2 detects that there is a vector operation instruction for updating a scalar register on the pipeline, it stores it and interlocks the subsequent instruction at the D stage.

This interlock must continue until the output from VP1 is written to the scalar register.

Process flow 37 in FIG. 4a shows the flow of subsequent instructions that are interlocked in this way, and line 39 shows the period of interlock.

[Problem that the invention seeks to solve]

According to the conventional method, when a VP updates a scalar register using relatively simple control,
It is possible to prevent subsequent instructions from referencing that scalar register before it is updated.

However, since all subsequent instructions are indiscriminately interlocked, even if the subsequent instructions do not refer to the registers listed above, their execution is delayed, resulting in a problem of unnecessarily lowering CPU performance. .

The present invention eliminates conflicts between updates of scalar registers by vector instructions and references by subsequent instructions.
The object of the present invention is to provide a register reference control method that can be realized efficiently and economically by reducing the time required to interlock instruction execution in a central processing unit as much as possible.

[Means for solving problems]

The above-mentioned problem is that the pipeline mechanism has a scalar register, executes instructions in parallel, and the pipeline mechanism includes a write destination register instruction pipeline that holds information indicating the write destination scalar register. , a conflict resolution mechanism that suppresses the reference until after the write is executed when the scalar register indicated by the information held on the write destination register instruction pipeline is referenced from a required stage in the pipeline mechanism; and a vector processing unit that independently executes vector operations according to the results of preprocessing of vector instructions by the central processing unit, in the final stage of the write destination register instruction pipeline. A VP write register is provided to receive and hold information to be held, and the output of the VP write register is connected to be added to the held information on the write destination register instruction pipeline processed by the contention resolution mechanism, and the central When a processing device executes preprocessing of the vector instruction using the pipeline mechanism, information indicating the scalar register to which the output of the vector processing by the vector instruction is to be written is transmitted by the write destination register instruction pipeline. This problem is solved by the register reference control method of the present invention, which is configured to set the output in the VP write register and hold it until the output of the vector processing is written.

[Effect]

That is, in addition to the register group that holds register addresses in the pipeline described above, at the end of the write destination register instruction pipeline, the register address of the scalar register that is updated by the execution of the vector operation instruction is held. do
Provide a VP write register.

In the CPU, when a vector operation instruction involves updating a scalar register, for example, the update destination register address is set in the VP write register in preprocessing.

In this way, in the control of general orders,
The address held in the VP write register is added to the conventional condition for detecting a match between an update register and a reference register, and only when a match is detected, a subsequent instruction is interlocked.

As described above, even in the case of a vector operation instruction that involves updating a scalar register, it is possible to reduce the number of interlocks to the necessary minimum without indiscriminately interlocking subsequent instructions.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 1 shows parts corresponding to the conventional configuration example shown in FIG. 3, and in the figure, the same components as in FIG. 3 are designated by the same reference numerals.

According to the present invention, a VP write register 40 is provided and connected to the final stage register W1 of the write destination register designation pipeline of the register group 15.

In the VP write register 40, in the preprocessing of a vector processing instruction, if the instruction is identified as an instruction that involves updating a scalar register,
It is assumed that the contents of the register W1 are set in the control cycle of the W stage of processing flow 33 (FIG. 4b), which is the last W stage.

The register address held in the VP write register 40 is input in addition to the conventional input to the comparator 20 and the comparator 24 that constitute the conflict resolution mechanism, and is compared with the register address of the scalar register referred to by the subsequent instruction. to be done.

If the comparison results in a match, the match output signal 2
1 or 25, the pipeline is interlocked at the D stage or B stage as in the case of conventional general instructions.

This interlock needs to continue until the register update by the output data from VP1 is completed.

However, in the above comparison, unless a register match is detected, the subsequent instruction will be executed without interlock.
You can proceed with the execution.

In FIG. 4 b and c, processing flows 30 to 3
3 is the same preprocessing flow of the vector processing instruction as in FIG. 4a, but at the W stage of processing flow 33.
A register address is set in the VP write register 40 and held until the write is completed, as shown by line 48.

Processing flows 41 to 46 are processing flows of subsequent instructions, and if there is no register reference conflict between instructions including vector processing instructions, each flow ends without delay as shown.

Processing flow 4 of the next instruction shown in FIG. 4b
In step 7, if an attempt is made to refer to the address register held by the VP write register 40 as a base register or index register for address calculation, it is interlocked at the D stage by the output 25 of the comparator 24. .

In addition, as in the case of the processing flow 47 shown in FIG. is interlocked with.

In those cases, this instruction is delayed from proceeding until VP1 has finished processing.

However, this delay is the minimum delay time necessary for program logic.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a computer system in which a CPU and a VP are connected, conflict resolution control when a register of the CPU is updated by the output of the VP is executed by the CPU. This has the remarkable effect of improving the performance of the CPU with an economical configuration, as it can be done economically and with a minimum of interlocks due to the common control between the instructions.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an example configuration of the present invention, Fig. 2 is a block diagram of an example configuration of a computer system, Fig. 3 is a block diagram of a conventional configuration example, and Fig. 4 is an explanatory diagram of a pipeline processing flow. It is. In the figure, 1 is VP, 2 is CPU, 3 is MCU,
4 is an MSU, 11 is a base register, 12 is an index register, 14, 15, 16 are register groups, 20, 24 are comparators, 23 is a register stack, 30 to 33, 41 to 47 are processing flows, 40
indicates the VP write register.

Claims (1)

[Claims] 1. A write destination register instruction pipeline that has a scalar register, executes instructions in parallel by a pipeline mechanism, and holds information indicating the write destination scalar register in the pipeline mechanism. and, when the scalar register indicated by the information held on the write destination register instruction pipeline is referenced from a required stage in the pipeline mechanism, conflict resolution is performed to suppress the reference until after the write is executed. In a computer system having a central processing unit having a central processing unit and a vector processing unit that independently executes vector operations according to a result of preprocessing of a vector instruction by the central processing unit, the final stage of the write destination register instruction pipeline A vector processing device write register is provided to receive and hold information held in the vector processing device write register, and the output of the vector processing device write register is added to the held information on the write destination register instruction pipeline processed by the conflict resolution mechanism. and when the central processing unit executes preprocessing of the vector instruction by the pipeline mechanism, information indicating the scalar register to which the output of the vector processing by the vector instruction is to be written is sent to the write destination register. 1. A register referencing method, characterized in that the register reference method is configured to set the output of the vector processing device in the write register of the vector processing device using an instruction pipeline and hold the output until the output of the vector processing is written.