JPS5896346A - Hierarchical arithmetic system - Google Patents

Abstract

PURPOSE:To solve a register conflict in its early stage and to improve a processing speed by reading stored input data immediately and using the arithmetic result of said data for the processing of succeeding instructions. CONSTITUTION:A pipeline type computer equipped with an operand buffer 20 for storing data until the starting of arithmetic execution by an arithmetic unit 14 has a preceding operating device 29 which performs arithmetic independently of the unit 14. Once decoded information on an instruction to be executed and operand data are stored in the buffer 20 without reference to whether the unit 14 is occupied or not, the data is read out immediately and inputted to the operating device 29 to perform arithmetic. Then, the arithmetic result is used for the processing of succeeding instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hierarchical arithmetic method, and particularly to a hierarchical arithmetic method that can speed up the advance control of instructions in a pipelined computer. , the calculation process is vertically divided into several stages, and many sets of data are passed simultaneously between them, so that the execution of one instruction, which normally takes many cycles, can be executed at a speed of one instruction/l cycle. It allows the flow of instructions to be processed.

In computers using this type of pipeline system, if the data required to process a certain instruction depends on the operation result of the preceding instruction, the pipeline processing must be interrupted until the operation result is determined. Therefore, performance decreases. For example, the absolute address in main memory is calculated by adding the pace address stored in the pace register and the address in the instruction, or by adding the address in the updatable index register and the address in the instruction. In methods that calculate absolute addresses in main memory, the contents of the pace register or index register used to calculate the operand address may be rewritten by an adjacent preceding instruction (
This is called an address conflict.)

Also, the addend value as the first operand of the addition instruction is stored in a specific general-purpose register (for example, one of 16), and the addition value is stored in the main memory indicated by the address specified by the second operand of the instruction. In a control system where operands are stored in a general-purpose register, the contents of a general-purpose register used for an operand may be overwritten by an adjacent preceding instruction (this is called an operand conflict). Address conflicts and operand conflicts are collectively called register conflicts.

When such a register conflict occurs, conventionally, among instructions that rewrite general-purpose registers (hereinafter referred to as modification instructions), instructions that perform relatively simple operations transfer the operation results to a dedicated circuit. (Hereafter referred to as the preceding arithmetic unit), the result of this operation is obtained early and used to process subsequent instructions that require it (hereinafter referred to as the request instruction), thereby minimizing performance degradation (Hitachi, general purpose (See Computer M-200H).

However, in the conventional method, when writing the operation result of an instruction to the result field of a general-purpose register, etc.

Instead of using the calculation result obtained by the preceding calculation unit, the calculation result obtained by performing the same calculation again in the calculation unit is written. Nevertheless, the same path is used to set up the input data to the preceding arithmetic unit and to set up the input data to the arithmetic unit. therefore.

If we assume that the setup of input data to the preceding arithmetic unit and the setup of the input data to the arithmetic unit are not performed at the same time, the setup of the input data to the preceding arithmetic unit and the setup of the input data to the arithmetic unit of a given instruction are different. There is a possibility that the instruction F.up of the input data to the arithmetic unit may conflict in the setup pass. Therefore, in order to avoid this conflict, for one instruction, the setup of the input data to the preceding arithmetic unit and the setup of the input data to the arithmetic unit are performed at the same time. However, if an arithmetic unit can process only one instruction at a time, input data cannot be set up until after the previous instruction is completed. Therefore, the preceding operation can only be performed after the immediately preceding instruction is completed.

In this way, in conventional methods, in order to avoid complicating pipeline control and increasing the size of the node, the data path to the preceding arithmetic unit and the data path to the arithmetic unit are shared. Therefore, the preceding operation can only be performed after the execution of the immediately preceding instruction has been completed.

On the other hand, the operand data itself required for the advance operation has generally already been read out by the advance control of the instruction performed in parallel with or before the execution of the operation of the immediately preceding instruction. Furthermore, the preceding arithmetic unit itself is not performing any operation during execution of the immediately preceding instruction. Therefore, in the conventional method, if the execution of the immediately preceding instruction takes a long time for some reason, even though the operand data of that instruction has already been read and the preceding arithmetic unit is empty, the Since the preceding operation is postponed until the execution of the instruction has been completed, the processing of the subsequent instruction that requires the result of the preceding operation of that instruction is further postponed.

The purpose of the present invention is to solve such conventional problems by: (1) resolving register conflicts early when register conflicts occur in pipelined computers and improving processing speed; The purpose of this invention is to provide a hierarchical calculation method that can perform the following tasks.

In order to achieve the above objects, the hierarchical arithmetic method of the present invention provides, in a pipelined computer, an input data buffer that stores instruction word decoding information and operand data until the start of arithmetic execution in an arithmetic unit; and a preceding arithmetic unit that obtains an arithmetic result independently of the arithmetic unit, and in order to execute the arithmetic operation of the preceding instruction, the instruction is stored in the input data buffer regardless of whether the arithmetic unit is occupied or not. Word decoding information and operands
When the data is stored, the data is immediately read from the input data buffer, the data is input to the preceding arithmetic unit to perform arithmetic operations, and the result of the arithmetic operation is used to process instructions subsequent to the above-mentioned instruction. There is.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a hierarchical arithmetic processing device showing an embodiment of the present invention.

In FIG. 1, the operation unit 14 and the preceding operation unit 29
In addition, a selector 11 reads out instruction decoding information and operand data independently in order to perform arithmetic processing in parallel.
, 12.2+, 25, buffer 32 for storing the result of the preceding operation. Selectors 38 to 41 that read out the calculation results at any time, and a conflict control circuit 13 that controls these selectors 38 to 41 are provided.

First, the instruction word read from the memory device 18 is set in the instruction register 1 and sent to the instruction decoder 3 for instruction decoding, and the signal line 2 is connected to the general register device for reading the address register. sent via. At the same time, address adder 5 for address calculation
It is also sent to the conflict control circuit 13 for address conflict detection. To instruction decoder 3? In this case, various information necessary for processing the instruction is generated by decoding the instruction word.

This decoding information includes information indicating whether or not pre-operation is possible, information indicating the S class of the operation if pre-operation is possible, the number of the general-purpose register to be changed, and the general-purpose register to be read as an operand. The decoding information is stored in the instruction queue 7 and the conflict control circuit 13 via the signal [6. In FIG. 1, the instruction queue 7 is provided three times, and each side stores decoding information for each instruction, and the three sides are used cyclically according to how many instructions are decoded. The decoding information of each instruction stored in each is sequentially sent to the selector 11.12 via line 16 8, 9°lO.

The selector 11 determines which of the decoding information stored in the instruction queue 7 is currently being integrated by the arithmetic unit 14.
Select the instruction that is generated from the instruction that should be executed next to the current instruction. In this case, the selection of the instruction queue 7 by the selector 11 is performed based on the value of the instruction queue output pointer sent from the profit control device 52 via the signal line 53, as in the conventional case. The value of this instruction queue output pointer is updated by 1 each time the contents of the instruction queue are set up in the arithmetic unit 14 (however, a method of adding l with modulo 5 is used).

In FIG. 1, among the decoding information selected by the selector 11 from the instruction queue 7, the general-purpose register number to be read as an operand is sent to the general-purpose register device 4 via the signal line 15. The general-purpose register number of the operand output from the selector 11 is determined at the time when the decoding information for that instruction exists in the instruction queue 7, the memory operand data has been read, and the operation execution of the immediately previous instruction has finished. Then, it is sent to the general-purpose register device f4 via the signal line 15, and the contents of the general-purpose register of the sent number are read out as an operand and sent to the arithmetic unit 14 via the Shingetsu line 16. . In the above explanation, the completion of the operation of the immediately preceding instruction means E, which is sent from the operation unit 14 via the signal line 59.
OP (End of Operaton) signal is “1”
This is determined by the following.

On the other hand, when the address register number is sent from the instruction register 1 to the general-purpose register device 14 via the signal line 2,
The contents of the general-purpose register specified by the address register number are sent from general-purpose register device 4 to address adder 5 via signal 1117. When the memory device 18 is accessed by the address determined by the address calculation, the memory operand is read out from the memory device 18 and sent to the operand buffer 2 via the signal line 19.
Stored at 0. Operand buffer 2o.

In FIG. 1, three planes are provided, each plane stores the operand of one instruction, and the three planes are used cyclically in accordance with the order in which the instructions are decoded.

In this case, the operand data stored in each side of the operand buffer 2o is sequentially transferred to the signal i121゜22.2.
3 to the selector 24.25.

The selector 24 selects the current operation item from among the operand data stored in the operand buffer 20.
At step 14, the instruction to be executed next to the instruction on which the operation is being executed is selected. In FIG. 1, each side of the operand buffer 2o and each side of the instruction queue 7 is 1
It corresponds to one-to-one, and the operand and
The selection of the buffer 20 is similar to the selection of the instruction queue 7 by the selector 11.
This is done using the value indicated by 3. Therefore, the operand data output from the selector 24 is sent to the arithmetic unit 14 via the signal line 26 in synchronization with the time when the decoding information is output from the selector 11.

The above is a description of the process of sending operands necessary for execution of an operation from the general-purpose register device 4 and the memory device 18 to the arithmetic unit 14, and these operations are conventionally performed, but the present invention will be described below. The operation of the newly provided logic circuit will be explained below.

The selector 12 selects the solution MfPt of the instruction to perform the preceding operation.
The general-purpose register number to be read out as an operand is sent to the general-purpose register device 4 via the signal line 27. The general-purpose register number selected by the selector 12 receives a signal (I
) becomes “1”K, and a signal indicating that the operand data required by the instruction has been read (described later
RDYE) becomes 1'', and the signal (
When EOPE (described later) becomes "1", the signal I! 2
7 to the general purpose register system. Note that at the time K when the above-mentioned signals IRDYE, 0RDYE, and EOPE all become "1", the signal BOPE indicating that the advance calculation has started becomes "1".

When a general-purpose register number is input to the general-purpose register device, the contents of the general-purpose register with that number are read out and sent to the preceding arithmetic unit 29 via the signal line 28. Selector 1
2, the instruction queue 7 is selected by the advance calculation control unit 5.
This is done by the value of the advance output pointer sent from 0 through the signal line 51. The value of this lookahead pointer is
When the input data for the preceding calculation is set up in the preceding calculation unit 29, it is updated by "1". That is, each time the above-mentioned BOPE signal becomes "1"K, it is updated by adding 1 modulo '3.

Next, the selector 25 selects, from among the operand data stored in the operand buffer 20, the one for the instruction to be subjected to the preliminary operation, and sends it to the preliminary operation result 9 via the signal line 30. Operand by selector 25
The selection of the buffer 20 is performed by the value indicated by the preceding output pointer 51, similar to the selection of the instruction queue 7 by the selector 12. Therefore, the operand data output from the selector 25 is sent to the preceding arithmetic unit 29 via the signal line 30 in synchronization with the time when the decoding information is output from the selector 12.

The preceding arithmetic unit 29 performs a preceding arithmetic operation, and forms a hierarchical structure with the arithmetic unit 14. The advance calculation of the advance calculation unit 29 is performed using the BOPE signal power ? sent from the advance calculation control device 50 via the signal line 54. 1''. At the end of the preceding calculation, the EOP signal is sent from the preceding calculation unit 29 to the preceding calculation control device 50 via the signal line 60.
The K signal becomes "1". This HOPB signal is also applied to the preceding calculation result buffer 32 and the conflict control circuit 13.
It is also sent to

In general, the preceding arithmetic unit 29 may be an arithmetic unit that can execute arithmetic operations for any instruction, but since its purpose is to obtain an arithmetic result faster than the processing of the arithmetic unit 14, the first In the figure, only relatively simple operations are executed at high speed. moreover.

In order to simplify control, it is desirable that the calculation in the preceding calculation unit 29 be completed within a certain period of time from the start of the calculation. In FIG. 1, it is assumed that the instructions operated in the advance @ calculator 29 include logical operation instructions, comparison instructions, addition/subtraction instructions, load instructions, etc., and these operations are completed within one machine cycle. Therefore, the signal BOPE indicating the start of the preceding calculation and the signal EOPE indicating the end are synchronized, and from now on, the BOPE signal will indicate both the start and the end of the preceding calculation.

The calculation result in the preceding calculation unit 29 is stored in the preceding & X result buffer 32 via the signal [31.

The preliminary calculation result buffer 32 has a function of storing the preliminary calculation results from the end of the preliminary calculation until the calculation unit 14 starts executing the calculation. The advance operation result buffer 32 has the same number of sides as the instruction queue 7, that is, three sides in FIG. 1, and corresponds one-to-one with each side of the instruction queue 7.

The calculation result of the preceding calculation unit 29 is sent to the EOPE signal 6°.The contents of each side of the preceding calculation result buffer 32 are sent to the signal line 35,
36, 37 via respective selectors 38, 39, 4
0,41. Selectors 38 and 39 select the preceding operation result stored in the preceding operation result buffer 32 when the result is required as an address register for a subsequent instruction. The selected preliminary calculation result is sent to the address adder δ via signal lines 42 and 43. For example, in Hitachi M series computers, there are two registers: index register and base register.
Since the type may be required, two selectors for address selection are provided.

Selectors 40.41 select the preceding operation result stored in the preceding operation result buffer 32 when the result is required as the contents of the general-purpose register of the operand of the subsequent instruction. The selected preliminary calculation result is sent to the preliminary calculation unit 29 via signal lines 44 and 45. For example, there are instructions such as the 1M series computer in which both operands are general-purpose registers.

Two selectors for operand selection are provided so that +C two preceding operation results can be simultaneously selected from the preceding operation result buffer 32.

Selection control of the selectors 38 to 41 is performed by the conflict control circuit 13, and the number of the preceding calculation result buffer 32 to be selected is w! It is sent to selectors 38-41 via L-order signal lines 46-49.

The conflict control circuit 13 detects an address conflict, and when an address conflict occurs, sends an ACONF signal to the instruction control device 52 via a signal 1158, and the DSQ signal indicating completion of decoding of the requested instruction is set to "1". '' and postpones the decoding and address calculation of the request instruction until the conflict is resolved. moreover.

In the processing of a request instruction, if a preliminary operation result is available, the selectors 38 to 41 are controlled by K to read out the necessary preliminary operation result from the preliminary operation result buffer 32. Therefore, the conflict control circuit 13 receives a signal DSQ indicating completion of instruction decoding via the signal line δ6, and also waits for an instruction in which decoding information is to be stored, that is, an instruction wait indicating the surface number of the matrix 7. A matrix input pointer IQIP (0-1) is input via the signal line 57, instruction decoding information is input via the signal line 6, and an EOPE signal indicating "end of preceding operation" is input via the signal line 60. Further, the preceding output pointer is inputted via the signal line 51.

The advance calculation control device 50 receives D8 from the instruction control device 52.
The Q signal is input via signal line 56, the instruction queue input pointer IQIP (0-1) is input via signal 1 [57, and operand data is still being read for each side of operand buffer 20. A signal 0BiFWAIT (1=O to 2) indicating a state of 5 when the signal is not set is inputted via the signal 1Ij55. - FIGS. 2 and 3 are explanatory diagrams of the operation of the advance calculation control device in FIG. 1.

Among the signals created by the advance calculation control device 50.

FIG. 2 shows the instruction queue 70 plane IK, and the IQiB8YE signal (
i=0 to 2), and FIG. 3 shows the BOPE signal indicating the start and end of the preceding calculation.

and the creation logic of the preceding output pointer IQOPELB (0 to 1), and FIGS. 21 and 3 show the signal lines 126 to 1.
28, 54.51 match A and B.

Connected at point 0.

First, #! In FIG. 2, the advance queue state setting circuit 100 has 7 lips and 70 teeth 101 to 103 (IQi
In order to control the setting of B8YEDD (1=0 to 2), the instruction decoding completion signal (nsq, 156
), instruction queue input pointer (IQIP(0-1)
) No. 1 line 57) is input, and the set signal (IQIBSYED) of the slip flops 101 to 103 is input as an output
D8 (1=0-2)) is output to signal lines 104-106. The decoding completion signal (line 56) and the instruction queue input pointer (line 57) are generated by the instruction controller 52 in the same manner as in the conventional system.

As shown in FIG. 2, the operation of the advance queue state setting circuit 100 is such that when the decoding completion signal (line 56) is "1", the instruction queue input pointer (line 57) is set to i=o, 1.
Depending on the combination of values of the clip flop 101
-103, any set signal line 104-106 is “
1″.

When one of the set signal lines 104 to 106 becomes "1",
The corresponding D (data) inputs of flip-flops 101 to 103 become "1", and OR gates 107 to 109
, the C (clock) input becomes "1" through its output signal lines 110 to 112, and the corresponding flip-flop is set to "1".

The advance queue state reset circuit 113 controls the reset of the flip-flops 101-103 by using the BOPE signal (1!54) indicating the start of advance operation.

Input the advance output pointer (line δ1) to reset the reset signal CI Q 1BS of the flip-flops 101 to 103.
The operation of the 1° advance queue state reset circuit 113 which outputs YEDDR (1=o~2)) on lines 114-116 is as follows.

As shown in Figure 2, the pre-operation start @ number (#54) is “
1'', the advance output pointer (IQOPELB)
By combining the values of t=0.1 of (line 51),
Reset signal of flip-flops 101 to 103 @(
IQiBSYEDDR) “l” for one of 114 to 116
Make it. One of the reset signal lines 114 to 116 is “l”
When it becomes K, if the corresponding D input of the flip flora 2101 to 103 is "0", the a buried phase game) 107 to 1
09. Since the C (clock) input becomes "1" through the output signals [110 to 112], the corresponding 7 lip-flops are reset to "O".

The output signals of flip-flops 101-103 are
As shown in the figure, seven lip-flops 117-119, 120-122, 123-12 are used for timing adjustment.
5 and the pre-queue status signal [126~
128.

Next, in FIG. 3, the advance queue status signal is the signal !
When input to the selector 129 via the status signal lines 126 to 128, the selector 129 selects these status signal lines 126 to 128.
Among them, the value of the signal line 51 indicated by the preceding output pointer is sent to the AND gate 133 via the signal line 132. A signal line 132 is an IRDYE signal indicating that decoding of the row 5 instruction of the primary preceding operation has been completed.

The selector 141 connects to an operand buffer weight signal line 55 (OBiFW) sent from the instruction control device 52.
AIT: Outputs the value of the signal $51 indicated by the preceding output pointer (IQOPELB (0 to 1)) from among i=o to 2) via the signal line 145 as the buffer weight signal (FWAIT). The meaning of the operand buffer wait signal (OBiFWAIT (1=0 to 2)) indicates the operand back state of surface number l.

In addition, the buffer wait signal (FWA
ITK) is inverted by the NOT circuit 146 and then sent to the AND gate 1 as the 0RDYE signal via the signal line 147.
33, and controls whether or not to suppress the advance operation start signal (BOPE). The result of the AND game 133 is sent to the advance output pointer control path 148 via the signal 1!54 as a advance operation start signal (BOPE).

The advance output pointer control circuit 148 controls the advance calculation start fF
r number (BOPE) (line 54), advance output pointer signal (IQOPELB (0 to 1)) (&51 > 4 is input, input signal (I
QOPEADIN(0~1))km No. m151゜15
Output to 2. The operation of the advance output pointer control circuit 148 is performed when the advance operation start signal (BOPE) (line 54) is "1".
When , the preceding output pointer signal (IQOPE
The value obtained by incrementing the value of LB (0 to 1) by 1 modulo 3 is output as a signal (IQOPEADIN (0 to 1)). The value of flip-flop 149°150 is
Clip flop 15 via signal lines 151 and 152
Sent on 3.15. flip flop 153,
154 is the preceding output pointer signal (IQOPELB(
0 to 1)) is output to the signal line 51.

FIG. 4 is an operation time chart showing an embodiment of the present invention.

In the 1pJ4 diagram, the 5 multiplication instruction M is in the arithmetic unit 14.
As an example, a case is taken in which processing of the subsequent addition instruction A is started while the calculation is being performed, and a load instruction that requires the result of the calculation as the contents of the address register is performed.

Processing of one instruction starts with reading the instruction word from the memory device, and can be divided into the following stages: decoding (decoding) the instruction word, reading operands, operation, and writing the operation result.

In FIG. 4, for each instruction M, A, and L, the processing from decoding the instruction word to performing the operation is shown.
, E, EOP, etc.

That is, in FIG. 4, the process from instruction word decoding to operation is roughly divided into four stages. The first stage is a stage for instruction word decoding and address calculation, and is called the D stage. The second stage is a stage in which the contents of the memory indicated by the address calculation result are read out as an operand, and this is called the A stage. The third stage inputs the operands to the arithmetic unit 14.
This is the stage where data etc. are set up, and this is called the L stage. The fourth stage is the calculation unit 1
This is the stage where calculations are performed using 4.

It is called the E stage. Note that a stage with parentheses added like (L) indicates a waiting state because it is desired to be set up in the arithmetic unit 14 but is occupied by the previous instruction, and the EOP is in a waiting state. Op@ra
This is an abbreviation for tion, and is the final E stage where the operation is completed and becomes vacant for the primary instruction.

All of these stages take one to several machine cycles for each instruction. In FIG. 4, one machine cycle is a scale T on the time axis.

to TO, and numbers from 1 to 10 are appended to each machine cycle for convenience.

Assume now that the E stage of multiplication instruction M requires machine cycles 1 to 5. It is also assumed that the D stage of addition instruction A starts from machine cycle 1. At this time, in machine cycle 1, the signal DSQ (outputted from the instruction control device 52 via the signal line 56) indicating the completion of the D stage of the addition instruction A becomes "1", and two cycles later, the instruction A status signal (IQI
BsYE) becomes "1" (assuming that the decoding information of the addition instruction is stored in surface 1). Signal (IQIBSY
E(t=o~2)) corresponds to each plane of the instruction queue 7, is set in synchronization with the signal (DSQ), and is reset in synchronization with the signal (BOPB) indicating the start of the preceding operation. This is a status signal indicating that the corresponding instruction has been decoded but no pre-operation has been performed. Assume that the advance output pointer points to plane 1 of the instruction queue 70.

A signal (IRDYE) indicating that the instruction has been decoded becomes "1". At this time, if reading of the memory operand is completed, the signal (ORDYE) becomes "1".

Also, if the preceding operation before the human command has finished here,
The signal (EOPE) becomes "1", and therefore the following condition is satisfied.

(IRDYE)△(ORDYE)△(EOPE)...
......(1) (△ indicates logical product) When condition (1) is satisfied, the preceding operation start signal (BOPE
) becomes “1” and a preliminary operation is performed.

At this time, the preceding output pointer (IQOPELB(0 to 1
) indicates the surface 1 where the addition instruction A is stored, so the preceding operation result of the addition instruction A is stored in the surface 1 of the preceding operation result buffer 32 accordingly.

On the other hand, in the primary load instruction, an address conflict occurs because the address register has the same number as the general-purpose register in which the operation result of the immediately preceding addition instruction A is stored.
This is detected by the conflict control circuit 13, and a signal (ACONF) indicating this becomes "1". When the address conflict signal (ACONF) is "1", the DSQ for the load instruction (signal indicating completion of addition instruction D stage) is "1" while this is "1".
'', the decoding of the load instruction is postponed.

In this way, the contents of the address register of the load instruction are obtained by the preceding operation of the add instruction A.

Around the end of machine cycle 3, this value is stored in surface 1 of advance calculation buffer 32, so this value is read out by selector 38 or 39 under the control of conflict control circuit 13 and sent via signal line 42 or 43. and sent to address adder 5.

Enables address calculation in machine cycle training.

Prior to this, the advance operation start @:jj (nopg) sets the address conflict signal (ACONF) to “0”, so the decoding of the postponed load instruction is restarted, and the DSQ (addition instruction D stage) is restarted. signal indicating completion)
becomes “1”.

With the above processing, the machine can decode the load instruction.
Completed in cycle 4, the computation stage ends up being completed in machine cycle 7.

On the other hand, according to the conventional method, the preceding operation of the addition instruction is performed at the same time as the last operation stage (EOP of machine cycle 5) of the immediately preceding multiplication instruction M.

Or after that, it will be performed in machine cycle 5 at the earliest. Therefore, even if the result of the preceding operation is used in the address calculation of the load instruction, the D stage of the load instruction will be executed in machine cycle 5. It becomes 6. In other words, in the present invention, the load instruction processing time is reduced by two cycles compared to the conventional method. this is,
This can be achieved by performing the advance operation of the addition instruction A at an early stage in the advance operation unit 29 without waiting for the completion of the operation stage of the immediately preceding instruction.

When the advance operation of addition instruction A is completed, the advance output pointer (IQOPELB (0-1)) is incremented by 1 with the convexity modulo.

Note that register conflicts occur with a probability of 20-30%, based on evaluations of system control programs. Although the present invention is not necessarily effective in all cases where such a register conflict occurs, as shown in the example of FIG. This is particularly effective when there is a simple operation (operation completed in about one cycle) such as addition instruction A next to the addition instruction A, and a register conflict occurs with the next instruction.

As explained above, according to the present invention, when a register conflict occurs in a computer using the Vibration method, the register conflict is resolved earlier, so that the processing speed of the computer can be improved. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a hierarchical arithmetic processing device showing an embodiment of the present invention, FIGS. 2 and 3 are schematic configuration diagrams of the preceding arithmetic and control device in FIG. 1, and FIG. 4 is an embodiment of the present invention. 3 is a time chart of instruction processing. 12: The instruction decoding information necessary for the advance operation is stored in the instruction queue 7
13: Conflict control U path;
25: Selector for selecting operand data necessary for the preceding operation from the operand buffer, 29: Advance operation unit, 32: Advance value calculation result buffer, 50 = Advance operation control device, 38 to 41 = In the advance operation result buffer a selector that reads data for subsequent instruction processing; 133 an AND gate that outputs a two-previous operation start signal (BOPE);
148=Advance output pointer control circuit. Patent Applicant: Hitachi, Ltd. Patent Attorney Masatoshi Isomura ← Figure 1 Figure 2

Claims (6)

[Claims] (1) In a pipelined computer equipped with an input data buffer that stores instruction decoding information and operand data until the arithmetic unit starts executing the arithmetic operation, the arithmetic operation is performed independently of the arithmetic unit. When the decoding information and operand data of an instruction to be executed are stored in the input data buffer, regardless of whether the arithmetic unit is occupied or not, the input data is immediately stored in the input data buffer. A hierarchical arithmetic system characterized in that data is read from a data buffer, the data is input to the preceding arithmetic unit to perform an arithmetic operation, and the result of the arithmetic operation is used to process instructions subsequent to the above-mentioned instruction. (2) When reading data from the input data buffer, a read circuit for sending data to the preceding arithmetic unit is provided separately from a read circuit for sending data to the arithmetic unit, and Claim 1 characterized in that data transmission to the unit and data transmission to the preceding arithmetic unit are performed without mutual interference.
Hierarchical calculation method described in section. (3) When performing an operation using the preceding arithmetic unit, the operation j! The operation result obtained by is stored in the preceding operation result buffer until the execution of the operation in the arithmetic unit starts, and the operation result stored in the preceding operation result buffer is extracted by a dedicated reading circuit and used for the subsequent instruction. A hierarchical calculation method according to claim 1 or 2, characterized in that it is used for processing. (4) The operation result of the preceding arithmetic unit is used in place of the contents of a general-purpose register necessary for calculating the operand address of a subsequent instruction. Hierarchical calculation method described in Section 3. (5) The arithmetic result of the preceding arithmetic unit is used in place of the contents of the general-purpose register operand of the subsequent instruction, as described in the first, second or third paragraphs of the patent. hierarchical calculation method. (6) The operation of the preceding arithmetic unit is limited to only instructions that complete the operation within a predetermined time, and once the operation according to the instruction is started, without looking at the judgment of the completion of the operation of the preceding arithmetic unit, Claims 1, 2, 3, and 4, characterized in that after the predetermined time, the preceding arithmetic unit is controlled to continue to calculate the next instruction. Hierarchical calculation method described in Section 5.