JP2558831B2 - Pipeline control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding pipeline control in a computer that processes instructions in a pipeline system, it is configured to generate a specific operation cycle when processing an instruction that does not require an operation to speed up the processing. For operating the pipeline more efficiently, when an instruction requiring no operation is input to the pipeline, a means for identifying whether the instruction immediately before the instruction and the instruction immediately after the instruction are arithmetic instructions And means for suppressing the occurrence of the specific operation cycle (V) when the instruction immediately before and the instruction immediately after the operation-free instruction are not operation instructions.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processing control device used as means for speeding up processing in an electronic computer system,
In particular, for load-related instructions that originally do not require arithmetic operations, the V cycle of another instruction processing flow is used as a V cycle.
The present invention relates to a pipeline processing control method capable of further speeding up processing by forcibly providing an arithmetic cycle that can be executed simultaneously with cycles other than cycles.

[Prior Art] Pipeline processing is widely used for the purpose of speeding up the processing of electronic computers. This divides the execution procedure of a given instruction into operations of each stage (stage) such as instruction decoding, address calculation, operand fetching, calculation, and result storage, and prepares a hardware mechanism to execute each stage. The execution unit of each stage passes the result to the next stage execution unit after the end of the stage operation, and executes the same stage for the next instruction. In this method, since a plurality of instructions are processed in parallel, the processing speed is improved.

On the other hand, the machine cycle of a computer is determined by the model, and whether or not each stage of instruction decoding, address calculation, etc. described above is executed in one machine cycle has a great influence on the pipeline processing speed. When all the stages are completed in one cycle, the pipeline is not disturbed and the processing can be performed in the shortest time, but in reality, there are many stages that require two or more machine cycles. A typical example is the operation execution stage in the operation instruction. Execution of an operation may require several cycles depending on its content.

As a means for eliminating the disturbance of the pipeline during execution of operation instructions and increasing the speed, it is possible to execute a specific cycle of multiple cycles that make up the operation stage at the same time as a cycle other than this specific cycle in the operation stage of another instruction. There is a way to. This operation cycle that can be executed simultaneously is provided by microcode as necessary, and is called a vanish cycle. Hereinafter, this is called a V cycle.

As shown in FIG. 5, an example of speeding up the processing when the operation stages are divided and the operation cycles that can be simultaneously executed, that is, the V cycles are provided, will be described. FIG.
Shows the case where the V cycle is not provided, and (b) shows the case where it is provided. The symbols D, A, T, B, E, W representing each stage are respectively D for instruction decoding (decoding), A for address calculation when reading data, T for checking whether data is in buffer storage or not. And a conversion from a logical address to a real address (translation), B is a buffer data read, E is an execution (execution), and W is a write stage for storing the result in a register or the like.

In FIG. 5 (a), the instructions I and II are the same kind of operation instructions and their minimum processing times are the same. However, the operation stage has two cycles, and the instruction I is processed in seven cycles of D, A, T, B, E, E and W. Instruction II should start its processing one cycle later than instruction I, and after the stage operation progresses in the order of D, A, T, B, originally it should move to the next E stage. Since the I stage is followed by the E stage, it is not possible to shift to the E stage and it is necessary to repeat the B stage again and wait. As a result, it takes 8 cycles to process the instruction II and the processing is delayed.

On the other hand, in FIG. 5 (b), the operation stage 2 cycle is divided into E and V cycles, and in order to make the V cycle a simultaneously executable operation cycle, the instruction II at the V cycle of the instruction I Execution of the operation stage can be started, waiting at the B stage is not necessary, and the instruction II ends in 7 cycles.

As described above, by providing an operation cycle that can be simultaneously executed in the operation instructions, that is, a V cycle, it is effective to speed up the process when the operation instructions are continuous. However, if a register is used in the middle of calculation, it is necessary to use a load-type instruction to set data in the register. Since this load instruction is generally processed in one cycle and does not require an arithmetic stage,
There is a problem that the above-mentioned V cycle cannot be generated, and as a result, the pipeline is disturbed, which hinders the speedup. An example thereof will be described with reference to FIG.

In FIG. 6, the operation stage of the operation instruction I extends over two cycles of E and V. With the next load instruction, there is no problem in processing each stage up to D, A, T, and B. The subsequent execution stage, that is, the load execution stage E can be executed in the section in which the V cycle of the instruction I is being executed, but the section of the next W stage overlaps with the W stage of the operation instruction I. So wait on the B stage, D, A, T, B, B,
The load instruction is processed in the order of E and W. Where D, A, T, B,
You can't wait at E like E, E, W. The reason is that when E, E and E operation are continued, E operation is ended by the processing end signal from the arithmetic unit,
This is because the load unit instruction does not activate the arithmetic unit, does not generate the processing end signal, and does not indicate the end point of the E operation.

The repetition of the B stage by the load instruction causes the subsequent arithmetic instruction processing to be delayed. That is, in the next operation instruction II, after processing each stage of D, A, and T in one cycle, it is necessary to wait in the T stage without immediately shifting to the B stage. Waiting on stage is required.

In order to solve such a problem, Japanese Patent Application No. 62-
According to No. 291813, when executing an instruction that does not require a calculation such as a load instruction, a V cycle is forcibly generated to smooth the flow of data on the pipeline and improve the processing speed. Is disclosed.

[Problems to be Solved by the Invention] A method for forcibly generating a V cycle when executing an instruction that does not require an operation as described above is to set a specific field in the microcode and set the content of the field. Is controlled depending on whether is "1" or "0".

Then, the value of this specific field was determined when the microcode was loaded into the processing device, and thereafter remained unchanged unless the microcode was changed.

Therefore, for example, in the microcode of the load instruction, V
If the cycle control field indicates "valid", the load instruction will generate V cycles each time it is executed.

In this method, when the load instruction exists in isolation while the operation instructions continue, as shown in FIG. 7 (a),
Since each stage of the pipeline moves smoothly in an orderly manner, high-speed processing can be expected without causing loss time.

However, looking at the case where there is no operation instruction before and after the load instruction, as shown in FIG. 7B, the loss time indicated by the letter L is generated. Then, in the instruction group in which the load instruction is inserted in this way, a loss time is generated by the number of load instructions.

In view of such a conventional problem, the present invention provides an instruction group that does not require another operation when a V cycle is forcibly generated by an instruction that does not require an operation, such as a load instruction. It is an object of the present invention to provide a pipeline control method that does not cause a loss time even if it exists.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention is
At the time of processing an arithmetic instruction, a specific arithmetic cycle (V) in an arithmetic execution stage consisting of a plurality of machine cycles other than a cycle (V) corresponding to the specific arithmetic cycle (V) in an arithmetic execution stage of another arithmetic instruction. Cycle (E)
In a pipeline-type computer which can be executed at the same time and is forced to generate the specific operation cycle (V) when the instruction to be processed is an instruction requiring no operation Means for identifying whether the instruction immediately before or after the instruction is an arithmetic instruction, and the instruction immediately before or after the instruction not requiring arithmetic operation is not an arithmetic instruction. At this time, the pipeline control system is provided with means for suppressing the occurrence of the specific operation cycle (V).

[Operation] FIG. 1 is a diagram for explaining the principle of the present invention.
1 (hereinafter, also referred to CS. Describes the CS in FIG.) Control storage 2 ₁ to 2 ₅ represents the transition of the V-cycle control field microcode.

While migrating as V cycle control field 2 ₁ 2 _{2-2 5} sequentially to each stage A~E read by CS1 from the decoding (D) stage as shown in the figure, the value is "1" Sometimes V cycles occur.

In the above-mentioned means according to the present invention, when an operation-free instruction such as a load instruction is input to the pipeline, when an instruction immediately before and after the instruction is looked at and the instruction is an operation-free instruction, The value of the V cycle control field of the microcode is forcedly set to "0" by, for example, hardware to prevent the V cycle from being generated.

As a result, as shown in the time chart of FIG. 2, instructions that do not require computation occur continuously, and, for example, a load instruction exists between instructions that do not require computation. Can be prevented.

[Embodiment] FIG. 3 is a block diagram of an embodiment of the present invention.

The figure is roughly divided into three parts (units). That is, they decode the instruction, calculate the operand address and issue a request, the instruction control unit 8 and the request from the instruction control unit 8 and the address information, and the buffer control unit 10 that reads the data and the data. It is a calculation unit 9 that performs calculation.

In the figure, 5 is a control for storing microcode read from the operation code of the instruction.
Storages (CS), 11 to 14 are registers of each state for holding the code read from CS5.

Reference numeral 15 is a register indicating a load instruction, which is set by CS or the operation code of the instruction. On the other hand, 6 is a detection circuit for detecting the relationship between the load instruction and the instruction immediately before it, 7
Indicates a pipeline control unit that receives the V cycle control field and controls the state of the pipeline, 3 indicates an interface unit with the arithmetic unit, and 4 indicates an interface unit with the buffer control unit. Operation of Embodiment 4 Below
This will be described with reference to the time chart in the figure.

In FIG. 4 (a), the V cycle control field of the operation instruction A is read from CS and the registers 11, 12, 13 of each state are read.
While the next load instruction is input to the pipeline, the field read from CS is also propagated to the register.

The outputs of the register 12, the register 11, and the register 15 enter the detection circuit 6 at the timing of the T state of the arithmetic instruction, that is, the A state of the load instruction. In the detection circuit 6, the register 12 is on and the register 11 is on and
If 15 is on (load instruction), a select signal for setting the register 12 is issued. This signal propagates the value from register 11 to register 12. If the register 12 is off (that is, not an operation instruction) at this timing, the value from the register 11 is not propagated without selecting the register 12. Then, when the register 12 is turned off, the processing does not generate the V state and becomes a normal operation as shown in the time chart of FIG. 4 (b). Whether or not to generate the V state is controlled so that the output from the register 12 and subsequent registers is sent to the pipeline control unit 7 so that the V state is generated when it is on and the V state is not generated when it is off. At the same time, E-unit 9
Since the interface of the S-unit 10 and the S-unit 10 must be synchronized with the state of the pipeline, these processes are performed by the interface units 3 and 4.

According to this method, the V instruction is in the V state when it is read from CS, but whether or not the V state is generated depends on whether the immediately preceding instruction is the operation instruction or the operation unnecessary instruction. Can be set to.

[Effects of the Invention] As described above, according to the present invention, in a computer that processes an instruction in a pipeline system, when an operation-free instruction such as a load instruction is interposed between operation instructions to be connected, the processing is performed. In the pipeline control method, in which the disturbance of the pipeline is eliminated and the processing speed is increased by forcibly generating the operation cycle (V cycle) that can be executed simultaneously during the flow, the load instruction is executed between the instructions that do not require the operation. Since it is possible to suppress the occurrence of V cycles when there are instructions that do not require arithmetic operations, such as when V cycles are generated, it is possible to further improve the processing efficiency of the pipeline. There is.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a time chart for explaining the principle of the present invention, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. FIG. 5 is a time chart showing an example of the operation of the example, FIG. 5 is a diagram explaining an example of providing a conventional V cycle to speed up the process, and FIG.
FIG. 7 is a diagram for explaining the processing delay when there is a load instruction among consecutive operation instructions, and FIG. 7 shows a loss time when there is a load instruction in an operation unnecessary instruction when V cycle is forcibly generated. It is a figure explaining that it produces. 1,5 ...... control storage 2 ₁ to 2 ₅ transition ...... V cycle control field, 3, 4 ......
Interface part, 6 ... Detection circuit, 7 ... Pipeline control part, 8 ... Instruction control part, 9 ... Arithmetic part, 10 ... Buffer control part, 11-15 ... Register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Mizushima 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Tetsuya Hagiwara, 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Satoshi Sugiura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yuta Shinoda, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor, Nakata Tatsumi, Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited (56) References JP-A-57-10872 (JP, A) JP-A-58-182758 (JP, A)

Claims (1)

(57) [Claims] 1. When processing an arithmetic instruction, a certain specific arithmetic cycle (V) in an arithmetic execution stage consisting of a plurality of machine cycles corresponds to the specific arithmetic cycle (V) in an arithmetic execution stage of another arithmetic instruction. It is possible to execute at the same time as the cycle (E) other than the cycle (V) to be executed and to forcefully generate the specific operation cycle (V) when the instruction to be processed is an instruction requiring no operation. In a pipeline type computer, when an instruction requiring no operation is input to the pipeline, means for identifying whether the instruction immediately before the instruction and the instruction immediately after the instruction are arithmetic instructions, And a means for suppressing the occurrence of the specific operation cycle (V) when the immediately preceding instruction and the immediately following instruction are not operation instructions.