JPS60178580A - Instruction control system - Google Patents

Abstract

PURPOSE:To improve the parallelism of execution processing between the 1st and the 2nd instructions when the processing speed of the leading instruction is slower than that of the following instruction by starting executing the 2nd instruction before the start of the processing of at least the final operand data in the execution of the 1st instruction. CONSTITUTION:A vector instruction from a main storage device is set in a D register 11 for instruction fetch. This instruction is decoded by a decoder 12 and set in a Q register 13 for queuing. An instruction transmission control circuit 14 transfers instruction information in the Q register 13 to a free inexecution instruction control part 15-1 or 15-2. In this case, if the leading vector instruction requires a longer processing time than the following vector instruction, the start of the execution of the following instruction is hastened to before the execution completion of the leading instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for controlling the execution start timing of a subsequent instruction in a vector processing device when the processing result of a preceding instruction is used as an input operand of the subsequent instruction.

(Background of BL technology A vector processing device processes a second operand A−aO+ al
+ ``' + al + ''・+ arI-1 and the third operand B-bO9b1. having a plurality of unit data.
..., bI, ..., bn-1, and calculate the first operand C=c(
The basic function is to obtain Lcl+...+cL...ICI)I. For example, vector operation C=A
+B is composed of unit data calculation ci=ai+bi repeated n times.

Such operations are performed in the vector processing device as execution of vector instructions. A vector instruction generally has an instruction code, a first operand specification section, a second operand specification section, and a third operand specification section, such as rVM
1, 2.3J is vector register 2 and vector register
This is a vector multiplication instruction that specifies that the result of multiplying the contents of register 3 is to be stored in vector register 1.

(C1 Prior Art and Problems FIG. 1 is a diagram showing an example of a vector processing device. A vector processing device 200 is connected to a main memory device l via a main memory control device 2, and processes data on the main memory device. However, the data to be processed is transferred in blocks between the main storage device 1 and the vector register storage device 40, and the direct target of the operation is the data in the storage device 4.This data transfer is performed by the load processing unit 7 and the vector register storage device 40. It is processed in the store processing section 8.

The operation is processed by the adder 9 and the multiplier/divider lO of the arithmetic processing section 6. The command control section 5 controls each of the above sections.

In order to execute vector instructions at high speed, a load processing unit 7,
The store processing unit 8, adder 9, multiplier/divider IO, etc. can operate in parallel, and a plurality of instructions are executed in parallel by a so-called pipeline control method. In such a vector processing device, if there is a subsequent instruction that uses its execution result as an input operand (this situation is called register interference), the start of the i & consequent instruction will start at the same time as the execution of the preceding instruction. Special considerations are required to synchronize the state. An improved system for controlling the start of subsequent commands in such cases is disclosed in Japanese Patent Application Laid-Open No. 57-206982 "Instruction Control System", a patent application published by the same applicant.

FIG. 2 shows the timing when executing the multiplication instruction VM and addition instruction VA by applying the present invention.

In the figure, IF is instruction fetch, D is instruction decode,
Q indicates waiting, and E indicates each phase of instruction execution.

As shown in the figure, a write flag signal is issued from the executing instruction management section when writing of unit data of the execution result of the preceding instruction is started, and if other conditions are met, the write flag signal Starts the subsequent command. This allows the resources of the vector processing device to be used effectively.

However, the method shown in Figure 2 is applicable if there is a stage in the pipeline of the preceding instruction that takes a long processing time, and therefore the writing speed of the result is slower than the reading speed of the same data by the subsequent instruction. Can not. Therefore, in the conventional case of such a combination, it is necessary to wait for the completion of execution of the preceding instruction before starting the subsequent instruction, which increases the idle time of the resources of the vector processing device.

(d1 Purpose of the Invention Therefore, the purpose of the present invention is to improve the parallelism of execution processing of both instructions when the processing speed of the preceding instruction is slower than the processing speed of the succeeding instruction, in view of the above-mentioned problems in vector processing devices. The aim is to provide an improved method.

Te1 Structure of the Invention The object of the present invention is to provide a storage device that can sequentially access a plurality of ordered unit data in a fixed order, and an arithmetic unit that processes the data in the storage device, which requires a first processing time. In an instruction control method for a vector processing device having a first arithmetic unit and a second arithmetic unit that can operate in parallel with the first arithmetic unit and requires a processing time shorter than the first processing time, the first arithmetic unit When a second instruction that uses the second arithmetic unit is executed using data in the storage device as an operand that is the processing result of the first instruction that uses the first instruction, at least the final operand in the execution of the first instruction. This is achieved by an instruction control method characterized in that execution of the second instruction is started before the start of data processing.

(f1 Embodiment of the Invention The present invention will be described in detail below, but before that, the configuration of the vector register storage device 4 suitable for application of the present invention will be briefly described.

Such a storage device consists of a plurality of banks (the figure shows an example of 8 banks, banks 100 to 107), as shown in FIG. By selecting, unit data of all banks belonging to the address can be accessed. In that case, each bank accesses the bank lOO every certain access cycle.
107 are accessed in order. The bank to be accessed is selected by selectors 120 and 121.

110 is a control circuit for the storage device.

In such a storage device, an access control method when the throughput of access a6 (amount of data that can be input/output per time) is smaller than the throughput of the storage device is disclosed in a patent application filed by the same manufacturer (Japanese Patent Application No. ``)r Storage Device Access Control System''. According to this, the throughput of the access source is l that of the storage device.
An integer X that is larger than /X is selected, and the sequential access to banks performed as described above is repeated X times.

By accessing only once every X times as a valid access during this time, all banks can be accessed with a throughput of 1/X.

As the most preferred embodiment of the present invention, an instruction control system for a vector processing device using the above-mentioned recording device as the vector register storage device 4 will be described.

FIG. 4 shows a command control device. The vector instruction fetched from the main memory l is stored in the instruction fetch D register 11.
is set to This instruction is decoded by decoder 12. The decoded instruction information is Q for waiting.
Set in register 13. The instruction transmission control circuit 14 includes the Q register 13 and the executing instruction management section 15-1 or 1.
Based on the information from 5-2, determine whether or not to issue the command,
If it is possible to send, an empty executing command management section 15-1
Alternatively, the instruction information in the Q register 13 is transferred to the Q register 15-2.

The executing instruction management unit 15-1 includes an E register 16-1 for executing instructions, a number circuit 17-1, and a write flag 18.
-1. The El register 16-1 stores instruction information to be executed by the corresponding arithmetic processing section. The counting circuit 17-1 starts counting time when the instruction information is set in the El register 16-1, and turns on the write flag 18-1 when it has counted the time determined by the instruction information. The executing command management unit 15-2 also has the same configuration as the executing command management unit 15-1.

The instruction transmission control unit 14 determines whether the instruction transmission destination arithmetic processing unit and executing instruction management unit are free, ■ whether there is interference with the vector register of the instruction operand, and ■ whether the write flag is on, etc. Determine whether or not it is possible. Here, vector register interference refers to a state in which there is the above-mentioned register interference in the registers on the vector register storage device. If this interference is detected, the write flag 1B-1 or 18-2 is turned on for the preceding instruction, even if other conditions are met.

Wait for command to be sent.

FIG. 5 shows an embodiment of a register interference check circuit included in the instruction transmission control circuit 14. The illustrated circuit corresponds to the executing command management unit 15-1, and the command transmission control circuit 14 is provided with another set of similar circuits corresponding to the executing command management unit 15-2.

In the figure, the write flag signal is write flag 18-
1, and the other input signals are each from El
This is operand register number information behind the instruction information in register 16-1 and Q register 13.

The first operand register number of the E register, that is, the register number where the result of the instruction being executed is stored, and the second operand register number of the Q register.
Or, when the third operand register number matches, the "l" output of the respective comparator circuit 19 or 20 is input to the AND game 21 or 22. At this time, if the write flag signal input to the NOT circuit 23 is "0", the gate 21
41! '!・1, ,−° ・F,,L” rotation;
+, (i+ The command transmission wait signal becomes "1" through the imperative sum gate 24. Under other conditions, the command transmission wait signal becomes "0". In the command transmission control circuit 14, the command transmission wait signal becomes "1". ``While the condition is ``BI'', the transmission of the rendezvous command in the Q-transfer register 13 is suppressed.

FIG. 6 shows an example of vector instruction execution according to the present invention.

The figure shows a case where the following two instructions are to be executed in the order of ■■.

■ VD 1, 2.3 ■ VA 4, 5.1 Here, the VD instruction in ■ executes division between the vectors of vector register number 2 and number 3, and stores the result in vector register number 2 and number 3.
This is an instruction to store in register number 1, and the VA instruction (3) is an instruction to execute addition between vectors of vector register number 5 and number 1, and store the result in vector register number 4.

Therefore, there is register interference at register number l between both instructions.

In addition, the instruction (2) suspends the arithmetic circuit for five cycles in the division of each vector element, and for this reason, the input/output of unit data between the vector register storage device 4 and the arithmetic unit 6 is as per the above-mentioned patent application ( According to the method of patent application 1982-),
It is executed once every five cycles as a valid access.

FIG. 6 shows the flow of time from left to right, and the diamonds represent the progress of the stages of each instruction execution pipeline as a flow from top to bottom. The meanings of symbols such as IF, D, Q, and E are the same as in FIG. The lowest stage in the VD instruction flow is the stage where the operation result is stored in the vector register storage device, and the number indicates the number of the storage device bank accessed in each cycle. Among these, the bank indicated by enclosing the number is the valid one. Indicates that it will be accessed as an access. In this example, the vector is composed of 8 unit data, and the same address in the storage device is accessed 5 times, and 8 data are input/input by accessing the same address in the storage device 5 times for a total of 40 cycles.
It is assumed to be output.

On the other hand, in the vector addition instruction VA (■), all stages of the pipeline advance in one cycle, so data can be input/output to/from the vector register storage device 4 every cycle, and all data can be input/output in 8 cycles. .

When the VD instruction (■) is set in the E register 16-1, the counting circuit 17-1 starts counting time and is incremented by 1 every cycle. When the counted value reaches the set value, the write flag 18-1 is set.
1 is turned on (“1”).

Therefore, the write flag signal in FIG. 5 becomes "1" and the command transmission wait signal becomes "O", so that in the command transmission control circuit 14, the VA instruction in the Q register 13 is transferred to the E2 register 16 for executing instructions. -2, VA command ■
execution begins.

In the above, the setting value of the counting circuit 17-1 is set to determine the start point of the X-th access in the access control method of repeatedly accessing each bank of the vector register storage device 4 X times. . Therefore, when using a counting circuit that counts and amplifies every cycle as described above, the setting value is N(X-1), where the number of banks is N and the number of repeated accesses is It is determined by the time it takes to store the results.

If the latter value is 10 cycles, the setting value in this example is 8X
(5-1)+l0=42.

1g) Effects of the Invention As is clear from the above description, according to the present invention, when there is register interference and the preceding vector instruction requires longer processing time than the subsequent vector instruction, the execution start time of the subsequent instruction can be set by Since it is possible to advance the execution of the preceding instruction to the point where it is completed, it is possible to increase the parallelism of execution of the vector processing device and thus improve the processing performance of the device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an overview of a vector processing device, FIG. 2 is a diagram showing an example of conventional instruction sequence processing timing, FIG. 3 is a diagram showing an example of a vector register storage device, and FIG. 4 is a diagram showing an example of a conventional instruction sequence processing timing. FIG. 5 is a block diagram of an embodiment of the instruction control device, FIG. 5 is a block diagram of an embodiment of the register interference check circuit in the instruction transmission control circuit, and FIG. 6 is a diagram showing an example of instruction sequence processing timing of the present invention. In the figure, 200 is a vector processing device, l is a main storage device, 2 is a main storage control device, 3 is a memory access processing unit, 4 is a vector register storage device, 5 is an instruction control unit,
6 is an arithmetic processing unit, 11 is a D register for instruction fetch, 1
3 is a Q register for waiting, 14 is a command transmission control unit,
15-1 and 15-2 are executing instruction management units, 16-1 and 16-2 are E1 and E2 registers for executing instructions, respectively, 17-1 and 17-2 are counting circuits, 18-1 and 1
8-2 is a write flag, 19 and 20 are comparison circuits, 2
1 and 22 are AND gates, 23 is a NOT gate, 24 is an OR gate, 100 to 107 are storage device banks, 11
0 is a control circuit of the storage device. Construction 1 □ θ O

Claims (1)

[Scope of Claims] A storage device capable of sequentially accessing a plurality of unit data arranged in fil order in a fixed order, and a first arithmetic unit that processes data in the storage device, which requires a first processing time.
an arithmetic unit, the first arithmetic unit is operable in parallel with the first arithmetic unit;
In an instruction control system for a vector processing device having a second arithmetic unit that requires a processing time shorter than the processing time of When a second instruction using two arithmetic units is executed, execution of the second instruction is started at least before the start of processing of the final operand data in the execution of the first instruction. command control method. (2) The storage device sequentially accesses ordered unit data in a fixed order in access cycles equal to the processing time of the second calculation unit, and the first calculation unit requires X times the processing time of the second calculation unit. , in the execution of the first instruction, the same unit data in the storage device is accessed X times each, and only one of the accesses is considered a valid access; A signal that enables the start of execution of the second instruction after the time of starting the access of the first unit data for the Xth access in the access for storing the processing result data in the storage device in the execution. The command control method according to claim f11, characterized in that the command control method is generated.