JPH0222413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device having an arithmetic processing function using SS type instructions.

Conventionally, in data processing devices, instructions that handle variable-length operands have been defined as so-called SS-type instructions that perform operations using operands in main memory and store the results of the operations back in main memory. . For example, the office instruction set consists mostly of SS-type instructions because most of the data it handles is variable-length data. However, when attempting to execute some kind of processing using the office instruction set, a certain operand (operation result) is often used consecutively in several instructions. For example, if we consider the case of adding two pieces of zone format data with the decimal points aligned on a data-based arithmetic unit in pack format, first
After packing two operands, then shifting one of them, and aligning the digits,
Perform addition (shift the calculation result if necessary), and unpack (Uupack) to return to zone format. In order to execute this process, for example, the following processing steps are required.

Pack B→Y Pack A→X Shift X→X Add X+Y→X Shift X→X Unpack X→A Since these are all composed of SS type instructions,
requires 2 operands for memory read and 1 operand for memory write; for others, 1 operand each is required for memory read and memory write; total memory read = 7 operands.
Memory write = 6 operands are required. Therefore, a large amount of time is spent reading/writing the memory, which is a major cause of hindering the calculation speed.

The present invention was made in view of the above circumstances, and
Flag information indicating whether it is necessary to read or write an operand to the main memory is added to the instruction word forming the type instruction, and the flag information is retained when the instruction is executed, and the operand is set according to the retained contents when the operation is executed. This data processing device is configured to select the read/write destination (main memory or arithmetic register section) of the data, thereby significantly reducing the number of accesses to the main memory and significantly improving the arithmetic speed. The purpose is to provide.

An embodiment of the present invention will be described below with reference to the drawings. Here, in the instruction word forming the SS type instruction format,
It has a 2-bit specific flag part, one of which
The first flag information (Flag A) of the bit specifies whether it is necessary to read the operand from the main memory, and the second flag information (Flag B) of the remaining 1 bit specifies whether it is necessary to read the operand from the main memory. It shall be specified whether writing is required or not for the operand of . Specifically, Flag A="O" specifies reading of the operand from main memory, and Flag A="O" specifies reading of the operand from main memory.
"1" specifies reading of operands from the register file of the arithmetic unit instead of the main memory, and Flag
It is assumed that B="O" specifies writing of the operand to the main memory, and Flag B="1" specifies writing the operand to the register file instead of the main memory.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 101 to 106 are arithmetic units (AL)
A gate 101 inputs data on a data bus 201 called an A bus connected to other calculation modules (for example, a fixed-point calculation control unit). 102 is a register that stores part (or all) of the first operand data input through this gate 101.
A selector 103 selects either data output from the gate 101 or output data from an arithmetic unit 105, which will be described later. Reference numeral 104 denotes a register file for storing second operand data, operation result data, etc. output from the selector 103. 105 is this register file 10
This is an arithmetic unit that receives the output data of 4 and the output data of the register 102 and executes an operation according to a designated operation mode. 106 is a gate for outputting the output data of this arithmetic unit 105 to a data bus 202 called S bus. A control section 107 obtains control signals for each section such as the arithmetic section (AL) and memory access, and is composed of a microprogram sequencer, a ROM, a microinstruction register, a microinstruction decoder, and the like. 108A, 108B
is the above-mentioned first, Second
This is a flip-flop that stores flag information Flag A and Flag B and provides the contents to the control unit 107.

FIG. 2 is a flowchart for explaining the operation of the embodiment shown in FIG. 1 above.

The operation of the embodiment shown in FIG. 1 will now be described with reference to the flowchart shown in FIG. 2. Here, since the processing before entering the calculation phase, such as fetching an instruction, is the same as the conventional process, a description thereof will be omitted and only the calculation phase will be described. In the case of a normal SS type instruction, both the first and second flag information mentioned above are “O” (Flag A, Flag B
Therefore, flip-flops 108A and 108B are both in the reset state (FIGS. 2A and 2D). When entering the arithmetic processing phase, the second operand is first fetched, and the operand data read from the main memory is supplied to the selector 103 via the data bus 201 and gate 101. At this time, the selector 103 controls the data bus 2 by a control command from the control unit 107.
Selection control is performed so that the data on 01 is input to the register file 104. As a result, the second operand data is input to the register file 104 and stored (FIG. 2B). Also, at this time, if the operand data cannot be read at once, it is transferred and stored several times. Next, the calculation unit 105 performs calculations under the control of the control unit 107 (FIG. 2C). At this time, if the first operand is required for the operation, the operand data is read from the main memory in parallel with the operation,
After being taken into the register 102, it is given to the arithmetic unit 105 together with the second operand data in the register file 104. After the calculation is completed, the calculation result data output from the calculation unit 105 is
The signal is output via gate 106 onto data bus 202 and stored in main memory (FIG. 2F).

Next, an explanation will be given of the operation when writing of the operand (operation result) to the main memory is omitted. An example of application of this operation is, for example, the above-mentioned series of instructions (Pack A→X). In this case, since the operation result is used again in the next instruction processing, it is sufficient to leave it in the register file 104 in the operation unit (AL), and therefore the write operation to the main memory can be omitted. At this time, of the first and second flag information Flag A and Flag B, only Flag B becomes "1", and only 108B of flip-flops 108A and 108B is set (see FIG. 2D). ). In this case as well, the operation up to the execution of the calculation by the calculation unit 105 is the same as in the above-mentioned operation example. Next, flip-flop 10
If 8B is set, the occurrence of an interrupt is first checked (FIG. 2E). If an interrupt occurs here, there is a possibility that control will be transferred to another task, the same arithmetic unit (AL) will be used again by another task, and different data will be written to the register file 104. Therefore, in this case, even if the flip-flop 108B is in the set state, the operation result is written to the main memory (FIG. 2F) in the same manner as in the above-mentioned operation example, and then control is transferred to interrupt processing. or,
When checking for the presence or absence of an interrupt, if no interrupt has occurred, the selector 103 is selectively controlled to input the output of the arithmetic unit 105 to the register file 104 under the control of the control unit 107 . Thereby, the calculation result output from the calculation unit 105 is taken into the register file 104 via the selector 103, and is used for subsequent calculation processing. In this way, when the flip-flop 108B is in the set state due to the designation of the second flag information Flag B,
After confirming that no interrupt has occurred, the operation result is not written to the main memory, but instead is written to the register file 104.

Next, a case will be described in which fetching of the second operand (reading of the second operand from the main memory) is omitted. As an application example of this operation, for example, the above-mentioned command ~ command (Shift
X). In this case, if X is stored in the register file 104, there is no need to read it from the main memory, and the calculation can be started immediately. In this case, the first and second flag information Flag A,
Of Flag B, only Flag A becomes “1”,
One of the flip-flops 108A and 108B
Only 08A is set (FIG. 2A). When this flip-flop 108A is in the set state,
Under the control of the control unit 107, the operand fetch processing is skipped and control is immediately transferred to the calculation processing (FIG. 2, A→C). At this time, if the first operand is necessary for the operation, the operand data is read from the main memory and transferred to the data bus 201,
After passing through a gate 101 and the like and latched into a register 102, it is applied to an arithmetic unit 105. In this way, when the flip-flop 108A is in the set state due to the designation of the first flag information Flag A, reading of the second operand from the main memory is skipped, and the data stored in the register file 104 is immediately used. The calculation begins.

When the arithmetic processing means of the embodiment described above executes the arithmetic operations according to the instructions .about. as described above, the entire portion of the instruction indicated by X is replaced in the register file 104 in the arithmetic unit (AL). Therefore, as in the above embodiment, attributes (Flag A,
By having Flag B), ,,,
All memory writes are no longer required. Also,
There is also no need to read the memory to read out the X of , , . Therefore, the total number of memory accesses is only 3 operands for memory read and 2 operands for memory write, and the number of memory accesses can be significantly reduced compared to the conventional example described above, resulting in a significant improvement in calculation speed. It can be measured.

In addition, in the above embodiment, information about Flags A and B is provided in the specific field of the SS type instruction, but it is also possible to obtain Flags A and B indirectly from the decoding result of the operation code, for example. .

As described in detail above, according to the data processing device of the present invention, when executing an operation using an SS type instruction,
The number of accesses to the main memory can be significantly reduced, and the calculation speed can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a flowchart for explaining the operation of the above embodiment. AL...Arithmetic unit, 101, 106...Gate, 10
2...Register, 103...Selector, 104...Register file, 105...Arithmetic unit, 107...Control unit, 108A, 108B...Flip-flop, 2
01, 202...Data bus, 203...Control bus, Flag A, Flag B...Flag information.

Claims (1)

[Claims] 1 In a data processing device that performs arithmetic processing on variable-length operand data in main memory using an instruction word of an SS type instruction, corresponding to the instruction word,
First flag information that specifies whether or not operand data is to be read from the main memory and second flag information that specifies whether or not to write the operand data to the main memory are provided, and the first flag information is provided when the operation of the instruction is executed. and a means for holding second flag information; an arithmetic register section for temporarily storing operand data during the execution of the operation of the instruction; and the first and second flag information held by the holding means during the execution of the operation of the instruction. a control unit that controls writing or reading of operand data to or from the memory or the arithmetic register unit by referring to the flag information of the main memory; A data processing device characterized in that the operand is read from the memory and written to the operation register instead of the main memory according to the designation of the second flag information.