JP2987281B2 - Processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register read / write mechanism in a processor used as a CPU of an information processing apparatus and a register interference detection mechanism in a processor having a pipeline structure.

[0002]

2. Description of the Related Art In recent years, with the development of electronic technology, information processing devices such as microprocessors have become widespread and used in all fields. As a conventional processor, for example,
Some are disclosed in JP-A-5-46383 (title of the invention: "data processing device and instruction code allocation system") and in JP-A-5-73778 (title of the invention: "data processing device").

FIG. 5 shows an overall configuration diagram of this conventional processor. In the figure, 50 is a processor, 51 is an input / output bus for exchanging data between the processor 50 and the outside world, 52 is a bus interface circuit for controlling the input / output bus 51, and 53 is a bus interface circuit 52 An instruction reading circuit for reading an instruction, a decoding / address calculation circuit for decoding an instruction received from the instruction reading circuit 53 and calculating an operand address when a memory operand is accessed, and a decoding / address calculation circuit 54 The operation including the access of the memory operand is executed in accordance with the instruction, and when the access of the memory operand is involved, the operation is performed via the bus interface circuit 52. The arithmetic execution circuit 55 has an arithmetic unit for performing arithmetic and logical operations and registers R0 to R3.
3 is allocated as a stack pointer. The decryption / address calculation circuit 54 also uses these registers R0 to R0.
The operand address is calculated using R3. The instruction reading circuit 53 has a program counter PC. This processor has a pipeline structure consisting of three stages, an instruction read circuit 53, a decoding / address calculation circuit 5
4. The processing in the arithmetic execution circuit 55 corresponds to each stage.

The operation of the conventional processor configured as described above will be described with reference to FIG. The figure shows instruction reading,
FIG. 9 is an explanatory diagram showing the processing contents of each stage of decoding / address calculation and operation execution for each cycle. FIG. 9A shows a case where an instruction 2 is processed following an instruction 1 described below. Instruction 1: Add 1 to register R0 and store result in register R0
To be stored.

Instruction 2: A memory is read with the result obtained by adding 2 to the register R0 as an address, and the contents thereof are stored in the register R0.
1 is stored. It should be noted here that the operation of the instruction 1 and the address calculation of the instruction 2 are to be executed simultaneously. That is, in the cycle t3, the arithmetic execution circuit 55 and the decryption / address calculation circuit 54 execute the addition of the instruction 1 and the instruction 2
However, since it is necessary to read the common register R0, the latter cannot be correctly performed unless the former is completed. Therefore, as indicated by the mark x in FIG.
The address calculation and the execution of the operation of the instruction 2 in the cycle t4 are cancelled, and each is processed in the next cycle.
Such a phenomenon is called register operand interference or simply register interference, and a measure for temporarily stopping the flow of the pipeline to avoid a malfunction due to the interference is called a pipeline interlock.

FIG. 1B shows an instruction 3 and an instruction 4 shown below.
Is processed. Instruction 3: Add 2 to register R3 and store result in register R3
To be stored. Instruction 4: Return from subroutine. This instruction 4 is a decoding / address calculation processing cycle in which the memory is read using the contents of the register R3, which is the stack pointer, as an address, and the contents are read by the program counter P
In order to perform the process of storing data in the register C, register interference occurs due to reading and writing of the register R3, as in FIG.
The address calculation stage and the operation execution stage must be interlocked.

FIG. 1C shows an instruction 5 and an instruction 6 shown below.
Are continuously processed. Instruction 5: Return from interrupt processing subroutine. Instruction 6: The memory is read with the result of adding 2 to register R3 as an address, and the contents are stored in register R1. This instruction 5 is a cycle of operation execution, in which 6 is added to the register R3 which is a stack pointer, and the result is stored in the register R3. Therefore, the instruction 5 is caused by reading and writing of the register R3 as in FIG. Therefore, it is necessary to interlock the decryption / address calculation stage and the operation execution stage in cycles t2 and t3, respectively.

Next, how the conventional processor detects register interference will be described. FIG. 7 is an explanatory diagram showing an instruction format of this conventional processor. FIG. 7A shows an instruction format for explicitly specifying a register and a write register used for address calculation.
In the src field, specify the number of the register used for calculating the address of the memory as the source operand, and in the dest field, specify the register number of the destination operand. The binary code described in the op field is particularly called an operation code. The register number is 00 for R0,
01 is set for R1, 10 for R2, and 11 for R3. Instruction 2 and instruction 6 in FIG. 6 take this form. On the other hand, FIG.
(B) is an instruction format in which there is no register to explicitly specify, and all fields specify an operation. Instruction 4 and instruction 5 in FIG. 6 take this form. Instruction 4
Uses the register R3 for address calculation, and in the instruction 5, data is written to the register R3. However, since the register R3 number 11 does not appear in the instruction, the register R3 assigned as a stack pointer is implicitly specified thereafter. Express as being done.

FIG. 8 is a block diagram of a register interference detection mechanism of a processor included in the decoding / address calculation circuit 54 shown in FIG. In the figure, reference numeral 81 denotes an instruction register for storing an instruction in the format shown in FIG.
The 4th and 4th bits are a src field, and the lower 2 bits are a dest field. 82 decodes the contents of the instruction register 81, and if the instruction is an instruction that uses the register indicated in the src field for address calculation in the decoding / address calculation processing cycle (the register read signal RRD = 1 at that time), The instruction is an instruction that uses the register R3 for address calculation in the decoding / address calculation processing cycle (at this time, the stack pointer read signal SP
RD = 1), the instruction is an instruction to write data to the register indicated in the dest field in the operation execution processing cycle (RWT = 1 which is a register write signal at that time), and the instruction is executed in the operation execution processing cycle. It is determined that the instruction is for writing data to the register R3 (at that time, the stack pointer write signal SPWT = 1). RRD and SPRD and RWT and SPWT
Are exclusive (both cannot be 1). 83 to 8
5 is a latch that holds its contents only for one cycle,
Reference numeral 86 denotes a combinational logic circuit. When a register interference is detected, the OR gate at the lowermost stage outputs "1".

FIG. 9 shows a truth table of the combinational logic circuit 86 of the register interference detecting mechanism shown in FIG. LRWT, LSPWT, L
DEST indicates the contents of the latch 83, the latch 84, and the latch 85, respectively. Register interference is detected in the following four cases. (Part 1) When SPRD = 1 and LSPWT = 1. (Part 2) When SPRD = 1, LRWT = 1 and LDEST = SP (register number 11).

(Part 3) RRD = 1, LSPWT = 1 and SRC = SP
(Register number is 11). (Part 4) When RRD = 1, LRWT = 1 and SRC = LDEST. The register interference shown in FIG. 6A is when the register rewritten by the instruction 1 and the register read by the instruction 2 are both explicitly specified.
Mechanism. The register interference shown in FIG. 9B is a case where the register to be rewritten by the instruction 3 is explicitly specified and the register to be read by the instruction 4 is implicitly specified. Is detected. The register interference shown in FIG. 11C is a case where the register to be rewritten by the instruction 5 is implicitly specified and the register to be read by the instruction 6 is explicitly specified. Is detected. The mechanism (part 1) described above functions when the register to be rewritten and the register to be read are both implicitly specified, and the instruction 5 and the instruction 4 in FIG. 6 are successively processed.

Next, how an implicitly specified register is read or written will be described. FIG.
6 is a configuration diagram of a register read / write mechanism of a processor included in the operation execution circuit 55 shown in FIG. In the figure, 101 is a register R0, 102 is a register R1,
103 is a register R2, 104 is a register R3, 105
And 106 are decoders for decoding a 2-bit input and outputting 4 bits in which one of them is 1 and the remaining is 0, and 107 is any of the registers R0 to R3 corresponding to the 4-bit output of the decoder 106. A selector for selecting and outputting one of them, 108 is a driver for transmitting the output of the selector 107 to another, 109 and 111 are OR gates, and 110 is an AND gate. All of the control signals at the left end are input from the register interference detection mechanism of FIG. When register R3 is used implicitly for address calculation, O
The output of '11' of the decoder 106 becomes 1 by the R gate 111, and the contents of the register R3 are read out via the selector 107 and the driver 108. Also, register R3
When data is implicitly written to the OR gate 109, the output of '11' of the decoder 105 becomes 1 by the OR gate 109 and AND
A write clock is applied to the register R3 via the gate 110 to perform writing.

[0013]

However, according to the above-mentioned prior art processor, there are two types of specification at the time of writing (a case where a register is explicitly specified and a case where a register is explicitly specified) which causes the occurrence of register interference. ) And two designations (the same) at the time of reading, it is necessary to detect all four combinations, which complicates the hardware and increases the scale, cost and power consumption of the hardware. There was a problem.

More specifically, the reading and writing of register R3 in decoding circuit 82 in FIG. 8 provided for detecting interference caused by reading and writing of register R3 implicitly specified. , The latch 84 for holding the latter, and the SPRD and LS of the combinational logic circuit 86.
There is a problem that the cost and power consumption of the hardware increase due to the portion that receives the PWT.

In addition, special control hardware is required to realize reading and writing of registers implicitly specified, which further increases the size, cost and power consumption of the hardware. More specifically, hardware cost and power consumption are increased by OR gate 109 in FIG. 10 provided for writing register R3 which is implicitly specified and OR gate 111 provided for reading. There is a problem in that.

The present invention has been made in view of the above problems, and has as its object to provide a processor capable of reducing the scale, cost, and power consumption of hardware by simplifying a circuit.

[0017] In order to achieve the above goal, the program
The processor includes a plurality of registers, and the plurality of registers.
Specify the register number specifying one at the specified position and
A first instruction code for accessing a register;
Access a unique register of a number of registers
Command decoding means for decoding the second command code.
A designated position of the first instruction code.
The position of the second instruction code corresponding to the
Register number of the unique register
And the same bit pattern.

Here, the instruction decoding means, when decoding the second instruction code, takes out a part of the operation code in the second instruction code as it is and accesses it based on the part of the operation code. It may be characterized by selecting a register to be executed. Here, the processor is a processor having a pipeline structure, and the instruction decoding means extracts a part of the operation code in the second instruction code as it is when decoding the second instruction code, and If there is a possibility of register interference between the instruction code and another instruction code
It may be a feature to detect absence .

Here, the first instruction code is stored in the register.
If the instruction involves reading the
Specify the number in the specified position of the source operand and
If the instruction involves writing data,
Signal at the specified position of the destination operand
And the second instruction code reads the unique register.
In the case of the instruction accompanied by the first instruction code,
The second position corresponding to the designated position of the source operand
The position of the instruction code is a part of the operation code
The same bit pattern as the register number of the register
And the second instruction code writes the unique register.
If the instruction is accompanied by an
Corresponds to the specified position of the destination operand
The position of the second instruction code is a part of the operation code.
And the same bit as the register number of the unique register
It may be characterized by being a pattern .

Here, the second instruction code is a stack
It may be characterized in that the instruction is an instruction for accessing a pointer .

In order to achieve the above object, a processor according to the present invention comprises: an instruction reading means for reading an instruction code and holding it in an instruction register; and an instruction decoding means for directly decoding the instruction code held in the instruction register. A plurality of registers, wherein the instruction decoding means specifies a register number specifying one of the plurality of registers at a designated position to access the register, A second instruction code for accessing a unique register among the plurality of registers is decoded, and a position of the second instruction code corresponding to the designated position of the first instruction code is a part of an operation code. The bit pattern may be the same as the register number of the unique register. Here, even when decoding the second instruction code, the instruction decoding means takes out a bit pattern at a position corresponding to the designated position in the instruction code held in the instruction register as it is, and based on the bit pattern. And selecting a register to be accessed. Here, the processor is a processor having a pipeline structure, and the instruction decoding means is configured to decode the second instruction code at a position corresponding to the designated position in the instruction code held in the instruction register. A certain bit pattern is taken out as it is, and a register error based on the instruction code and another instruction code is performed based on the bit pattern.
It may be characterized by detecting the presence or absence of interference. Here, when the first instruction code is an instruction accompanied by reading of the register, the register number is specified at a designated position of a source operand, and when the instruction code involves writing of the register, the register number is designated by the register number. At the designated position of the destination operand, and the instruction decoding means includes a bit pattern at a position corresponding to the designated position of the destination operand of the first instruction code in the instruction code held in the instruction register. Holding means, and a bit pattern at a position corresponding to the designated position of the source operand of the first instruction code in the new instruction code held in the instruction register and the content held by the holding means are Two instruction codes will access the same register at the same time depending on whether they match It may be characterized in that it comprises a coincidence detecting means for detecting whether. In order to achieve the above object, a processor according to the present invention reads an instruction code including a plurality of registers, an instruction code including first, second, and third portions, and at least a first portion having an operation code. The instruction reading means held in the instruction register when the instruction code explicitly indicates a register number specifying one of the plurality of registers at a designated position and indicates an operation involving reading of the register; Deciding to use the second part of the instruction code as the source operand register number;
When the instruction code clearly indicates a register number specifying one of the plurality of registers at a designated position and indicates an operation involving writing to the register, the third part of the instruction code held in the instruction register is written. When the instruction code is determined to be used as a register number serving as a destination operand, and the instruction code indicates an operation involving reading of a unique register among the plurality of registers, the second part of the instruction code is also an operation code. Instruction decoding means for determining that the second part of the instruction code held in the instruction register is to be used as a register number serving as a source operand, contents of an operation to be executed from the instruction decoding means, and a register number serving as a source operand; Execution that receives and executes the register number that is the destination operand It may be characterized in that it comprises a stage. In order to achieve the above object, a processor according to the present invention reads an instruction code including a plurality of registers, an instruction code including first, second, and third portions, and at least a first portion having an operation code. Instruction reading means for holding the instruction register when the instruction code explicitly indicates a register number specifying one of the plurality of registers at a designated position and indicates an operation involving reading of the register. It is determined that the second part of the instruction code is to be used as a register number serving as a source operand, and the instruction code specifies a register number specifying one of the plurality of registers at a specified position, and involves writing the register. When indicating an operation, the third part of the instruction code held in the instruction register is used as a destination operand. It was determined to be used as comprising a register number, the instruction code of the instruction code
The third part is also an operation code, and when indicating an operation involving writing of a unique register among the plurality of registers, the third part of the instruction code held in the instruction register is set as a register number serving as a destination operand. Instruction decoding means for deciding to use, and execution means for receiving and executing the contents of the operation to be executed, the register number as the source operand, and the register number as the destination operand from the instruction decoding means. It may be. In addition,
To achieve this, the processor according to the present invention comprises a plurality of registers.
And a register for specifying one of the plurality of registers
Specify the number at the specified position to access the register.
A first instruction code and a fixed one of the plurality of registers.
Decodes second instruction code for accessing existing registers
And a position corresponding to the designated position of the first instruction code.
And a part of the operation code of the second instruction code.
Select the unique register based on the bit pattern
And a command decoding means.

[0022]

According to the above arrangement, a part of the operation code is unique.
The same bit pattern as the register number of the register
Second instruction code is decoded by the instruction decoding means.

Also, when the second instruction code is decoded, a part of the operation code in the second instruction code is taken out as it is, and a register to be accessed is selected by the instruction decoding means based on the part of the operation code. Is done. Further, when the second instruction code is decoded, a part of the operation code in the second instruction code is taken out as it is, and based on a part of the operation code, the register interference between the instruction code and another instruction code is prevented . The occurrence is detected by the instruction decoding means. Further, when the first instruction code is an instruction that involves reading of the register, the register number is specified at a specified position of a source operand,
If the instruction involves writing to the register, the register number is specified at the designated position of the destination operand. If the second instruction code is an instruction involving reading of the unique register, the first The position of the second instruction code corresponding to the designated position of the source operand of the instruction code is a part of an operation code and has the same bit pattern as the register number of the unique register, and the second instruction code is When the instruction involves writing of the unique register, the position of the second instruction code corresponding to the designated position of the destination operand of the first instruction code is a part of an operation code, and The bit pattern may be the same as the register number of the register.

The second instruction code is a stack point
May be an instruction instructing access to the data.

Further, according to the above configuration, the instruction code is read by the instruction reading means and held in the instruction register, and the instruction code held in the instruction register is directly decoded by the instruction decoding means, and a part of the operation code is obtained. The second instruction code having the same bit pattern as the register number of the unique register is decoded by the instruction decoding means. Further, when the second instruction code is decoded, the bit pattern at the position corresponding to the designated position in the instruction code held in the instruction register is extracted as it is, and the register to be accessed based on the bit pattern specifies the instruction. Selected by decryption means. Further, when the second instruction code is decoded, the bit pattern at the position corresponding to the designated position in the instruction code held in the instruction register is taken out as it is, and the instruction code and another Register interference due to instruction code
Whether the occurrence is detected by the instruction decoding means. Further, in the first instruction code, when the instruction involves reading of the register, the register number is specified at the designated position of the source operand, and when the instruction code involves writing of the register, the register number is A bit pattern that is specified at the designated position of the destination operand and that is at a position corresponding to the designated position of the destination operand of the first instruction code in the instruction code held in the instruction register is held by the holding unit;
The two instruction codes are determined based on whether or not the bit pattern at the position corresponding to the designated position of the source operand of the first instruction code in the new instruction code held in the instruction register matches the content held by the holding means. Are simultaneously detected by the coincidence detecting means. Further, according to the above configuration, the first,
An instruction code, which includes second and third parts and has an operation code in at least a first part, is read by an instruction reading means and held in an instruction register, and the instruction code specifies one of a plurality of registers. When the operation is accompanied by reading of the register by specifying the number in the designated position, the instruction decoding means determines that the second part of the instruction code held in the instruction register is used as the register number serving as the source operand. If the instruction code explicitly indicates a register number specifying one of a plurality of registers at a specified position to indicate an operation involving writing to the register, the third part of the instruction code held in the instruction register is destined. It is determined by the instruction decoding means to use the register number as an operand, and the instruction code As register number of the second portion of the instruction code held in the instruction register becomes the source operand to indicate operation involving the reading of specific registers of the second portion is also opcode plurality of registers of the instruction code The use of the instruction is determined by the instruction decoding means, and the content of the operation to be executed, the register number as the source operand, and the register number as the destination operand are received from the instruction decoding means and executed. Further, according to the above configuration, an instruction code including the first, second, and third portions and having an operation code in at least the first portion is read by the instruction reading means and held in the instruction register. If a register number specifying one of a plurality of registers is specified at a specified position to indicate an operation involving reading of the register, the second part of the instruction code held in the instruction register is used as a source operand register It is determined by the instruction decoding means to be used as a number, and if the instruction code clearly indicates a register number specifying one of the plurality of registers at a specified position and indicates an operation involving writing to the register, the instruction code is held in the instruction register. Using the third part of the instruction code as the register number to be the destination operand Is determined by the stage, a third portion of the instruction code held in the instruction register when the instruction code indicating an operation that writes specific registers of the third portion is also opcode plurality of registers of the instruction code Is used by the instruction decoding means to determine the contents of the operation to be executed, the register number serving as the source operand, and the register number serving as the destination operand. And executed. Also according to the above configuration
If the second instruction code is decoded by the instruction decoding means,
The position corresponding to the position specified by the first instruction code
Based on the bit pattern of the second instruction code in
An existing register is selected.

[0026]

FIG. 5 is a block diagram showing the overall arrangement of a processor according to an embodiment of the present invention.
It is composed of Further, the processor 50 includes a bus interface circuit 52, an instruction reading circuit 53,
It comprises an address calculation circuit 54 and an operation execution circuit 55, has a pipeline structure consisting of three stages, and has an instruction reading circuit 53, a decoding / address calculation circuit 5
4. The processing in the arithmetic execution circuit 55 corresponds to each stage.

The processor 50 comprises a bus interface circuit 52, an instruction reading circuit 53, a decoding / address calculation circuit 54, and an operation execution circuit 55. The input / output bus 51 exchanges data between the processor 50 and the outside world. The bus interface circuit 52 controls the input / output bus 51. The instruction reading circuit 53 has a program counter PC, and reads an instruction through the bus interface circuit 52.

The decoding / address calculation circuit 54 decodes the instruction received from the instruction reading circuit 53, and calculates the operand address when the memory operand is accessed. When calculating the operand address, a register inside the arithmetic execution circuit 55 is used. The operation execution circuit 55 includes a decryption / address calculation circuit 54
The operation including the access of the memory operand is executed in accordance with the instruction. At this time, access to the memory operand is performed via the bus interface circuit 52. It also has an arithmetic unit for performing arithmetic and logical operations and registers R0 to R3 inside.
3 is allocated as a stack pointer.

FIG. 1 is an explanatory diagram showing an instruction format of a processor in this embodiment. FIG. 11A shows an instruction format for explicitly specifying a register and a write register used for address calculation. The operation is performed in an op field, and the number of a register used for calculating the address of a memory serving as a source operand in a src field. To
Specify the register number of the destination operand in the dest field. Register number is 0 for R0
0, 01 for R1, 10 for R2, and 11 for R3.

FIG. 2B shows the format of an instruction in which the register R3 is used for address calculation in the decoding / address calculation processing stage among the instructions that implicitly specify the register R3 in the prior art, and all fields specify operations. However, the third and fourth bits from the lower order of the operation code are limited to 1. In other words, the third and fourth bits from the low-order register R3
May be viewed as a field for specifying

FIG. 3C shows the format of an instruction in which data is written to the register R3 in the processing step of execution of an operation among instructions for implicitly specifying the register R3 in the prior art, in which all fields specify an operation. However, the lower two bits of the operation code are limited to 1. In other words, the third and fourth bits from the lower order may be regarded as a field for specifying the register R3.

FIG. 2 is a block diagram of a register interference detecting mechanism included in the decoding / address calculation circuit 54 shown in FIG. 5, and includes a command register 21, a decoding circuit 22, a latch 23, a latch 24, and a combinational logic circuit 25. It is configured. The instruction register 21 is a register for storing an instruction in the format shown in FIG. 1. The upper 4 bits are an OP field, the third and fourth bits from the lower are a src field, and the lower 2
Let the bits be the dest field or all 8 bits the OP field.

The decoding circuit 22 decodes the contents of the instruction register 21 and determines that the instruction is an instruction that uses the register indicated in the src field for the address calculation in the decoding / address calculation processing cycle (the register read signal RRD =
1) and that the instruction is an instruction for writing data to the register indicated in the dest field in the processing cycle of the operation execution (at that time, the register write signal RWT = 1).

The latch 23 has the RWT for only one cycle.
Hold. Latch 24 is DEST only for one cycle
Hold. Reference numeral 25 denotes a combinational logic circuit. When register interference is detected, the AND gate outputs "1". FIG. 3 is FIG.
3 shows a truth table of the combinational logic circuit 25 of the register interference detection mechanism shown in FIG. LRWT and LDEST indicate the contents of the latch 23 and the latch 24, respectively. Register interference is RRD = 1 and LRW
Detected when T = 1 and SRC = LDEST.

A description will be given of how the detection of register interference is realized in the processor of the present embodiment configured as described above. An explanation will be given using an example shown in FIG. 6 to clarify the difference from the conventional processor. (A)
The register interference shown in (1) is a case where a register to be rewritten (R0 of instruction 1) and a register to be read out (R0 of instruction 2) are both explicitly specified. The operation in this case is the same as that of the conventional processor. When the instruction 2 is decoded in the cycle t3, the decoding circuit 22 uses the register indicated in the src field for address calculation in the decoding / address calculation processing cycle, so that the decoding circuit 22 determines that RRD = 1
And the src field is SRC [1: 0] = 00. On the other hand, the immediately preceding instruction 1
The latch 23 holds LRWT = 1 because the instruction writes data into the register indicated by the st field, and the latch 24 holds LDEST [1: 0] = 00 by the dest field of the instruction 1. As a result, the output of the AND gate of the combinational logic circuit 25 becomes 1, and register interference is detected.

In the register interference shown in (b), the register to be rewritten is explicitly specified (R3 of instruction 3), and the register to be read is implicitly specified (R3 of instruction 4).
Is the case. The operation in this case is different from a conventional processor. The instruction 4 is an instruction that uses the register R3 for address calculation implicitly in the decryption / address calculation processing cycle, and the portion of the opcode located in the src field becomes 11 as shown in FIG. Therefore, it can be interpreted that the register indicated in the src field is used for address calculation. Then, when the instruction 4 is decoded in the cycle t3, the decoding circuit 22 regards this instruction as an instruction that uses the register indicated in the src field for the address calculation in the decoding / address calculation processing cycle, and
RRD = 1 is output, and the part located in the src field is 11
Therefore, SRC [1: 0] = 11. On the other hand, since the immediately preceding instruction 3 is an instruction for writing data to the register indicated by the dest field in the processing cycle of the operation execution, the latch 23
LRWT = 1 is held, and the latch 24 holds LDEST [1: 0] = 11 by the dest field of the instruction 3. As a result, the output of the AND gate of the combinational logic circuit 25 becomes 1, and register interference is detected.

In the register interference shown in (c), the register to be rewritten is implicitly specified (R3 of instruction 5), and the register to be read is explicitly specified (R3 of instruction 6).
Is the case. The operation in this case is also different from the conventional processor. Instruction 5 has a register R
3 is an instruction for writing data implicitly. Since the portion corresponding to the dest field in the operation code is 11, as shown in FIG. 1C, the data is stored in the register indicated in the dest field. Can be interpreted as writing. Then, when the instruction 6 is decoded in the cycle t2,
Since this instruction is an instruction that uses the register indicated in the src field for address calculation in the decoding / address calculation processing cycle, the decoding circuit 22 outputs RRD = 1, and the src field is SRC [1: 0] = 11. ing. On the other hand, the decoding circuit 22 considers that the immediately preceding instruction 5 is an instruction for writing data to the register indicated by the dest field in the processing cycle of the operation execution, and
The latch 23 holds LRWT = 1 by the output RWT = 1,
Since the portion located in the dest field of the instruction 5 is 11, the latch 24 holds LDEST [1: 0] = 11. As a result, the output of the AND gate of the combinational logic circuit 25 becomes 1, and register interference is detected.

FIG. 4 is a block diagram of the register read / write mechanism of the processor according to the present embodiment. The register R0 of 41, the register R1 of 42, the registers R2 and 44 of 43 are provided.
, A decoder 45 and a decoder 46, a selector 47, a driver 48, and an AND gate 49. 41 to 44 are registers, and only the register R3 of 44 is allocated as a stack pointer.

The decoder 45 and the decoder 46 decode a 2-bit input so that one of them is 1 and the other is 0
Is output. The selector 47 selects and outputs any one of the registers R0 to R3 in accordance with the 4-bit output of the decoder 46. The driver 48 transmits the output of the selector 47 to another.

The AND gate 49 takes a logical sum of two inputs. The control signals at the left end are all input from the register interference detection mechanism of FIG. Next, a description will be given of how the processor of this embodiment implements reading and writing of registers implicitly specified.

In the instruction that uses the register R3 for address calculation implicitly in the decoding / address calculation processing cycle, the portion of the opcode located in the src field is shown in FIG.
11B, SRC [1: 0] = 11 is input to the decoder 46 as shown in FIG. On the other hand, the decoding circuit 22 shown in FIG. 2 outputs RRD = 1 to the driver 48 assuming that the same instruction is an instruction that uses the register indicated in the src field for address calculation in a decoding / address calculation processing cycle. In response, the output of 11 of the decoder 46 becomes 1 and the contents of the register R3 are read via the selector 47 and the driver 48.

In the instruction for implicitly writing data to the register R3 in the processing cycle of the operation execution, dest in the operation code
1C is 11 as shown in FIG. 1C, and DEST [1: 0] = 11 is input to the decoder 46. On the other hand, the decoding circuit 22 in FIG. 2 regards the instruction as an instruction for writing data to the register indicated in the dest field in the processing cycle of the operation execution, and outputs RWT = 1 to the AND gate 49. In response to these, 11 of the decoder 45
Becomes 1 and the register R is output via the AND gate 49.
3, a write clock is applied to perform write.

As described above, according to the present embodiment, by using the hardware for reading and writing the explicitly designated register, conventionally, the implicitly designated register can be read or written. . Therefore, as compared with the conventional processor, hardware dedicated to reading and writing of registers implicitly specified (OR gate 109 and AND gate 11 shown in FIG. 10) is provided.
0) reduces cost and power consumption.

Conventionally, by using hardware for detecting register interference caused by reading and writing of explicitly designated registers, conventionally, registers caused by reading and writing of implicitly designated registers are conventionally used. Interference can be detected. Therefore, as compared with the conventional processor, hardware dedicated to detecting register interference caused by reading and writing of registers implicitly designated (SP of the decoding circuit 82 shown in FIG. 8) is used.
The cost and power consumption are reduced only by the part that generates RD and SPWT, the latch 84, and the OR gate and three AND gates in the combinational logic circuit 86.

In this embodiment, the instruction format sr
Registers specified in c and dest fields from R0 to R
3 and the register specified implicitly is R
Although three, these may be any number of any registers. In that case, the instruction format sr
The field of c and dest is set to a bit width corresponding to the number of registers (for example, 3 bits for 8 registers, 4 bits for 16 registers), and in an instruction for implicitly reading a register, the position of the src field is the register number and the register number. In an instruction that implicitly writes data to a register, the operation code is such that the position of the dest field is the register number.

In this embodiment, the format of the instruction is 2
Although the operands are used, these may be three operands. At this time, in an instruction that reads a register implicitly, one of the fields corresponding to one of the two source operand designating fields is an operation code whose number is the register number. Also, in the present embodiment, the register interference between the register read at the address calculation stage and the register write at the operation execution stage occurs in a processor having a pipeline configuration consisting of three stages of instruction reading, decoding, address calculation, and operation execution. However, the present invention is not limited to this pipeline configuration, and can be applied to any pipeline configuration in which reading and writing of an internal register are performed in a plurality of stages. For example, in a processor having a pipeline configuration including four stages of instruction reading, decoding, register reading, and operation execution (including address calculation), a register read at a register read stage and a register write at an operation execution stage are performed. May cause register interference. At that time, in the instruction that reads the register implicitly, the position of the field of src becomes the operation code whose number is the register,
For an instruction that implicitly writes data to a register, the position of the dest field is an opcode whose register number is the register number.

[0047]

As described above, according to the present invention, by using the hardware for reading and writing the register explicitly specified without providing dedicated hardware, conventionally, the hardware which is implicitly specified is used. Registers can be read or written, and therefore, compared to conventional processors, hardware dedicated to reading and writing of registers implicitly specified (OR gate 109 shown in FIG. Only the AND gate 110) reduces the circuit size, cost, and power consumption.

Also, by using hardware for detecting register interference caused by reading and writing of explicitly designated registers, register interference caused by reading and writing of implicitly designated registers is detected. As compared with a conventional processor, hardware dedicated to detecting register interference caused by reading and writing of a register implicitly specified (decoding circuit 82 shown in FIG. 8) can be used. And the OR gate and the three AND gates of the latch 84 and the combinational logic circuit 86) that reduce the cost and power consumption, and reduce the hardware circuit scale and the cost and power consumption. The practical effect is great.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an instruction format of a processor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a register interference detection mechanism of a processor in the present embodiment.

FIG. 3 is an explanatory diagram showing a truth table of the combinational logic circuit 25 of the register interference detection mechanism of the processor in the embodiment.

FIG. 4 is a configuration diagram of a register read / write mechanism of a processor in the present embodiment.

FIG. 5 shows an overall configuration diagram of a processor which is common to the processor in the present embodiment and a conventional processor.

FIG. 6 is an explanatory diagram showing an example of processing contents of each stage of a pipeline of the processor, which is common to the processor in the present embodiment and a conventional processor.

FIG. 7 is an explanatory diagram showing an instruction format of a conventional processor.

FIG. 8 is a configuration diagram of a register interference detection mechanism of a conventional processor.

FIG. 9 is an explanatory diagram showing a truth table of the combinational logic circuit 86 of the conventional register interference detection mechanism of the processor.

FIG. 10 is a configuration diagram of a register read / write mechanism of a conventional processor.

[Explanation of symbols]

 21 Instruction Register 22 Decoding Circuit 23 Latch 24 Latch 25 Combinational Logic Circuit 41 Register R0 42 Register R1 43 Register R2 44 Register R3 45 Decoder 46 Decoder 47 Selector 48 Driver 49 AND Gate 50 Processor 51 Input / Output Bus 52 Bus Interface Circuit 53 Instruction Read Circuit 54 Decoding / Address Calculation Circuit 55 Arithmetic Execution Circuit 81 Instruction Register 82 Decoding Circuit 83 Latch 84 Latch 85 Latch 86 Combinational Logic Circuit 101 Register R0 102 Register R1 103 Register R2 104 Register R3 105 Decoder 106 Decoder 107 Selector 108 Driver 109 OR Gate 111 OR gate 110 AND gate

Claims (12)

(57) [Claims] A first register that specifies a plurality of registers and a register number that specifies one of the plurality of registers at a designated position to access the register;
And an instruction decoding means for decoding a second instruction code for accessing a unique register of the plurality of registers, wherein the instruction code is located at the designated position of the first instruction code. The position of the corresponding second instruction code is a part of an operation code,
A processor having the same bit pattern as the register number of the unique register. 2. The instruction decoding means, when decoding the second instruction code, takes out a part of the operation code in the second instruction code as it is and accesses based on the part of the operation code. 2. The processor according to claim 1, wherein a register to be selected is selected. 3. The processor according to claim 1, wherein the processor is a processor having a pipeline structure, and the instruction decoder decodes a part of the operation code in the second instruction code when decoding the second instruction code. Take out the register as it is and register it with the instruction code and other instruction codes based on a part of the operation code.
2. The method according to claim 1, wherein the presence or absence of interference is detected.
A processor according to claim 1. 4. When the first instruction code is an instruction involving reading of the register, the register number is specified at a designated position of a source operand, and when the instruction code involves writing of the register, Specifies the register number at a designated position of a destination operand, and specifies the source operand of the first instruction code when the second instruction code is an instruction that involves reading of the unique register. The position of the second instruction code corresponding to the position is a part of an operation code, and has the same bit pattern as the register number of the unique register, and the second instruction code writes the unique register. If the instruction is an associated instruction, the first instruction code corresponds to the designated position of the destination operand. 4. The processor according to claim 1, wherein the position of the second instruction code is a part of an operation code and has the same bit pattern as the register number of the unique register. 5. The processor according to claim 4, wherein said second instruction code is an instruction for instructing access of a stack pointer. 6. A processor comprising: an instruction reading unit that reads an instruction code and holds the instruction code in an instruction register; an instruction decoding unit that directly decodes the instruction code held in the instruction register; and a plurality of registers. The instruction decoding means specifies a register number specifying one of the plurality of registers at a designated position, and performs a first access to the register.
And a second instruction code for accessing a unique register among the plurality of registers, and a position of the second instruction code corresponding to the designated position of the first instruction code Is part of the opcode,
A processor having the same bit pattern as the register number of the unique register. 7. The instruction decoding means, when decoding the second instruction code, extracts a bit pattern at a position corresponding to the designated position in the instruction code held in the instruction register as it is. 7. The processor according to claim 6, wherein a register to be accessed is selected based on the bit pattern. 8. The processor according to claim 1, wherein said processor is a processor having a pipeline structure, and said instruction decoding means, when decoding said second instruction code, outputs said instruction code in said instruction code held in said instruction register. The bit pattern at the position corresponding to the position is directly taken out, and the register interference between the instruction code and another instruction code is performed based on the bit pattern.
7. The processor according to claim 6, wherein the presence / absence of the occurrence is detected. 9. When the first instruction code is an instruction accompanied by reading of the register, the register number is specified at a designated position of a source operand, and when the instruction code involves writing of the register, Specifies the register number at the designated position of the destination operand, and the instruction decoding means corresponds to the designated position of the destination operand of the first instruction code in the instruction code held in the instruction register. Holding means for holding a bit pattern at a position to be executed, and a new instruction code held in the instruction register,
The two instruction codes may access the same register at the same time, depending on whether or not the bit pattern at the position corresponding to the designated position of the source operand of the first instruction code matches the content held by the holding means. 9. The processor according to claim 8, further comprising: a coincidence detecting unit configured to detect whether or not the setting is made. 10. An instruction reading means, comprising: a plurality of registers; first, second, and third parts; an instruction reading means for reading an instruction code having an operation code in at least a first part and holding the read instruction code in an instruction register; When the instruction code explicitly indicates a register number for specifying one of the plurality of registers at a designated position and indicates an operation involving reading of the register, the second part of the instruction code held in the instruction register is written. If the instruction code is determined to be used as a register number serving as a source operand, and the instruction code indicates a register number specifying one of the plurality of registers at a specified position and indicates an operation involving writing of the register, The third part of the instruction code held in the instruction register is used as a register number serving as a destination operand. When the instruction code is an operation code also in the second part of the instruction code and indicates an operation involving reading of a unique register among the plurality of registers, the instruction held in the instruction register is determined. Instruction decoding means for deciding to use the second part of the code as a register number serving as a source operand; and from the instruction decoding means, contents of an operation to be executed, a register number serving as a source operand, and a destination operand. And an execution means for receiving and executing the register number. 11. An instruction reading means comprising: a plurality of registers; first, second, and third portions; an instruction code having an operation code in at least a first portion; and reading the instruction code in an instruction register; When the instruction code explicitly indicates a register number for specifying one of the plurality of registers at a designated position and indicates an operation involving reading of the register, the second part of the instruction code held in the instruction register is written. If the instruction code is determined to be used as a register number serving as a source operand, and the instruction code indicates a register number specifying one of the plurality of registers at a specified position and indicates an operation involving writing of the register, The third part of the instruction code held in the instruction register is used as a register number serving as a destination operand. When the instruction code is an operation code also in a third part of the instruction code and indicates an operation involving writing of a unique register among the plurality of registers, the instruction held in the instruction register is determined. Instruction decoding means for deciding to use the third part of the code as a register number serving as a destination operand; from the instruction decoding means, contents of an operation to be executed, a register number serving as a source operand, and a destination operand And an executing means for receiving and executing the register number. 12. A plurality of registers and a register number for specifying one of the plurality of registers are designated.
The first to access the register explicitly at the fixed position
Instruction code and a unique code among the plurality of registers.
The second instruction code that accesses the register of
And a position corresponding to the designated position of the first instruction code.
Part of the operation code of the second instruction code
The unique register is selected based on the bit pattern
Command decoding means for selecting
Ssa.