JPS5819954A - Data processing device - Google Patents

Abstract

PURPOSE:To reduce the number of times of access to a main memory considerably to improve the operation speed, by selecting the main memory or an operation register part in accordance with held contents of flog information when an instruction is executed. CONSTITUTION:Means 108A and 108B, which hold flag information designating whether operand data obtained directly or indirectly from an SS type instruction should be read out from a main memory or be written in the main memory, and an operation register part AL where operand data in the operation execusion of an instruction is stored temporarily are provided. A controlling part 107 is provided which refers to flag information held in the operation execution of the instruction to control the write or the read of operand data to or from the main memory or the operation register part AL.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device having an arithmetic processing function using 5liII instructions.

Conventionally, in data processing devices, instructions that handle variable-length operands are defined as nSs-type instructions that perform operations using operands in main memory and store the results of the operations back in the main memory. For example, an office instruction set, in which most of the data it handles is variable length data, consists mostly of SS@ instructions.

However, when attempting to perform some processing using the office instruction set, the operands (operation results) are often used consecutively in several instructions. Let's consider the case of adding two pieces of data in zone format with a device with the decimal point stirrups aligned. First, Paek L the two lands, then Shift one of them.
L) After performing the combination, if it is necessary to perform addition (Add), shift the calculation result) L), Anonymous parable (
[rnpa@k) and return to the zone format.The ninth step of executing this process requires, for example, the processing steps ① to ① shown below.

■ Pa@k B4Y ■ Pack A-+X ■ 8hift X-4X ■ Add X + Y -) X■, 5h
1ft x-+x ■ Unps+ek Each write requires one operand, and the total memory read =
It takes 7 lands and 6 lands for memory write. Therefore, a large amount of time is consumed in reading/writing the memory, which is a major factor hindering the calculation speed.

The present invention has been made in view of the above-mentioned circumstances, and includes an instruction word that constitutes an SS type instruction that includes read operands to the main memory,
Flag information indicating whether a write is required or not is added, and the flag information is retained when executing the instruction, and according to the retained contents, when executing an operation, it is An object of the present invention is to provide a data processing device which can significantly reduce the number of accesses to the main memory and significantly improve the calculation speed by selecting the main memory (register section).

An embodiment of the present invention will be described below with reference to the drawings. Here, an instruction word in the sB type instruction format has a 2-bit specific flag part, and 1 bit of the first flag information is included. (Flag A) specifies whether it is necessary to read the operand from the main memory, and the remaining 1-bit second
The flag information (Fl island gB) K specifies whether or not writing of the operand to the main memory is required. That is, specifically, Flag=@O- specifies reading of the operand from main memory, and Flag A-=@
l' specifies reading of the operand from the register file of the arithmetic unit instead of the main memory, and Flmg B; @O''
Specifies writing of the operand to main memory with Fla
g Bw @1'' specifies writing of the command to the register 7 isle instead of the main memory. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 201 106 to 106 are constituent elements of an arithmetic unit (AL), and 101 is a data/f path connected to other arithmetic modules (for example, a fixed-point arithmetic control unit), etc., and is connected to the data/f path 201. This is the input r-t.1
02 is the first output (
103 is a register for storing a part (or all) of the output data. 103 is a selector for selecting either the data outputted from the r-t 101 or the output data of the arithmetic unit 108, which will be described later. 104 is a register aisle that stores the second operand data, operation result data, etc. output from this selector 103.1elS
Fi.

This is an arithmetic unit that receives the output data of this register file 104 and the output data of the register 102 and executes an operation according to a designated operation mode.

106 is an e for outputting the output data of the arithmetic unit 105 as a data signal called SI xo;ttVc.
- It is. Reference numeral 101 denotes a control unit that obtains control signals for each unit such as the arithmetic unit (AL) and memory access, and includes a micro fO Durham sequencer and a ROM.

It consists of a microinstruction register, microinstruction decoder, etc. 108 and 108B are inputted via a control node called CNTA which exchanges various control signals between the control unit 101 and nine calculation modules including the calculation unit (AL) described above. 1st. Second flag information Flag A, Flmg B
Fritz f70 stores the contents and gives the contents to the control unit 101.
It's Tuzo.

FIG. 2 is a rounding flowchart illustrating the operation of the embodiment shown in FIG. 1 above.

The operation of the embodiment shown in FIG. 1 will now be described with reference to the flowchart shown in FIG. 2. ζ Hi de Mori,
The processing before entering the operation phase, such as the 7th step of the instruction, is the same as before, so its explanation will be omitted, and the operation phase will be explained below.
je? For normal 88 type instructions,
The above 1. Both 72g information of relay 2 is 0' (Flag
input F1mg B = @O''), and therefore, both the 7th lip 7a and l0IA and l0IIB are in the reset state (Fig. 2 A, D).
7 First, the second O (land) is fetched and the operand data read from the main memory is transferred to the data bus 2.
01,? -) 70 J and is supplied to the selector 103. At this time, the selector 103 is selectively controlled to input data on the data bus 201 to the register file 104 by a control command from the control unit 101. With this), the second operand data is the register file 10
4 and stored (second wJB). Also, at this time, if the above operand data cannot be read at once, it is transferred and stored several times to the 6th order arithmetic unit 1.
By 05.

Calculations are performed under the control of the control unit 107 (FIG. 2C)
), at this time, if the @1 operand is required for the operation, its operation is read out from the main memory () in parallel with the operation and taken into the register 102, and then stored in the register file 104. Arithmetic unit 105fC is applied together with second operand data. After the calculation is completed, calculation 11
105〉 is outputted to the data line of the result of the nine operations, r-to1
0g, is output onto the data bus 201, and stored in the main memory (FIG. 2F).

Next, an explanation will be given of the operation when writing of the operand (operation result) to the main memory is omitted.

As an application example of this operation, for example, the above-mentioned series of commands
An example of this is the instruction (Pa@k A→X). In this case, the result of the operation can be left in the register file 104 in the arithmetic unit (AL) in order to be used again in the next 0 instruction processing, and therefore the write operation to the main memory can be omitted. At this time, Hiro, the aforementioned O No. 1. Second 7 lag information Fla
gA.

Of FlmgB, only FlmgB is @1'', Fligfup Tsubu 108mm, 101B out of 108B
is set (FIG. 2D), and in this case as well, the depth of calculation by the arithmetic unit 161 is the same as in the above-mentioned operation example. If 108B is set, the occurrence of an interrupt is first checked (FIG. 2E). When an interrupt occurs at this point, control is transferred to another task and the same calculation unit (MU L) is restarted in another task.
) may be used and other data may be written to the register file 104. Therefore, in this case welfare fri f7
Even if 0ff10gB is in the set state, the calculation result is written to the main memory in the same manner as in the above-mentioned operation example <fK2 (Fig. Fl), and then control is transferred to interrupt processing. Also, when checking the presence or absence of the above interrupt, if 1 interrupt does not occur,
Under the control of the control unit 1010, the selector 103 operates as the arithmetic unit 10.
Selection control is performed to input the output of No. 5 to the register file 104. As a result, the operation result output from the arithmetic unit 105 passes through the selector 103 to the register file 1.
04 and used for subsequent calculation processing. In this way, after confirming that the 7-rig float f10BB is in the set state 11 by specifying the second flag information F1mgB and that no interrupt has occurred, the operation result is written to the main memory. Instead, the register file 104
write to.

Next, the 7th edge of the second O C land (from the main memory to the O second
In case of omitting the operation readout, it is stated as ')%/%. As an application example of this operation, for example, the above-mentioned command
An example of the instruction (shtttX-+X>) is the instruction (shttt Of the 1st and 2nd) 2nd flag information Flag A and Flmg B, Flag
Only A is displayed as 11”, and the frig float flO8,
Of 10.11H, only 108 is set (person in Figure 2).

When this frig f4 f1011 is in the set state, the processing of operand 7 etching is skilved under the control of the control unit 1010, and control is immediately transferred to the calculation processing (second
Figure A→C). At this time, if the first 4/P is required for the calculation, the land data is read from the main memory and transferred to the register 10IK' via the data bus 201.1''-101 etc. After that, it is given to operation 0105.In this way, when the first flag information Flag is specified and 7 reset!108 people are in the set state, the readout of the second operand from the main memory is skipped An operation is immediately started using the data stored in the register file 104.

When the arithmetic processing means of the embodiment described above executes the arithmetic operations using the instructions ■ to ■O as described above, all the portions of the instructions indicated by X are replaced in the register file 104 in the arithmetic unit (AL). . Therefore, as in the above embodiment, by providing the command word with attributes (Flag A, Flmg B) specifying the Oland Nori 1 read/write, ■ and ■.

The memory writes of ■ and ■ are all unnecessary. Also■、■
There is also no need to read the memory to read the X's of , ■, and ■. Therefore, the total number of memory accesses is only 3 operands for memory read and 2 operands for memory write, and the number of memory accesses can be significantly reduced compared to the conventional example mentioned above. Significant improvement can be seen.

In addition, in the above embodiment, the specific field K of the Hiro 3s type instruction
For example, KL& is 1 to have the information of F1agm and B. For example, F1 is indirectly
lmg people, please K and turtle to get B.

As detailed above, according to the data processing device of the present invention,
When performing calculations using 88-type instructions, the number of accesses to the main memory can be significantly reduced, and the calculation speed can be significantly improved.

[Brief explanation of the drawing]

Fig. 1 is an f+2 ivy diagram showing one embodiment of the present invention, and Fig. 2 is a 70- chart for explaining the operation of the above embodiment. Anus...Arithmetic unit, 101, 106...r-), 102
...Register, 103...Sector ν, 104...
Register file, 105...Arithmetic unit, 101...
Control unit, 108, 1 (JIB...F70 horn, 201゜202...Data bus, 20S...Control/f70, Flmg, Flag 7')
Da information.

Claims (1)

[Claims] Means for retaining flag information specifying whether or not a fourth land fh-data obtained directly or indirectly from an SS-type instruction is to be read out or written to the main memory, and an operation of the instruction. an arithmetic register section that temporarily stores operand data during execution; and an iP that refers to the held flag information when executing the operation of the instruction, and controls writing or successive output of operand data to the main memory or the arithmetic register section. What is claimed is: 1. A data processing device comprising: a control unit for performing operations;