JPS6275743A - Diagnostic system for microinstruction - Google Patents

Abstract

PURPOSE:To execute highly accurate diagnoses, by causing an instruction buffer to hold data outputted from an arithmetic logical operation circuit instead of data read out from a memory and loading the held data onto an instruction processing section. CONSTITUTION:When the 1st microinstruction 600 is outputted, a selector 8 selectively passes data 400 from an arithmetic logical operation circuit 7 through an ALUI and outputs the data 400 to a RIB 1. When the 2nd microinstruction 800 is outputted to the RIB 1 thereafter, the data held by the RIB 1 are loaded onto and processed by an instruction processing section 5. A RIB checking circuit 6 simultaneously outputs a read request signal 200 to a gate 9 when detecting that the RIB 1 becomes vacant, but, since a flip flop 10 is set by the 2nd microinstruction 800, passing of the signal 200 through the gate 9 is checked. Therefore, no bus controlling signal is inputted to a bus controller 3 and, as a result, readout of instructions from a memory 2 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The invention relates to a microinstruction diagnosis method in the computation implementation of a microprogram ilJ control method.

[Technical Background of the Invention] Conventionally, a circuit as shown in FIG. 2 has been adopted around an instruction buffer (hereinafter referred to as RIB) provided in this type of calculator. That is, the symbol @1 is the RIB, which holds user instructions fetched from the main memory 2. Reference numeral 3 denotes a bus controller that controls access to the main memory 2 through the common bus 50. Reference numeral 4 denotes a gate that allows either a microinstruction 100 for fetching an instruction from the main memory or a read request signal 200 from the main memory 2 to pass to the bus controller 3. Code 5 is load signal @30
This is an instruction processing unit that processes instructions loaded from RIB1 by 0. Reference numeral 6 denotes an RIB check circuit that, after loading an instruction from RIB1 to the instruction processing unit 5, detects whether RIBI is empty or not, and outputs a read request signal 200 if it is empty.

To diagnose RIB-related microinstructions, the circuit configuration C described above first writes specific data to the main memory 2, and then writes the microinstruction 100 that fetches that data or the next instruction from the RI81. This is done by loading the data in the main memory 2 into the RIBI using a microinstruction that fetches the data from the main memory 2.

[Problems with the previous day's technology] Therefore, in order to diagnose RIB-related instructions, the operation of the main memory 2 must be guaranteed, and if this is not guaranteed, there is a drawback that the target of diagnosis cannot be limited to RIBI. .

[Object of the Invention] In view of the above-mentioned drawbacks, an object of the present invention is to provide a microinstruction diagnosis method that can perform highly accurate diagnosis by diagnosing instruction buffer-related microinstructions. I'm in the middle of the day.

[Summary of the Invention] The present invention achieves the above object by causing an instruction buffer to hold data output from an arithmetic logic circuit instead of data read from a memory, and loading the held data to an instruction processing unit. It is something to do.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, in which the same parts as those of the conventional example are denoted by the same reference numerals. The code " is an instruction buffer (RIB), and the code 2 is the main memory. The code 3 is a bus controller, and the code 4 is a gate that controls the signal input to the bus controller. The code @5 is loaded from RIBI. It is an instruction processing unit that processes data, and reference numeral 6 is an RIB check circuit. Reference numeral 7 is an arithmetic logic operation circuit (ALU), and data 400 from this circuit 7 is output to RIB1 via a selector 8. .Selector 8 has data 400 ALUI and main memory 2
It is configured to select either one of the data 500 DMI from the . That is, data 400A L LJ 1 is sent from the selector 8 by the first microinstruction 600.
is selectively output, and data 500 DM■ is selectively output by the inverted signal of the @1 microinstruction 800.

The gate 9 receives a request signal 200 output from the RIB check circuit 6, and a j-7 lip-flop (F, /F) 10.
When the control signal 700 is off, the request signal 200 passes through the gate 9 and is input to the gate 4. Flip-flop 10 is set by the second microinstruction 800 and reset by the third microinstruction 100. Note that when the Noritsubu flop 10 is set, the control signal 7
00 is turned on.

Next, the operation of this embodiment will be explained. First, when the third microinstruction 100 indicating a normal instruction fetch is output, this instruction 100 passes through the gate 4 and is input to the bus controller 3 as a bus control signal. As a result, the bus controller 3 gives a read signal 900 to the main memory 2, so that the command in the memory 2 is read out and inputted as data 500 to the selector 8.

Normally, the first microinstruction 600 is not output, so the data 500 is passed from the selector 8, and the RIB
It is input to l and held there. After that, when the fourth microinstruction 300 that executes the instruction stored in RIB1 is input, the contents of RIBI are loaded to the instruction processing unit 5,
One microinstruction is executed. On the other hand, the RIB check circuit 6 monitors the empty state of RIBI, and when it detects that RIB1 is empty, outputs the read request signal 200 of the main memory 2 to the gate 9. At this time, when the third microinstruction 100 described above is output, the flip-flop 10 is reset, and this flip-flop 1
The control signal @700 output from gate 9 to gate 9 is off. Therefore, the signals Q200 pass through gates 9 and 4 to become bus control signals and are input to the bus controller 3. For this purpose, the bus controller 3 provides a read signal 900 to the main memory 2 to read out the instructions in the main memory 2. The subsequent operation is similar to the above operation, and the instruction read here passes through the selector 8 as data 500 and is held in RIB1. This RIB
The instruction from the main memory 2 held in 1 is loaded to the instruction processing unit 5 in the same manner as above, and the next microinstruction is executed as the actual 1':
At the same time, the main memory 2 is
A read request signal 200 is output.

The above operations are repeated to sequentially execute instructions in the main memory 2.

Next, when diagnosing a RIBI-related microinstruction, first the first microinstruction 600 is output, so that the selector 8 receives the data 4 from the arithmetic logic circuit 7.
00ALUI is selected and output to RIBI. When the second microinstruction 800 is output to the RIB1, the data held in the RIB1 is loaded to the instruction processing unit 5 and processed. When the RIB check circuit 6 detects that RIBl is empty, it similarly outputs a read request signal 200 to the gate 9. However, since flip-flop 10 is set by the second microinstruction 800, the output signal 70 from flip-flop 10
0 is turned on and prevents the read request signal 200 from passing through the gate 9. Therefore, since no bus control signal based on the read request signal 200 is input to the bus controller 3, no command is read from the memory 2.

According to this embodiment, the data 4 from the arithmetic logic operation circuit 7
After holding 00 in RIB1, by loading this data to the instruction processing unit 5, the diagnosis can be performed by focusing on the RIBI-related microinstructions (1st to 4th) regardless of the presence or absence of the main memory 2. This can often improve the accuracy of diagnosis.

As described above, according to the microinstruction diagnostic method of the present invention, instead of data read from the main memory, the data output by the arithmetic and logic circuit is held in the instruction buffer, and the held data is loaded to the instruction processing unit. This has the effect of limiting the target of diagnosis to microinstructions related to the instruction buffer and making it possible to perform highly accurate diagnosis.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer to which the microinstruction diagnosis method of the present invention is applied, and FIG. 2 is a block diagram showing an example of a computer to which the conventional microinstruction diagnosis method is applied. 1... Instruction buffer 2... Main memory 3... Bus controller 4
．． 9...Gate 5...Instruction processing unit 6...R
IB check circuit 7...Arithmetic logic operation circuit 8...Selector 10...Flip-flop agent Patent attorney Nori Chika Ken Ken Shu Yama Tama -

Claims (1)

[Claims] a selector provided between the main memory and the instruction buffer; an arithmetic logic circuit connected to the other input of the selector; one microinstruction, a second microinstruction output after the first microinstruction, and means for outputting output data from the instruction buffer to the instruction processing unit; A microinstruction diagnostic method comprising means for suppressing an instruction read request output to the microinstruction diagnostic method.