JPS5936853A - Operation processor - Google Patents

Abstract

PURPOSE:To detect a writing error without reducing processing speed and to improve the reliability of the titled device by writing an arithmetic result in a combined data reading/writing address and immediately comparing the written data with the read-out arithmetic result. CONSTITUTION:The storage address of an arithmetic result by the 1st micro- instruction is held in a storage address register 3. Four bits out of the 1st microinstruction in a microinstruction register 5 are held in an operation mode register 8 to specify the operation of an arithmetic unit 9. In the 1st machine cycle of the succeeding microinstruction, a comparator 12 compares the output data of the arithmetic unit 9 with the data read out by the address indicated by the register 3. If an error is detected in the compared result, a dissidence signal is outputted from a register memory 4. The output signal stops the operation processor to inform the generation of the writing error.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an arithmetic processing device.

[Prior art]

Conventionally, as shown in FIG. 1, an arithmetic processing device selects an address in the register memory 4 indicated by a microinstruction held in a microinstruction register 5 with a selector 6, thereby saving the register memory in the first machine cycle. In the second machine cycle, the data in the register memory 4 is held in the register 2, and in the third machine cycle, the result of the operation in the device 9 is written to the register memory 4. Execution of one microinstruction ended. Therefore, errors when writing to register memory 4 are not detected, or if the parity check function is included, errors can be detected when the data written to register memory 4 is needed, but it is difficult to determine which part of the error occurs. The drawback was that it couldn't be done.

[Purpose of the invention]

An object of the present invention is to provide a register memory for storing calculation results with an address terminal exclusively used for data reading, an address terminal used for both data writing and reading, a data writing terminal, and the data read by the data read/write address and the data read from the data read/write address. Using a register memory that has a comparator that compares data and a terminal that outputs the comparison result of the comparator, the calculation result is stored in the data read/write address, and this written data is immediately read and compared with the calculation result. However, if the comparison results do not match, a write error signal is output and used as a control signal for error processing, increasing reliability and not slowing down processing speed. The goal is to provide equipment.

[Structure of the invention]

According to the present invention, an arithmetic device, first and second registers that temporarily hold first and second input data of the device, and a write address of a register memory that stores arithmetic results are temporarily set. a third register to hold, a read-only address terminal, a read terminal for data read by the read-only address, a read/write address terminal, a data write terminal, and a data write terminal for data read by the read/write address; a register memory having a comparator I that compares the written data with the data of the write terminal, a register memory having a terminal that outputs the comparison result of the comparator, and an arithmetic mode register that holds the arithmetic mode of the arithmetic unit; The address set by the previous microinstruction is held in the third register, and a write error in the register memory can be detected from the comparison result in the first machine cycle of the instruction being executed. A performance processing device is obtained.

Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart explaining the g operation, and Fig. 4 shows details of the register memory in Fig. 2. is the first register/%2 is the second register, 3 is the third register, 4 is the register memory, 5 is the microinstruction register, 7
8 is the read address selector, 8 is the calculation mode register,
9 is a calculation device. In Fig. 4, 11 is an output drive, 12 is a comparator, 13 is a read-only address terminal, 1
4 is a read terminal for data read from an address exclusively for reading, 15 is an address terminal for both reading and writing, and 16
1 is a data write terminal, and 17 is a read terminal for data read by the read/write address. When the microinstruction is held in the microinstruction register 5,
The function code is decoded for each instruction, and the operation of the instruction held in the Moeki microinstruction register 5 is determined.

The first microinstruction (al (INS'l
"(11) is held in the microinstruction register 5, the instruction is executed in three machine cycles (FIG. 3(b)). First, in the first machine cycle, the 32-bit microinstruction register is 8 bits out of 5 become the read address of register memory 4 through selector 7,
The read data is held in register 1 (see Figure 3 (
C)). This read address is held in the register 3 because it becomes the storage address for the calculation result (FIG. 3(f)). In addition, 4 bits in the microinstruction register 5 are held in the operation mode register 8 (FIG. 3(i)), and the operation unit #9
instructs the operation of Next, in the second machine cycle, 8 bits other than the above 8 bits in the microinstruction register 5 are read out through the selector 7 as an address in the register memory 4, and the data is held in the register 2 (@
Figure 3(d)). Next, in the third machine cycle, an arithmetic operation is performed (FIG. 3(e)), and data is written to the address indicated by the register 3 of the register memory 4 using the write pulse shown in FIG. 3(11). Now microinstruction 11 (IN8 T(
The execution of it) is completed.

Next, the microinstruction (I N 81' (z)) shown in FIG. 3(a) is held in the microinstruction register 5 and [I N
8 i' (ll) is similarly executed. In the first machine cycle of the microinstruction (I N 8 T (2)), the operation mode of (INST(IJ) is held in the operation mode register 8, and the storage address of the (INST(i) microinstruction is held in register 3. Then, the output data of the arithmetic unit 90 and the take read at the address indicated by the register 3 are compared by the comparator 12 shown in FIG. is outputted from the register memory 4 as .This output signal causes the arithmetic processing unit to stop and informs that a write error has occurred.

〔Effect of the invention〕

As explained above, the present invention does not reduce processing speed,
If the calculation result written to the register memory is incorrect, a mismatch signal is output, which has the effect of detecting a write error early and improving reliability.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the conventional technology, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a tights and chart showing the operation of the present invention, and Fig. 4 is a block diagram showing an example of the present invention. FIG. 2 is a block diagram of an example of a register memory. 1...First register, 2...Second register, 3...Third register, 4...
...Register memory, 5...Micro instruction register, 7...Read address selector, 8...
... Arithmetic mode register, 9... Arithmetic device,
11...Output driver, 12...Mountain comparator.箭１＠ Ichikyo Ribbon A No. 2＠ １ Yugo and Taepu, page 4

Claims (1)

[Claims] an arithmetic device, first and second registers that temporarily hold first and second input data of the arithmetic device, and a third register that temporarily holds a write address of a register memory that stores a calculation result. , read-only address terminal,
Compare the read terminal of the data read by the read-only address, the terminal of the read/write address, the data write terminal, and the data read by the read/write address and the data of the write terminal. It includes a register memory having a comparator and a terminal for outputting the comparison result of the comparator, and an arithmetic mode register that holds the arithmetic mode of the arithmetic unit, which was set by the previous microinstruction during execution. An arithmetic processing device characterized in that an address is held in the third register and a write error in the register memory can be detected as a comparison result in the first machine cycle of an instruction being executed.