JPS6158049A - Error detection - Google Patents

Abstract

PURPOSE:To decide quickly and easily the register circuit where errors arise by utilizing output information of a means for latching address information and output information of a parity check circuit. CONSTITUTION:A signal outputted from a MPU1 to a bus (a) is converted by an address decoder 3, and a prescribed register circuit 4 is selected with the aid of outputted address information. An address signal is latched by a gate signal obtained by taking a NAND between an RD signal from the MPU1 and an error detecting signal from a parity check circuit 2 in a latch circuit 9. When errors are found in read-out data outputted on a data bus (b), the MPU1 starts executing an error processing routine by an INT signal from the parity check circuit 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a system consisting of a plurality of devices having registers for storing data and a control device controlling the plurality of devices, and particularly relates to a system that includes a plurality of devices having registers for storing data and a control device that controls the plurality of devices. Error detection method for detecting the relevant register With the development of information processing technology, functional configurations that write and store data in registers, etc., and read stored data under the control of microprocessors (hereinafter referred to as MPU), etc. have been developed. There are generally many systems in use (in practical use).

When an error occurs in the data handled by the above-mentioned information processing systems, systems, etc., conventionally, it has been common to only detect the error at the time the error occurs, and then investigate the cause of the error later.

Therefore, it has been desired to put into practical use a system that can easily and quickly determine the cause of an error when it occurs.

[Conventional technology]

A conventional error detection method in a system including a plurality of devices having registers for storing data and a control device controlling the plurality of devices will be described with reference to one drawing.

FIG. 3 shows a block diagram of a system with a conventional error detection scheme. In the figure, a is an address bus, b is a data bus, and ■ is an interrupt signal (hereinafter INT
(referred to as a signal) and ■ indicate address information, respectively.

In the conventional error detection method shown in Fig. 3, the memory (R
Under the control of the operating program of the microprocessor (hereinafter referred to as liver υ) 1 stored in OM) 5, the data stored in memory (RA?I') 6 is retrieved, and the signal output on address bus a is used as an address. The decoder 3 converts it and outputs address information (■) that specifies and controls one of the registers 4a' to 4d' in the plurality of controlled devices 4a to 4d, and outputs address information (for example, register 4a') specified by the address information (■). outputs the data stored on data bus b.

The parity check circuit 2 checks the data output on the data bus b, and if a parity error is detected, outputs the INT signal to the signal ``1PU1''.

The INT signal signal MP [11] immediately executes the interrupt routine, but in order to determine which register 4a' has generated a parity error, it is necessary to use the instruction pointer value saved when executing the general interrupt routine and the MPUI program. (for example.

The register 4a' in which the error occurred is determined.

[Problem that the invention seeks to solve]

The conventional error detection method as described above is used to determine which register 4a' to 4d' has caused the error.

The cause of the error cannot be determined without the troublesome MPUI program analysis, and even analysis is impossible unless the latest assembly list of the program is maintained.

Another problem is that when using the liver υ1 connected to the high-speed clock buses a and b, the value of the instruction pointer where an error occurs cannot be accurately obtained unless the high-speed parity check circuit 2 is used. was there.

Means for Solving Problem C] The present invention aims to realize a new error detection method that solves the above problems.

The problem is that a control device is provided with means for launching address information for data writing/reading control to the register circuit, and when an error occurs in data read by data reading control, the control device launches address information for controlling data writing/reading to the register circuit. This problem is solved by the error detection method according to the present invention, which detects and determines the register circuit in which an error has occurred using the output information of the parity check circuit and the output information of the parity check circuit.

[Function] First, by providing a circuit that latches address information for selecting a plurality of register circuits in the device by the control device (MPIJ), and using the timing at the time of data read as the timing to latch the address information, A high-speed parity check circuit is not required, and the register circuit in which a parity error occurs can be easily determined.

The present invention as described above is particularly effective when developing software-controlled systems and debugging programs.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 1 is a block diagram of a system having an embodiment of the error detection method according to the present invention, and FIG. 2 shows the operation timing of a latch circuit.

In the figure, ■ is the data read signal (RD double signal,
(2) indicates a gate signal, (2) indicates an output signal of a launch circuit, and the same symbols indicate the same objects and contents throughout the figures.

In this embodiment, the signal output from MPUI to bus a is converted by address decoder 3, and the output address information ■
Accordingly, a predetermined register circuit 4 is selected.

Next, the RO signal to the predetermined register circuit 4 is
A predetermined register circuit when issued from the UI.

For example, the address information that selects the register circuit 4a is
is latched by the latch circuit 9, and the register circuit 4a
data reading is started.

Furthermore, the latch circuit 9 receives the RD signal color from the MPUI.

Error detection signal from parity check circuit 2 (IN
Gate signal obtained by NANDing the T signal signal reactor■
The address information ■ is latched.

If there is an error in the read data output on data bus b, the MPUI checks the parity check circuit 2.
Execution of the error handling routine is started by the INT signal (highest priority interrupt) . The address information latched in the latch circuit 9 is held until the error detection signal (INT signal signal) is reset.

It is not necessary to output the error detection signal (INT signal) immediately after the RD signal (■ of MPUI) rises.

It is sufficient to wait until the start of the next data bus cycle. That is, even if a relatively slow parity check circuit 2 is used for an MPUI that operates on high-speed data bus cycles, the two objects of the present invention can be achieved. Incidentally, FIG. 2 shows the timing of this related operation.

Error detection targets in this embodiment are registers 4a' to 4b'
The MP shown in FIGS. 1 and 3 is not limited to
It is also possible to detect errors in the memories 5 and 6 of the UI.

〔Effect of the invention〕

According to the present invention as described above, a register circuit in which an error has occurred can be quickly and easily determined without requiring a high-speed parity check circuit or analyzing an assemble list.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system having an embodiment of the error detection method according to the present invention. Figure 2 shows the operation timing of the latch circuit. FIG. 3 is a block diagram of a system having a conventional error detection method. are shown respectively. In fig. 1 is 1IIpu. 2 is a parity check circuit. 3 is an address decoder circuit. 4a' to 4b' are register circuits. 5 is memory (ROM'), 6 is memory (
RAM). 7 is a NAND circuit, 8 is an output gate circuit. 9 is a latch circuit. are shown respectively.

Claims (1)

[Claims] a plurality of devices having register circuits for storing data;
In a system comprising a control device that has a parity check circuit that checks parity errors in data read from the register circuit and controls the plurality of devices, the control device controls data writing/reading to the register circuit. means for latching address information of the parity check circuit, and when an error occurs in the data read by the data read control, the control device determines whether an error has occurred between the output information of the means and the output information of the parity check circuit. An error detection method characterized by detecting and determining which register circuit is present.